From b03878f68a3bed141bae0e6442996399e55e683d Mon Sep 17 00:00:00 2001
From: b <rowerynaksiezycu@gmail.com>
Date: Sun, 23 Jan 2022 21:57:00 +0100
Subject: [PATCH 1/1] Final version as of 23.1.2022
---
.cproject | 179 +
.project | 28 +
.settings/language.settings.xml | 25 +
.settings/org.eclipse.cdt.codan.core.prefs | 73 +
CMSIS/core/arm_common_tables.h | 136 +
CMSIS/core/arm_const_structs.h | 79 +
CMSIS/core/arm_math.h | 7154 ++++++++++++++++++
CMSIS/core/cmsis_armcc.h | 734 ++
CMSIS/core/cmsis_armcc_V6.h | 1800 +++++
CMSIS/core/cmsis_gcc.h | 1373 ++++
CMSIS/core/core_cm0.h | 798 ++
CMSIS/core/core_cm0plus.h | 914 +++
CMSIS/core/core_cm3.h | 1763 +++++
CMSIS/core/core_cm4.h | 1937 +++++
CMSIS/core/core_cm7.h | 2512 ++++++
CMSIS/core/core_cmFunc.h | 87 +
CMSIS/core/core_cmInstr.h | 87 +
CMSIS/core/core_cmSimd.h | 96 +
CMSIS/core/core_sc000.h | 926 +++
CMSIS/core/core_sc300.h | 1745 +++++
CMSIS/device/stm32l010x4.h | 5803 ++++++++++++++
CMSIS/device/stm32l010x6.h | 5860 ++++++++++++++
CMSIS/device/stm32l010x8.h | 5856 ++++++++++++++
CMSIS/device/stm32l010xb.h | 5932 +++++++++++++++
CMSIS/device/stm32l011xx.h | 5945 +++++++++++++++
CMSIS/device/stm32l021xx.h | 6085 +++++++++++++++
CMSIS/device/stm32l031xx.h | 6090 +++++++++++++++
CMSIS/device/stm32l041xx.h | 6230 +++++++++++++++
CMSIS/device/stm32l051xx.h | 6265 +++++++++++++++
CMSIS/device/stm32l052xx.h | 7349 ++++++++++++++++++
CMSIS/device/stm32l053xx.h | 7509 ++++++++++++++++++
CMSIS/device/stm32l061xx.h | 6405 ++++++++++++++++
CMSIS/device/stm32l062xx.h | 7489 ++++++++++++++++++
CMSIS/device/stm32l063xx.h | 7649 +++++++++++++++++++
CMSIS/device/stm32l071xx.h | 6497 ++++++++++++++++
CMSIS/device/stm32l072xx.h | 7683 +++++++++++++++++++
CMSIS/device/stm32l073xx.h | 7845 +++++++++++++++++++
CMSIS/device/stm32l081xx.h | 6637 ++++++++++++++++
CMSIS/device/stm32l082xx.h | 7823 +++++++++++++++++++
CMSIS/device/stm32l083xx.h | 7985 ++++++++++++++++++++
CMSIS/device/stm32l0xx.h | 238 +
CMSIS/device/system_stm32l0xx.h | 109 +
LinkerScript.ld | 188 +
NUCLEO-L053R8.xml | 19 +
inc/stm32l0xx_it.h | 62 +
klavirko Debug (1).cfg | 36 +
klavirko Debug.cfg | 36 +
license.txt | 5 +
src/klavirko.c | 1089 +++
src/klavirko.h | 287 +
src/klavirko_asm.S | 291 +
src/stm32l053xx_asm.h | 7084 +++++++++++++++++
src/syscalls.c | 204 +
src/system_stm32l0xx.c | 295 +
startup/startup_stm32l053xx.S | 301 +
55 files changed, 167627 insertions(+)
create mode 100644 .cproject
create mode 100644 .project
create mode 100644 .settings/language.settings.xml
create mode 100644 .settings/org.eclipse.cdt.codan.core.prefs
create mode 100644 CMSIS/core/arm_common_tables.h
create mode 100644 CMSIS/core/arm_const_structs.h
create mode 100644 CMSIS/core/arm_math.h
create mode 100644 CMSIS/core/cmsis_armcc.h
create mode 100644 CMSIS/core/cmsis_armcc_V6.h
create mode 100644 CMSIS/core/cmsis_gcc.h
create mode 100644 CMSIS/core/core_cm0.h
create mode 100644 CMSIS/core/core_cm0plus.h
create mode 100644 CMSIS/core/core_cm3.h
create mode 100644 CMSIS/core/core_cm4.h
create mode 100644 CMSIS/core/core_cm7.h
create mode 100644 CMSIS/core/core_cmFunc.h
create mode 100644 CMSIS/core/core_cmInstr.h
create mode 100644 CMSIS/core/core_cmSimd.h
create mode 100644 CMSIS/core/core_sc000.h
create mode 100644 CMSIS/core/core_sc300.h
create mode 100644 CMSIS/device/stm32l010x4.h
create mode 100644 CMSIS/device/stm32l010x6.h
create mode 100644 CMSIS/device/stm32l010x8.h
create mode 100644 CMSIS/device/stm32l010xb.h
create mode 100644 CMSIS/device/stm32l011xx.h
create mode 100644 CMSIS/device/stm32l021xx.h
create mode 100644 CMSIS/device/stm32l031xx.h
create mode 100644 CMSIS/device/stm32l041xx.h
create mode 100644 CMSIS/device/stm32l051xx.h
create mode 100644 CMSIS/device/stm32l052xx.h
create mode 100644 CMSIS/device/stm32l053xx.h
create mode 100644 CMSIS/device/stm32l061xx.h
create mode 100644 CMSIS/device/stm32l062xx.h
create mode 100644 CMSIS/device/stm32l063xx.h
create mode 100644 CMSIS/device/stm32l071xx.h
create mode 100644 CMSIS/device/stm32l072xx.h
create mode 100644 CMSIS/device/stm32l073xx.h
create mode 100644 CMSIS/device/stm32l081xx.h
create mode 100644 CMSIS/device/stm32l082xx.h
create mode 100644 CMSIS/device/stm32l083xx.h
create mode 100644 CMSIS/device/stm32l0xx.h
create mode 100644 CMSIS/device/system_stm32l0xx.h
create mode 100644 LinkerScript.ld
create mode 100644 NUCLEO-L053R8.xml
create mode 100644 inc/stm32l0xx_it.h
create mode 100644 klavirko Debug (1).cfg
create mode 100644 klavirko Debug.cfg
create mode 100644 license.txt
create mode 100644 src/klavirko.c
create mode 100644 src/klavirko.h
create mode 100644 src/klavirko_asm.S
create mode 100644 src/stm32l053xx_asm.h
create mode 100644 src/syscalls.c
create mode 100644 src/system_stm32l0xx.c
create mode 100644 startup/startup_stm32l053xx.S
diff --git a/.cproject b/.cproject
new file mode 100644
index 0000000..bb60a72
--- /dev/null
+++ b/.cproject
@@ -0,0 +1,179 @@
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+ <scannerConfigBuildInfo instanceId="fr.ac6.managedbuild.config.gnu.cross.exe.release.1216733401;fr.ac6.managedbuild.config.gnu.cross.exe.release.1216733401.;fr.ac6.managedbuild.tool.gnu.cross.c.compiler.400187759;fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c.473697007">
+ <autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
+ </scannerConfigBuildInfo>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+ <storageModule moduleId="refreshScope" versionNumber="2">
+ <configuration configurationName="Debug">
+ <resource resourceType="PROJECT" workspacePath="/klavirko"/>
+ </configuration>
+ <configuration configurationName="Release">
+ <resource resourceType="PROJECT" workspacePath="/klavirko"/>
+ </configuration>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+ <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+</cproject>
diff --git a/.project b/.project
new file mode 100644
index 0000000..a6d00c6
--- /dev/null
+++ b/.project
@@ -0,0 +1,28 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>klavirko</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <triggers>full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ <nature>fr.ac6.mcu.ide.core.MCUProjectNature</nature>
+ <nature>fr.ac6.mcu.ide.core.MCUSingleCoreProjectNature</nature>
+ </natures>
+</projectDescription>
diff --git a/.settings/language.settings.xml b/.settings/language.settings.xml
new file mode 100644
index 0000000..b9f7b41
--- /dev/null
+++ b/.settings/language.settings.xml
@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+ <configuration id="fr.ac6.managedbuild.config.gnu.cross.exe.debug.953511369" name="Debug">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ <provider class="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" console="false" env-hash="1396705008450768097" id="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="Ac6 SW4 STM32 MCU Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ </extension>
+ </configuration>
+ <configuration id="fr.ac6.managedbuild.config.gnu.cross.exe.release.1216733401" name="Release">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ <provider class="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" console="false" env-hash="1396705008450768097" id="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="Ac6 SW4 STM32 MCU Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ </extension>
+ </configuration>
+</project>
diff --git a/.settings/org.eclipse.cdt.codan.core.prefs b/.settings/org.eclipse.cdt.codan.core.prefs
new file mode 100644
index 0000000..81deb5b
--- /dev/null
+++ b/.settings/org.eclipse.cdt.codan.core.prefs
@@ -0,0 +1,73 @@
+eclipse.preferences.version=1
+fr.ac6.mcu.ide.source.checker.libnano.problem=Error
+fr.ac6.mcu.ide.source.checker.libnano.problem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Float formatting support\\")"}
+org.eclipse.cdt.codan.checkers.errnoreturn=Warning
+org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return\\")",implicit\=>false}
+org.eclipse.cdt.codan.checkers.errreturnvalue=Error
+org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused return value\\")"}
+org.eclipse.cdt.codan.checkers.nocommentinside=-Error
+org.eclipse.cdt.codan.checkers.nocommentinside.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Nesting comments\\")"}
+org.eclipse.cdt.codan.checkers.nolinecomment=-Error
+org.eclipse.cdt.codan.checkers.nolinecomment.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Line comments\\")"}
+org.eclipse.cdt.codan.checkers.noreturn=Error
+org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return value\\")",implicit\=>false}
+org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error
+org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Abstract class cannot be instantiated\\")"}
+org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem=Error
+org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Ambiguous problem\\")"}
+org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment in condition\\")"}
+org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem=Error
+org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment to itself\\")"}
+org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No break at end of case\\")",no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false}
+org.eclipse.cdt.codan.internal.checkers.CatchByReference=Warning
+org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Catching by reference is recommended\\")",unknown\=>false,exceptions\=>()}
+org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem=Error
+org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Circular inheritance\\")"}
+org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization=Warning
+org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class members should be properly initialized\\")",skip\=>true}
+org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Field cannot be resolved\\")"}
+org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function cannot be resolved\\")"}
+org.eclipse.cdt.codan.internal.checkers.InvalidArguments=Error
+org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid arguments\\")"}
+org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem=Error
+org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid template argument\\")"}
+org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem=Error
+org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Label statement not found\\")"}
+org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem=Error
+org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Member declaration not found\\")"}
+org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Method cannot be resolved\\")"}
+org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker=-Info
+org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Name convention for function\\")",pattern\=>"^[a-z]",macro\=>true,exceptions\=>()}
+org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class has a virtual method and non-virtual destructor\\")"}
+org.eclipse.cdt.codan.internal.checkers.OverloadProblem=Error
+org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid overload\\")"}
+org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem=Error
+org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redeclaration\\")"}
+org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redefinition\\")"}
+org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return with parenthesis\\")"}
+org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem=-Warning
+org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Format String Vulnerability\\")"}
+org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Statement has no effect\\")",macro\=>true,exceptions\=>()}
+org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suggested parenthesis around expression\\")",paramNot\=>false}
+org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suspicious semicolon\\")",else\=>false,afterelse\=>false}
+org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Type cannot be resolved\\")"}
+org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused function declaration\\")",macro\=>true}
+org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused static function\\")",macro\=>true}
+org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem=Warning
+org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused variable declaration in file scope\\")",macro\=>true,exceptions\=>("@(\#)","$Id")}
+org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error
+org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"}
diff --git a/CMSIS/core/arm_common_tables.h b/CMSIS/core/arm_common_tables.h
new file mode 100644
index 0000000..d5d7241
--- /dev/null
+++ b/CMSIS/core/arm_common_tables.h
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. October 2015
+* $Revision: V.1.4.5 a
+*
+* Project: CMSIS DSP Library
+* Title: arm_common_tables.h
+*
+* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+/* extern const q31_t realCoefAQ31[1024]; */
+/* extern const q31_t realCoefBQ31[1024]; */
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /* ARM_COMMON_TABLES_H */
diff --git a/CMSIS/core/arm_const_structs.h b/CMSIS/core/arm_const_structs.h
new file mode 100644
index 0000000..54595f5
--- /dev/null
+++ b/CMSIS/core/arm_const_structs.h
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_const_structs.h
+*
+* Description: This file has constant structs that are initialized for
+* user convenience. For example, some can be given as
+* arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/CMSIS/core/arm_math.h b/CMSIS/core/arm_math.h
new file mode 100644
index 0000000..580cbbd
--- /dev/null
+++ b/CMSIS/core/arm_math.h
@@ -0,0 +1,7154 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+*
+* $Date: 20. October 2015
+* $Revision: V1.4.5 b
+*
+* Project: CMSIS DSP Library
+* Title: arm_math.h
+*
+* Description: Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+ \mainpage CMSIS DSP Software Library
+ *
+ * Introduction
+ * ------------
+ *
+ * This user manual describes the CMSIS DSP software library,
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.
+ *
+ * The library is divided into a number of functions each covering a specific category:
+ * - Basic math functions
+ * - Fast math functions
+ * - Complex math functions
+ * - Filters
+ * - Matrix functions
+ * - Transforms
+ * - Motor control functions
+ * - Statistical functions
+ * - Support functions
+ * - Interpolation functions
+ *
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+ * 32-bit integer and 32-bit floating-point values.
+ *
+ * Using the Library
+ * ------------
+ *
+ * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+ * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)
+ * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)
+ * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+ * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+ * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+ * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+ * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)
+ * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)
+ *
+ * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file <code> arm_math.h</code> for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+ *
+ * Examples
+ * --------
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * Toolchain Support
+ * ------------
+ *
+ * The library has been developed and tested with MDK-ARM version 5.14.0.0
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * Building the Library
+ * ------------
+ *
+ * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+ * - arm_cortexM_math.uvprojx
+ *
+ *
+ * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+ *
+ * Pre-processor Macros
+ * ------------
+ *
+ * Each library project have differant pre-processor macros.
+ *
+ * - UNALIGNED_SUPPORT_DISABLE:
+ *
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+ *
+ * - ARM_MATH_BIG_ENDIAN:
+ *
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * - ARM_MATH_MATRIX_CHECK:
+ *
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+ *
+ * - ARM_MATH_ROUNDING:
+ *
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions
+ *
+ * - ARM_MATH_CMx:
+ *
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+ * ARM_MATH_CM7 for building the library on cortex-M7.
+ *
+ * - __FPU_PRESENT:
+ *
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+ *
+ * <hr>
+ * CMSIS-DSP in ARM::CMSIS Pack
+ * -----------------------------
+ *
+ * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+ * |File/Folder |Content |
+ * |------------------------------|------------------------------------------------------------------------|
+ * |\b CMSIS\\Documentation\\DSP | This documentation |
+ * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |
+ * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |
+ * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |
+ *
+ * <hr>
+ * Revision History of CMSIS-DSP
+ * ------------
+ * Please refer to \ref ChangeLog_pg.
+ *
+ * Copyright Notice
+ * ------------
+ *
+ * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+ */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ * typedef struct
+ * {
+ * uint16_t numRows; // number of rows of the matrix.
+ * uint16_t numCols; // number of columns of the matrix.
+ * float32_t *pData; // points to the data of the matrix.
+ * } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data. The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ * pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ * <pre>
+ * ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ * ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ * ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings. By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* ignore some GCC warnings */
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+ #include "core_cm7.h"
+#elif defined (ARM_MATH_CM4)
+ #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+ #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+ #include "core_cm0.h"
+ #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+ #include "core_cm0plus.h"
+ #define ARM_MATH_CM0_FAMILY
+#else
+ #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
+#endif
+
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+#define PI 3.14159265358979f
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define FAST_MATH_TABLE_SIZE 512
+#define FAST_MATH_Q31_SHIFT (32 - 10)
+#define FAST_MATH_Q15_SHIFT (16 - 10)
+#define CONTROLLER_Q31_SHIFT (32 - 9)
+#define TABLE_SIZE 256
+#define TABLE_SPACING_Q31 0x400000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+ /**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ #define ALIGN4
+#else
+ #if defined (__GNUC__)
+ #define ALIGN4 __attribute__((aligned(4)))
+ #else
+ #define ALIGN4 __align(4)
+ #endif
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+ /**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if defined __CC_ARM
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED __attribute__((unused))
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+
+#elif defined __GNUC__
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+
+#elif defined __ICCARM__
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED
+
+#elif defined __CSMC__
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED
+
+#elif defined __TASKING__
+ #define __SIMD32_TYPE __unaligned int32_t
+ #define CMSIS_UNUSED
+
+#else
+ #error Unknown compiler
+#endif
+
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
+#define __SIMD64(addr) (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+
+#endif
+
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ static __INLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ static __INLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ static __INLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ static __INLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+ static __INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y)));
+ }
+
+/*
+ #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )
+ #define __CLZ __clz
+ #endif
+ */
+/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) )
+ static __INLINE uint32_t __CLZ(
+ q31_t data);
+
+ static __INLINE uint32_t __CLZ(
+ q31_t data)
+ {
+ uint32_t count = 0;
+ uint32_t mask = 0x80000000;
+
+ while((data & mask) == 0)
+ {
+ count += 1u;
+ mask = mask >> 1u;
+ }
+
+ return (count);
+ }
+#endif
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+
+ static __INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ q31_t * pRecipTable)
+ {
+ q31_t out;
+ uint32_t tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if(in > 0)
+ {
+ signBits = ((uint32_t) (__CLZ( in) - 1));
+ }
+ else
+ {
+ signBits = ((uint32_t) (__CLZ(-in) - 1));
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 24);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++)
+ {
+ tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+ tempVal = 0x7FFFFFFFu - tempVal;
+ /* 1.31 with exp 1 */
+ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+ out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1u);
+ }
+
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+ static __INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ q15_t * pRecipTable)
+ {
+ q15_t out = 0;
+ uint32_t tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if(in > 0)
+ {
+ signBits = ((uint32_t)(__CLZ( in) - 17));
+ }
+ else
+ {
+ signBits = ((uint32_t)(__CLZ(-in) - 17));
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 8);
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++)
+ {
+ tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFFu - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+ }
+
+
+ /*
+ * @brief C custom defined intrinisic function for only M0 processors
+ */
+#if defined(ARM_MATH_CM0_FAMILY)
+ static __INLINE q31_t __SSAT(
+ q31_t x,
+ uint32_t y)
+ {
+ int32_t posMax, negMin;
+ uint32_t i;
+
+ posMax = 1;
+ for (i = 0; i < (y - 1); i++)
+ {
+ posMax = posMax * 2;
+ }
+
+ if(x > 0)
+ {
+ posMax = (posMax - 1);
+
+ if(x > posMax)
+ {
+ x = posMax;
+ }
+ }
+ else
+ {
+ negMin = -posMax;
+
+ if(x < negMin)
+ {
+ x = negMin;
+ }
+ }
+ return (x);
+ }
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+ /*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+ /*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QADD8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QSUB8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
+ q31_t r = 0, s = 0;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SHADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SHSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SHASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __QSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SHSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMUSDX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+ /*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMUADX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+ static __INLINE int32_t __QADD(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+ static __INLINE int32_t __QSUB(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMLAD(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMLADX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMLSDX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+ static __INLINE uint64_t __SMLALD(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+ static __INLINE uint64_t __SMLALDX(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMUAD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SMUSD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+ static __INLINE uint32_t __SXTB16(
+ uint32_t x)
+ {
+ return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+ ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
+ }
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] S points to an instance of the Q7 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] S points to an instance of the Q15 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * <code>numTaps</code> is not a supported value.
+ */
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] S points to an instance of the floating-point FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q15;
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_casd_df1_inst_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float64_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f64;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q31;
+
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+ arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+ void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the q15 PID Control structure
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+ const arm_cfft_instance_q15 * S,
+ q15_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+ const arm_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_f32;
+
+ void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q15;
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q31;
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct
+ {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+ */
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q31 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q15 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+ arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f64;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64 * S,
+ float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64 * S,
+ uint8_t numStages,
+ float64_t * pCoeffs,
+ float64_t * pState);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ */
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+ void arm_correlate_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+ void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+ void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+ void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_correlate_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cos output.
+ */
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal);
+
+
+ /**
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cosine output.
+ */
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the PID control data structure. <code>in</code>
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ * <pre>
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd </pre>
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ */
+ static __INLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+ {
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+ static __INLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+ {
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31u);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ * @brief Process function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+ static __INLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+ {
+ q63_t acc;
+ q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+ __SIMD32_TYPE *vstate;
+
+ /* Implementation of PID controller */
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ vstate = __SIMD32_CONST(S->state);
+ acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
+#else
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+ /**
+ * @} end of PID group
+ */
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f64(
+ const arm_matrix_instance_f64 * src,
+ arm_matrix_instance_f64 * dst);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+ * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+ * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+ * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+ * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate <code>a</code>
+ * @param[in] Ib input three-phase coordinate <code>b</code>
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ */
+ static __INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+ }
+
+
+ /**
+ * @brief Clarke transform for Q31 version
+ * @param[in] Ia input three-phase coordinate <code>a</code>
+ * @param[in] Ib input three-phase coordinate <code>b</code>
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+ static __INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+ * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate <code>a</code>
+ * @param[out] pIb points to output three-phase coordinate <code>b</code>
+ */
+ static __INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+ }
+
+
+ /**
+ * @brief Inverse Clarke transform for Q31 version
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate <code>a</code>
+ * @param[out] pIb points to output three-phase coordinate <code>b</code>
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+ static __INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+ * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+ static __INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+ }
+
+
+ /**
+ * @brief Park transform for Q31 version
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+ static __INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+ * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ */
+ static __INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+ }
+
+
+ /**
+ * @brief Inverse Park transform for Q31 version
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+ static __INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ * <pre>
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ * </pre>
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+ * <code>x</code> is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+ static __INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if(i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if((uint32_t)i >= S->nValues)
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ static __INLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (q31_t)0xFFF00000) >> 20);
+
+ if(index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1u);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ static __INLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (int32_t)0xFFF00000) >> 20);
+
+ if(index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (q15_t) (y >> 20);
+ }
+ }
+
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+ static __INLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0)
+ {
+ return (pYData[0]);
+ }
+ index = (x >> 20) & 0xfff;
+
+ if(index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (q7_t) (y >> 20);
+ }
+ }
+
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+ float32_t arm_sin_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q31_t arm_sin_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q15_t arm_sin_q15(
+ q15_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+ float32_t arm_cos_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q31_t arm_cos_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ * <pre>
+ * x1 = x0 - f(x0)/f'(x0)
+ * </pre>
+ * where <code>x1</code> is the current estimate,
+ * <code>x0</code> is the previous estimate, and
+ * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+ * For the square root function, the algorithm reduces to:
+ * <pre>
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ * </pre>
+ */
+
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+ /**
+ * @brief Floating-point square root function.
+ * @param[in] in input value.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ static __INLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+ {
+ if(in >= 0.0f)
+ {
+
+#if (__FPU_USED == 1) && defined ( __CC_ARM )
+ *pOut = __sqrtf(in);
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined(__GNUC__)
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
+ __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+ }
+
+
+ /**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+ static __INLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ static __INLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (int32_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+ static __INLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ static __INLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q15_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+ static __INLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ static __INLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q7_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[in] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * <b>Algorithm</b>
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ * <pre>
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ * </pre>
+ *
+ * \par
+ * where <code>numRows</code> specifies the number of rows in the table;
+ * <code>numCols</code> specifies the number of columns in the table;
+ * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+ * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+ *
+ * \par
+ * Let <code>(x, y)</code> specify the desired interpolation point. Then define:
+ * <pre>
+ * XF = floor(x)
+ * YF = floor(y)
+ * </pre>
+ * \par
+ * The interpolated output point is computed as:
+ * <pre>
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ * </pre>
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+ /**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+
+ /**
+ *
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+ static __INLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+ {
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+ }
+
+
+ /**
+ *
+ * @brief Q31 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ static __INLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
+ x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
+ y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return ((q31_t)(acc << 2));
+ }
+
+
+ /**
+ * @brief Q15 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ static __INLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+ acc = ((q63_t) out * (0xFFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return ((q15_t)(acc >> 36));
+ }
+
+
+ /**
+ * @brief Q7 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ static __INLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return ((q7_t)(acc >> 40));
+ }
+
+ /**
+ * @} end of BilinearInterpolate group
+ */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM )
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("push") \
+ _Pragma ("O1")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define LOW_OPTIMIZATION_EXIT \
+ _Pragma ("pop")
+ #else
+ #define LOW_OPTIMIZATION_EXIT
+ #endif
+
+ /* Enter low optimization region - place directly above function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+ #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__)
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define LOW_OPTIMIZATION_EXIT
+
+ /* Enter low optimization region - place directly above function definition */
+ #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #endif
+
+ /* Exit low optimization region - place directly after end of function definition */
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__CSMC__)
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__TASKING__)
+ #define LOW_OPTIMIZATION_ENTER
+ #define LOW_OPTIMIZATION_EXIT
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/CMSIS/core/cmsis_armcc.h b/CMSIS/core/cmsis_armcc.h
new file mode 100644
index 0000000..f2bb66a
--- /dev/null
+++ b/CMSIS/core/cmsis_armcc.h
@@ -0,0 +1,734 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+
+#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#endif /* (__CORTEX_M >= 0x04) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/CMSIS/core/cmsis_armcc_V6.h b/CMSIS/core/cmsis_armcc_V6.h
new file mode 100644
index 0000000..d714e9b
--- /dev/null
+++ b/CMSIS/core/cmsis_armcc_V6.h
@@ -0,0 +1,1800 @@
+/**************************************************************************//**
+ * @file cmsis_armcc_V6.h
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_ARMCC_V6_H
+#define __CMSIS_ARMCC_V6_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get IPSR Register (non-secure)
+ \details Returns the content of the non-secure IPSR Register when in secure state.
+ \return IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get APSR Register (non-secure)
+ \details Returns the content of the non-secure APSR Register when in secure state.
+ \return APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get xPSR Register (non-secure)
+ \details Returns the content of the non-secure xPSR Register when in secure state.
+ \return xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp");
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp");
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Base Priority with condition (non_secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+
+#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
+
+
+#if (__ARM_ARCH_8M__ == 1U)
+
+/**
+ \brief Get Process Stack Pointer Limit
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* (__ARM_ARCH_8M__ == 1U) */
+
+
+#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */
+
+/**
+ \brief Get FPSCR
+ \details eturns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#define __get_FPSCR __builtin_arm_get_fpscr
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ uint32_t result;
+
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+#endif
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get FPSCR (non-secure)
+ \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state.
+ \return Floating Point Status/Control register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ uint32_t result;
+
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+#endif
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#define __set_FPSCR __builtin_arm_set_fpscr
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+#endif
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set FPSCR (non-secure)
+ \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+#endif
+
+#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF);
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF);
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF);
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __builtin_bswap32
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+ /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+ int32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+ /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return(result);
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+/*#define __SSAT __builtin_arm_ssat*/
+#define __SSAT(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+#if 0
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+#endif
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
+
+
+#if (__ARM_ARCH_8M__ == 1U)
+
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* (__ARM_ARCH_8M__ == 1U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1U) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_V6_H */
diff --git a/CMSIS/core/cmsis_gcc.h b/CMSIS/core/cmsis_gcc.h
new file mode 100644
index 0000000..d868f2e
--- /dev/null
+++ b/CMSIS/core/cmsis_gcc.h
@@ -0,0 +1,1373 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__CORTEX_M >= 0x03U)
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03U) */
+
+
+#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ uint32_t result;
+
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (short)__builtin_bswap16(value);
+#else
+ int32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return(result);
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x04) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* __CMSIS_GCC_H */
diff --git a/CMSIS/core/core_cm0.h b/CMSIS/core/core_cm0.h
new file mode 100644
index 0000000..fdee521
--- /dev/null
+++ b/CMSIS/core/core_cm0.h
@@ -0,0 +1,798 @@
+/**************************************************************************//**
+ * @file core_cm0.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M0
+ @{
+ */
+
+/* CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0_REV
+ #define __CM0_REV 0x0000U
+ #warning "__CM0_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ uint32_t RESERVED0;
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/CMSIS/core/core_cm0plus.h b/CMSIS/core/core_cm0plus.h
new file mode 100644
index 0000000..7614450
--- /dev/null
+++ b/CMSIS/core/core_cm0plus.h
@@ -0,0 +1,914 @@
+/**************************************************************************//**
+ * @file core_cm0plus.h
+ * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex-M0+
+ @{
+ */
+
+/* CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+ __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM0PLUS_REV
+ #define __CM0PLUS_REV 0x0000U
+ #warning "__CM0PLUS_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 0U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+#if (__VTOR_PRESENT == 1U)
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+#else
+ uint32_t RESERVED0;
+#endif
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED1;
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the Cortex-M0+ header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/CMSIS/core/core_cm3.h b/CMSIS/core/core_cm3.h
new file mode 100644
index 0000000..34ed84c
--- /dev/null
+++ b/CMSIS/core/core_cm3.h
@@ -0,0 +1,1763 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03U) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200U
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201U) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U))
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/CMSIS/core/core_cm4.h b/CMSIS/core/core_cm4.h
new file mode 100644
index 0000000..01cb73b
--- /dev/null
+++ b/CMSIS/core/core_cm4.h
@@ -0,0 +1,1937 @@
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M4
+ @{
+ */
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x04U) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000U
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1U)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/CMSIS/core/core_cm7.h b/CMSIS/core/core_cm7.h
new file mode 100644
index 0000000..20963c1
--- /dev/null
+++ b/CMSIS/core/core_cm7.h
@@ -0,0 +1,2512 @@
+/**************************************************************************//**
+ * @file core_cm7.h
+ * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M7
+ @{
+ */
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+ __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x07U) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM7_REV
+ #define __CM7_REV 0x0000U
+ #warning "__CM7_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ICACHE_PRESENT
+ #define __ICACHE_PRESENT 0U
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DCACHE_PRESENT
+ #define __DCACHE_PRESENT 0U
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DTCM_PRESENT
+ #define __DTCM_PRESENT 0U
+ #warning "__DTCM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[1U];
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED3[93U];
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15U];
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
+ uint32_t RESERVED5[1U];
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1U];
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6U];
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1U];
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED3[981U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1U)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = SCB->MVFR0;
+ if ((mvfr0 & 0x00000FF0UL) == 0x220UL)
+ {
+ return 2UL; /* Double + Single precision FPU */
+ }
+ else if ((mvfr0 & 0x00000FF0UL) == 0x020UL)
+ {
+ return 1UL; /* Single precision FPU */
+ }
+ else
+ {
+ return 0UL; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## Cache functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions
+ \brief Functions that configure Instruction and Data cache.
+ @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
+
+
+/**
+ \brief Enable I-Cache
+ \details Turns on I-Cache
+ */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+ #if (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable I-Cache
+ \details Turns off I-Cache
+ */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+ #if (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate I-Cache
+ \details Invalidates I-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+ #if (__ICACHE_PRESENT == 1U)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL;
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Enable D-Cache
+ \details Turns on D-Cache
+ */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+ __DSB();
+
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Disable D-Cache
+ \details Turns off D-Cache
+ */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Invalidate D-Cache
+ \details Invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean D-Cache
+ \details Cleans D-Cache
+ */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief Clean & Invalidate D-Cache
+ \details Cleans and Invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ uint32_t ccsidr;
+ uint32_t sets;
+ uint32_t ways;
+
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
+ __DSB();
+
+ ccsidr = SCB->CCSIDR;
+
+ /* clean & invalidate D-Cache */
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ do {
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ do {
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
+ #if defined ( __CC_ARM )
+ __schedule_barrier();
+ #endif
+ } while (ways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Invalidate by address
+ \details Invalidates D-Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t)addr;
+ int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCIMVAC = op_addr;
+ op_addr += linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean by address
+ \details Cleans D-Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if (__DCACHE_PRESENT == 1)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t) addr;
+ int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCCMVAC = op_addr;
+ op_addr += linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \brief D-Cache Clean and Invalidate by address
+ \details Cleans and invalidates D_Cache for the given address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if (__DCACHE_PRESENT == 1U)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t) addr;
+ int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCCIMVAC = op_addr;
+ op_addr += linesize;
+ op_size -= linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/CMSIS/core/core_cmFunc.h b/CMSIS/core/core_cmFunc.h
new file mode 100644
index 0000000..ca319a5
--- /dev/null
+++ b/CMSIS/core/core_cmFunc.h
@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+ #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+ #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+ #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/CMSIS/core/core_cmInstr.h b/CMSIS/core/core_cmInstr.h
new file mode 100644
index 0000000..a0a5064
--- /dev/null
+++ b/CMSIS/core/core_cmInstr.h
@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+ #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+ #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+ #include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/CMSIS/core/core_cmSimd.h b/CMSIS/core/core_cmSimd.h
new file mode 100644
index 0000000..4d76bf9
--- /dev/null
+++ b/CMSIS/core/core_cmSimd.h
@@ -0,0 +1,96 @@
+/**************************************************************************//**
+ * @file core_cmSimd.h
+ * @brief CMSIS Cortex-M SIMD Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if defined ( __CC_ARM )
+ #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+ #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+ #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+ #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+ /*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+ #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
diff --git a/CMSIS/core/core_sc000.h b/CMSIS/core/core_sc000.h
new file mode 100644
index 0000000..ea16bf3
--- /dev/null
+++ b/CMSIS/core/core_sc000.h
@@ -0,0 +1,926 @@
+/**************************************************************************//**
+ * @file core_sc000.h
+ * @brief CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup SC000
+ @{
+ */
+
+/* CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+ __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC (000U) /*!< Cortex secure core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC000_REV
+ #define __SC000_REV 0x0000U
+ #warning "__SC000_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 2U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[31U];
+ __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[31U];
+ __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[31U];
+ __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[31U];
+ uint32_t RESERVED4[64U];
+ __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
+} NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ uint32_t RESERVED1[154U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+ Therefore they are not covered by the SC000 header file.
+ @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+ else
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/CMSIS/core/core_sc300.h b/CMSIS/core/core_sc300.h
new file mode 100644
index 0000000..820cef4
--- /dev/null
+++ b/CMSIS/core/core_sc300.h
@@ -0,0 +1,1745 @@
+/**************************************************************************//**
+ * @file core_sc300.h
+ * @brief CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup SC3000
+ @{
+ */
+
+/* CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+ __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC (300U) /*!< Cortex secure core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __SC300_REV
+ #define __SC300_REV 0x0000U
+ #warning "__SC300_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED1[129U];
+ __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/CMSIS/device/stm32l010x4.h b/CMSIS/device/stm32l010x4.h
new file mode 100644
index 0000000..ff1d875
--- /dev/null
+++ b/CMSIS/device/stm32l010x4.h
@@ -0,0 +1,5803 @@
+/**
+ ******************************************************************************
+ * @file stm32l010x4.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for stm32l010x4 devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright(c) 2018 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l010x4
+ * @{
+ */
+
+#ifndef __STM32L010x4_H
+#define __STM32L010x4_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 0U /*!< STM32L0xx provides no MPU */
+#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
+#define __NVIC_PRIO_BITS 2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief stm32l010x4 Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+/*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
+
+/****** STM32L-0 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */
+ RCC_IRQn = 4, /*!< RCC Interrupt */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
+ ADC1_IRQn = 12, /*!< ADC1 Interrupt */
+ LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 Interrupt */
+ TIM21_IRQn = 20, /*!< TIM21 Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ USART2_IRQn = 28, /*!< USART2 Interrupt */
+ LPUART1_IRQn = 29, /*!< LPUART1 Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0plus.h"
+#include "system_stm32l0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+ uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+} ADC_Common_TypeDef;
+
+
+
+/**
+* @brief CRC calculation unit
+*/
+
+typedef struct
+{
+__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+uint8_t RESERVED0; /*!< Reserved, 0x05 */
+uint16_t RESERVED1; /*!< Reserved, 0x06 */
+__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+uint32_t RESERVED2; /*!< Reserved, 0x0C */
+__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
+} DMA_Request_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
+ __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
+ __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
+ __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
+ __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
+ __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
+ __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
+ __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
+ __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
+ __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
+} OB_TypeDef;
+
+
+/**
+ * @brief General Purpose IO
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief LPTIMIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+} LPTIM_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+ * @brief Independent WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
+ __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
+ __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
+ __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
+ __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
+ __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
+ __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
+ __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
+ __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
+ __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
+ __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */
+
+#define DATA_EEPROM_BASE (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
+#define DATA_EEPROM_END (0x0808007FUL) /*!< DATA EEPROM end address in the alias region */
+#define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */
+#define SRAM_SIZE_MAX (0x00000800UL) /*!< maximum SRAM size (up to 2KBytes) */
+
+#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000UL)
+
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
+#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800UL)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
+#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL)
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL)
+#define TIM21_BASE (APBPERIPH_BASE + 0x00010800UL)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708UL)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
+#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL)
+
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
+#define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */
+#define FLASHSIZE_BASE (0x1FF8007CUL) /*!< FLASH Size register base address */
+#define UID_BASE (0x1FF80050UL) /*!< Unique device ID register base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
+
+#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL)
+#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL)
+#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
+/* Legacy defines */
+#define ADC ADC1_COMMON
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_EOCAL_Pos (11U)
+#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
+#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
+#define ADC_ISR_AWD_Pos (7U)
+#define ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
+#define ADC_ISR_EOSEQ_Pos (3U)
+#define ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_EOCALIE_Pos (11U)
+#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
+#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
+#define ADC_IER_AWDIE_Pos (7U)
+#define ADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE_Pos (3U)
+#define ADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH_Pos (26U)
+#define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
+#define ADC_CFGR1_AWDEN_Pos (23U)
+#define ADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL_Pos (22U)
+#define ADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN_Pos (16U)
+#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF_Pos (15U)
+#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
+#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT_Pos (14U)
+#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
+#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT_Pos (13U)
+#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD_Pos (12U)
+#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN_Pos (10U)
+#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
+#define ADC_CFGR1_EXTSEL_Pos (6U)
+#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
+#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
+#define ADC_CFGR1_ALIGN_Pos (5U)
+#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
+#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
+#define ADC_CFGR1_RES_Pos (3U)
+#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
+#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
+#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
+#define ADC_CFGR1_SCANDIR_Pos (2U)
+#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG_Pos (1U)
+#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
+#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN_Pos (0U)
+#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
+#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_TOVS_Pos (9U)
+#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
+#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+#define ADC_CFGR2_OVSR_Pos (2U)
+#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
+#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+#define ADC_CFGR2_OVSE_Pos (0U)
+#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
+#define ADC_CFGR2_CKMODE_Pos (30U)
+#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
+#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
+#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
+#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
+
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP_Pos (0U)
+#define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
+#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
+#define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
+#define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define ADC_SMPR_SMPR ADC_SMPR_SMP
+#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
+#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
+#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT_Pos (16U)
+#define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
+#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
+#define ADC_TR_LT_Pos (0U)
+#define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL_Pos (0U)
+#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
+#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
+#define ADC_CHSELR_CHSEL18_Pos (18U)
+#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17_Pos (17U)
+#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
+#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL15_Pos (15U)
+#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
+#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14_Pos (14U)
+#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
+#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13_Pos (13U)
+#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
+#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12_Pos (12U)
+#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
+#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11_Pos (11U)
+#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
+#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10_Pos (10U)
+#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
+#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9_Pos (9U)
+#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
+#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8_Pos (8U)
+#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
+#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7_Pos (7U)
+#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
+#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6_Pos (6U)
+#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
+#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5_Pos (5U)
+#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
+#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4_Pos (4U)
+#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
+#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3_Pos (3U)
+#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
+#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2_Pos (2U)
+#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
+#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1_Pos (1U)
+#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
+#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0_Pos (0U)
+#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
+#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_CALFACT_Pos (0U)
+#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_LFMEN_Pos (25U)
+#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
+#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR (0xFFU) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos (3U)
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos (5U)
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos (7U)
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT_Pos (0U)
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL_Pos (0U)
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_Pos (0U)
+#define DBGMCU_CR_DBG_Msk (0x7UL << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
+#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+
+/******************* Bit definition for DMA_CSELR register *******************/
+#define DMA_CSELR_C1S_Pos (0U)
+#define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
+#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos (4U)
+#define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
+#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos (8U)
+#define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
+#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos (12U)
+#define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
+#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos (16U)
+#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
+#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S_Pos (20U)
+#define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
+#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S_Pos (24U)
+#define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
+#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_IM0_Pos (0U)
+#define EXTI_IMR_IM0_Msk (0x1UL << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_IM1_Pos (1U)
+#define EXTI_IMR_IM1_Msk (0x1UL << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_IM2_Pos (2U)
+#define EXTI_IMR_IM2_Msk (0x1UL << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_IM3_Pos (3U)
+#define EXTI_IMR_IM3_Msk (0x1UL << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_IM4_Pos (4U)
+#define EXTI_IMR_IM4_Msk (0x1UL << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_IM5_Pos (5U)
+#define EXTI_IMR_IM5_Msk (0x1UL << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_IM6_Pos (6U)
+#define EXTI_IMR_IM6_Msk (0x1UL << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_IM7_Pos (7U)
+#define EXTI_IMR_IM7_Msk (0x1UL << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_IM8_Pos (8U)
+#define EXTI_IMR_IM8_Msk (0x1UL << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_IM9_Pos (9U)
+#define EXTI_IMR_IM9_Msk (0x1UL << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_IM10_Pos (10U)
+#define EXTI_IMR_IM10_Msk (0x1UL << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_IM11_Pos (11U)
+#define EXTI_IMR_IM11_Msk (0x1UL << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_IM12_Pos (12U)
+#define EXTI_IMR_IM12_Msk (0x1UL << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_IM13_Pos (13U)
+#define EXTI_IMR_IM13_Msk (0x1UL << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_IM14_Pos (14U)
+#define EXTI_IMR_IM14_Msk (0x1UL << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_IM15_Pos (15U)
+#define EXTI_IMR_IM15_Msk (0x1UL << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_IM17_Pos (17U)
+#define EXTI_IMR_IM17_Msk (0x1UL << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_IM19_Pos (19U)
+#define EXTI_IMR_IM19_Msk (0x1UL << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_IM20_Pos (20U)
+#define EXTI_IMR_IM20_Msk (0x1UL << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_IM23_Pos (23U)
+#define EXTI_IMR_IM23_Msk (0x1UL << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
+#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_IM26_Pos (26U)
+#define EXTI_IMR_IM26_Msk (0x1UL << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
+#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_IM28_Pos (28U)
+#define EXTI_IMR_IM28_Msk (0x1UL << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
+#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_IM29_Pos (29U)
+#define EXTI_IMR_IM29_Msk (0x1UL << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
+#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
+
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x36FFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x36FFFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_EM0_Pos (0U)
+#define EXTI_EMR_EM0_Msk (0x1UL << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_EM1_Pos (1U)
+#define EXTI_EMR_EM1_Msk (0x1UL << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_EM2_Pos (2U)
+#define EXTI_EMR_EM2_Msk (0x1UL << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_EM3_Pos (3U)
+#define EXTI_EMR_EM3_Msk (0x1UL << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_EM4_Pos (4U)
+#define EXTI_EMR_EM4_Msk (0x1UL << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_EM5_Pos (5U)
+#define EXTI_EMR_EM5_Msk (0x1UL << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_EM6_Pos (6U)
+#define EXTI_EMR_EM6_Msk (0x1UL << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_EM7_Pos (7U)
+#define EXTI_EMR_EM7_Msk (0x1UL << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_EM8_Pos (8U)
+#define EXTI_EMR_EM8_Msk (0x1UL << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_EM9_Pos (9U)
+#define EXTI_EMR_EM9_Msk (0x1UL << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_EM10_Pos (10U)
+#define EXTI_EMR_EM10_Msk (0x1UL << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_EM11_Pos (11U)
+#define EXTI_EMR_EM11_Msk (0x1UL << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_EM12_Pos (12U)
+#define EXTI_EMR_EM12_Msk (0x1UL << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_EM13_Pos (13U)
+#define EXTI_EMR_EM13_Msk (0x1UL << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_EM14_Pos (14U)
+#define EXTI_EMR_EM14_Msk (0x1UL << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_EM15_Pos (15U)
+#define EXTI_EMR_EM15_Msk (0x1UL << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_EM17_Pos (17U)
+#define EXTI_EMR_EM17_Msk (0x1UL << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_EM19_Pos (19U)
+#define EXTI_EMR_EM19_Msk (0x1UL << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_EM20_Pos (20U)
+#define EXTI_EMR_EM20_Msk (0x1UL << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_EM23_Pos (23U)
+#define EXTI_EMR_EM23_Msk (0x1UL << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
+#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
+#define EXTI_EMR_EM26_Pos (26U)
+#define EXTI_EMR_EM26_Msk (0x1UL << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
+#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
+#define EXTI_EMR_EM28_Pos (28U)
+#define EXTI_EMR_EM28_Msk (0x1UL << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
+#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
+#define EXTI_EMR_EM29_Pos (29U)
+#define EXTI_EMR_EM29_Msk (0x1UL << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
+#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_RT0_Pos (0U)
+#define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_RT1_Pos (1U)
+#define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_RT2_Pos (2U)
+#define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_RT3_Pos (3U)
+#define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_RT4_Pos (4U)
+#define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_RT5_Pos (5U)
+#define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_RT6_Pos (6U)
+#define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_RT7_Pos (7U)
+#define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_RT8_Pos (8U)
+#define EXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_RT9_Pos (9U)
+#define EXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_RT10_Pos (10U)
+#define EXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_RT11_Pos (11U)
+#define EXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_RT12_Pos (12U)
+#define EXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_RT13_Pos (13U)
+#define EXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_RT14_Pos (14U)
+#define EXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_RT15_Pos (15U)
+#define EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_RT16_Pos (16U)
+#define EXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_RT17_Pos (17U)
+#define EXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_RT19_Pos (19U)
+#define EXTI_RTSR_RT19_Msk (0x1UL << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_RT20_Pos (20U)
+#define EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_RT21_Pos (21U)
+#define EXTI_RTSR_RT21_Msk (0x1UL << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_RT22_Pos (22U)
+#define EXTI_RTSR_RT22_Msk (0x1UL << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
+#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
+#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
+#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
+#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
+#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
+#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
+#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
+#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
+#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
+#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
+#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
+#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
+#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
+#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
+#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
+#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
+#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
+#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
+#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
+#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
+#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_FT0_Pos (0U)
+#define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_FT1_Pos (1U)
+#define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_FT2_Pos (2U)
+#define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_FT3_Pos (3U)
+#define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_FT4_Pos (4U)
+#define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_FT5_Pos (5U)
+#define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_FT6_Pos (6U)
+#define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_FT7_Pos (7U)
+#define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_FT8_Pos (8U)
+#define EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_FT9_Pos (9U)
+#define EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_FT10_Pos (10U)
+#define EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_FT11_Pos (11U)
+#define EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_FT12_Pos (12U)
+#define EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_FT13_Pos (13U)
+#define EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_FT14_Pos (14U)
+#define EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_FT15_Pos (15U)
+#define EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_FT16_Pos (16U)
+#define EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_FT17_Pos (17U)
+#define EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_FT19_Pos (19U)
+#define EXTI_FTSR_FT19_Msk (0x1UL << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_FT20_Pos (20U)
+#define EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_FT21_Pos (21U)
+#define EXTI_FTSR_FT21_Msk (0x1UL << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_FT22_Pos (22U)
+#define EXTI_FTSR_FT22_Msk (0x1UL << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
+#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
+#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
+#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
+#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
+#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
+#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
+#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
+#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
+#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
+#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
+#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
+#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
+#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
+#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
+#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
+#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
+#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
+#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
+#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
+#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
+#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWI0_Pos (0U)
+#define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWI1_Pos (1U)
+#define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWI2_Pos (2U)
+#define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWI3_Pos (3U)
+#define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWI4_Pos (4U)
+#define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWI5_Pos (5U)
+#define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWI6_Pos (6U)
+#define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWI7_Pos (7U)
+#define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWI8_Pos (8U)
+#define EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWI9_Pos (9U)
+#define EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWI10_Pos (10U)
+#define EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWI11_Pos (11U)
+#define EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWI12_Pos (12U)
+#define EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWI13_Pos (13U)
+#define EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWI14_Pos (14U)
+#define EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWI15_Pos (15U)
+#define EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWI16_Pos (16U)
+#define EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWI17_Pos (17U)
+#define EXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWI19_Pos (19U)
+#define EXTI_SWIER_SWI19_Msk (0x1UL << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWI20_Pos (20U)
+#define EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWI21_Pos (21U)
+#define EXTI_SWIER_SWI21_Msk (0x1UL << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWI22_Pos (22U)
+#define EXTI_SWIER_SWI22_Msk (0x1UL << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
+
+/* Legacy defines */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PIF0_Pos (0U)
+#define EXTI_PR_PIF0_Msk (0x1UL << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
+#define EXTI_PR_PIF1_Pos (1U)
+#define EXTI_PR_PIF1_Msk (0x1UL << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
+#define EXTI_PR_PIF2_Pos (2U)
+#define EXTI_PR_PIF2_Msk (0x1UL << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
+#define EXTI_PR_PIF3_Pos (3U)
+#define EXTI_PR_PIF3_Msk (0x1UL << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
+#define EXTI_PR_PIF4_Pos (4U)
+#define EXTI_PR_PIF4_Msk (0x1UL << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
+#define EXTI_PR_PIF5_Pos (5U)
+#define EXTI_PR_PIF5_Msk (0x1UL << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
+#define EXTI_PR_PIF6_Pos (6U)
+#define EXTI_PR_PIF6_Msk (0x1UL << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
+#define EXTI_PR_PIF7_Pos (7U)
+#define EXTI_PR_PIF7_Msk (0x1UL << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
+#define EXTI_PR_PIF8_Pos (8U)
+#define EXTI_PR_PIF8_Msk (0x1UL << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
+#define EXTI_PR_PIF9_Pos (9U)
+#define EXTI_PR_PIF9_Msk (0x1UL << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
+#define EXTI_PR_PIF10_Pos (10U)
+#define EXTI_PR_PIF10_Msk (0x1UL << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
+#define EXTI_PR_PIF11_Pos (11U)
+#define EXTI_PR_PIF11_Msk (0x1UL << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
+#define EXTI_PR_PIF12_Pos (12U)
+#define EXTI_PR_PIF12_Msk (0x1UL << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
+#define EXTI_PR_PIF13_Pos (13U)
+#define EXTI_PR_PIF13_Msk (0x1UL << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
+#define EXTI_PR_PIF14_Pos (14U)
+#define EXTI_PR_PIF14_Msk (0x1UL << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
+#define EXTI_PR_PIF15_Pos (15U)
+#define EXTI_PR_PIF15_Msk (0x1UL << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
+#define EXTI_PR_PIF16_Pos (16U)
+#define EXTI_PR_PIF16_Msk (0x1UL << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
+#define EXTI_PR_PIF17_Pos (17U)
+#define EXTI_PR_PIF17_Msk (0x1UL << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
+#define EXTI_PR_PIF19_Pos (19U)
+#define EXTI_PR_PIF19_Msk (0x1UL << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
+#define EXTI_PR_PIF20_Pos (20U)
+#define EXTI_PR_PIF20_Msk (0x1UL << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
+#define EXTI_PR_PIF21_Pos (21U)
+#define EXTI_PR_PIF21_Msk (0x1UL << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
+#define EXTI_PR_PIF22_Pos (22U)
+#define EXTI_PR_PIF22_Msk (0x1UL << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
+
+/* Legacy defines */
+#define EXTI_PR_PR0 EXTI_PR_PIF0
+#define EXTI_PR_PR1 EXTI_PR_PIF1
+#define EXTI_PR_PR2 EXTI_PR_PIF2
+#define EXTI_PR_PR3 EXTI_PR_PIF3
+#define EXTI_PR_PR4 EXTI_PR_PIF4
+#define EXTI_PR_PR5 EXTI_PR_PIF5
+#define EXTI_PR_PR6 EXTI_PR_PIF6
+#define EXTI_PR_PR7 EXTI_PR_PIF7
+#define EXTI_PR_PR8 EXTI_PR_PIF8
+#define EXTI_PR_PR9 EXTI_PR_PIF9
+#define EXTI_PR_PR10 EXTI_PR_PIF10
+#define EXTI_PR_PR11 EXTI_PR_PIF11
+#define EXTI_PR_PR12 EXTI_PR_PIF12
+#define EXTI_PR_PR13 EXTI_PR_PIF13
+#define EXTI_PR_PR14 EXTI_PR_PIF14
+#define EXTI_PR_PR15 EXTI_PR_PIF15
+#define EXTI_PR_PR16 EXTI_PR_PIF16
+#define EXTI_PR_PR17 EXTI_PR_PIF17
+#define EXTI_PR_PR19 EXTI_PR_PIF19
+#define EXTI_PR_PR20 EXTI_PR_PIF20
+#define EXTI_PR_PR21 EXTI_PR_PIF21
+#define EXTI_PR_PR22 EXTI_PR_PIF22
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
+#define FLASH_ACR_PRFTEN_Pos (1U)
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_SLEEP_PD_Pos (3U)
+#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD_Pos (4U)
+#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
+#define FLASH_ACR_DISAB_BUF_Pos (5U)
+#define FLASH_ACR_DISAB_BUF_Msk (0x1UL << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
+#define FLASH_ACR_PRE_READ_Pos (6U)
+#define FLASH_ACR_PRE_READ_Msk (0x1UL << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
+#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
+
+/******************* Bit definition for FLASH_PECR register ******************/
+#define FLASH_PECR_PELOCK_Pos (0U)
+#define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
+#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK_Pos (1U)
+#define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
+#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK_Pos (2U)
+#define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
+#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG_Pos (3U)
+#define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
+#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
+#define FLASH_PECR_DATA_Pos (4U)
+#define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
+#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
+#define FLASH_PECR_FIX_Pos (8U)
+#define FLASH_PECR_FIX_Msk (0x1UL << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
+#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE_Pos (9U)
+#define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
+#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
+#define FLASH_PECR_FPRG_Pos (10U)
+#define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
+#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_EOPIE_Pos (16U)
+#define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
+#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
+#define FLASH_PECR_ERRIE_Pos (17U)
+#define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
+#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
+#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
+#define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
+#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
+#define FLASH_PECR_HALF_ARRAY_Pos (19U)
+#define FLASH_PECR_HALF_ARRAY_Msk (0x1UL << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
+#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
+
+/****************** Bit definition for FLASH_PDKEYR register ******************/
+#define FLASH_PDKEYR_PDKEYR_Pos (0U)
+#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PEKEYR register ******************/
+#define FLASH_PEKEYR_PEKEYR_Pos (0U)
+#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PRGKEYR register ******************/
+#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
+#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
+
+/****************** Bit definition for FLASH_OPTKEYR register ******************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_EOP_Pos (1U)
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
+#define FLASH_SR_HVOFF_Pos (2U)
+#define FLASH_SR_HVOFF_Msk (0x1UL << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
+#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
+#define FLASH_SR_READY_Pos (3U)
+#define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */
+#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR_Pos (8U)
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
+#define FLASH_SR_PGAERR_Pos (9U)
+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR_Pos (10U)
+#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
+#define FLASH_SR_OPTVERR_Pos (11U)
+#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
+#define FLASH_SR_RDERR_Pos (13U)
+#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
+#define FLASH_SR_NOTZEROERR_Pos (16U)
+#define FLASH_SR_NOTZEROERR_Msk (0x1UL << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
+#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
+#define FLASH_SR_FWWERR_Pos (17U)
+#define FLASH_SR_FWWERR_Msk (0x1UL << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
+#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
+
+/* Legacy defines */
+#define FLASH_SR_FWWER FLASH_SR_FWWERR
+#define FLASH_SR_ENHV FLASH_SR_HVOFF
+#define FLASH_SR_ENDHV FLASH_SR_HVOFF
+
+/****************** Bit definition for FLASH_OPTR register *******************/
+#define FLASH_OPTR_RDPROT_Pos (0U)
+#define FLASH_OPTR_RDPROT_Msk (0xFFUL << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
+#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
+#define FLASH_OPTR_WPRMOD_Pos (8U)
+#define FLASH_OPTR_WPRMOD_Msk (0x1UL << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
+#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
+#define FLASH_OPTR_BOR_LEV_Pos (16U)
+#define FLASH_OPTR_BOR_LEV_Msk (0xFUL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
+#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OPTR_IWDG_SW_Pos (20U)
+#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
+#define FLASH_OPTR_nRST_STOP_Pos (21U)
+#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OPTR_nRST_STDBY_Pos (22U)
+#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OPTR_USER_Pos (20U)
+#define FLASH_OPTR_USER_Msk (0x7UL << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
+#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OPTR_BOOT1_Pos (31U)
+#define FLASH_OPTR_BOOT1_Msk (0x1UL << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
+#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 (0x00000001U)
+#define GPIO_OTYPER_OT_1 (0x00000002U)
+#define GPIO_OTYPER_OT_2 (0x00000004U)
+#define GPIO_OTYPER_OT_3 (0x00000008U)
+#define GPIO_OTYPER_OT_4 (0x00000010U)
+#define GPIO_OTYPER_OT_5 (0x00000020U)
+#define GPIO_OTYPER_OT_6 (0x00000040U)
+#define GPIO_OTYPER_OT_7 (0x00000080U)
+#define GPIO_OTYPER_OT_8 (0x00000100U)
+#define GPIO_OTYPER_OT_9 (0x00000200U)
+#define GPIO_OTYPER_OT_10 (0x00000400U)
+#define GPIO_OTYPER_OT_11 (0x00000800U)
+#define GPIO_OTYPER_OT_12 (0x00001000U)
+#define GPIO_OTYPER_OT_13 (0x00002000U)
+#define GPIO_OTYPER_OT_14 (0x00004000U)
+#define GPIO_OTYPER_OT_15 (0x00008000U)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDER_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
+#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDER_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
+#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDER_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
+#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDER_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
+#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDER_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
+#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDER_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
+#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDER_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
+#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDER_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
+#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDER_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
+#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDER_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
+#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDER_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
+#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDER_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
+#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDER_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
+#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDER_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
+#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDER_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
+#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDER_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
+#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 (0x00000001U)
+#define GPIO_BSRR_BS_1 (0x00000002U)
+#define GPIO_BSRR_BS_2 (0x00000004U)
+#define GPIO_BSRR_BS_3 (0x00000008U)
+#define GPIO_BSRR_BS_4 (0x00000010U)
+#define GPIO_BSRR_BS_5 (0x00000020U)
+#define GPIO_BSRR_BS_6 (0x00000040U)
+#define GPIO_BSRR_BS_7 (0x00000080U)
+#define GPIO_BSRR_BS_8 (0x00000100U)
+#define GPIO_BSRR_BS_9 (0x00000200U)
+#define GPIO_BSRR_BS_10 (0x00000400U)
+#define GPIO_BSRR_BS_11 (0x00000800U)
+#define GPIO_BSRR_BS_12 (0x00001000U)
+#define GPIO_BSRR_BS_13 (0x00002000U)
+#define GPIO_BSRR_BS_14 (0x00004000U)
+#define GPIO_BSRR_BS_15 (0x00008000U)
+#define GPIO_BSRR_BR_0 (0x00010000U)
+#define GPIO_BSRR_BR_1 (0x00020000U)
+#define GPIO_BSRR_BR_2 (0x00040000U)
+#define GPIO_BSRR_BR_3 (0x00080000U)
+#define GPIO_BSRR_BR_4 (0x00100000U)
+#define GPIO_BSRR_BR_5 (0x00200000U)
+#define GPIO_BSRR_BR_6 (0x00400000U)
+#define GPIO_BSRR_BR_7 (0x00800000U)
+#define GPIO_BSRR_BR_8 (0x01000000U)
+#define GPIO_BSRR_BR_9 (0x02000000U)
+#define GPIO_BSRR_BR_10 (0x04000000U)
+#define GPIO_BSRR_BR_11 (0x08000000U)
+#define GPIO_BSRR_BR_12 (0x10000000U)
+#define GPIO_BSRR_BR_13 (0x20000000U)
+#define GPIO_BSRR_BR_14 (0x40000000U)
+#define GPIO_BSRR_BR_15 (0x80000000U)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 (0x00000001U)
+#define GPIO_BRR_BR_1 (0x00000002U)
+#define GPIO_BRR_BR_2 (0x00000004U)
+#define GPIO_BRR_BR_3 (0x00000008U)
+#define GPIO_BRR_BR_4 (0x00000010U)
+#define GPIO_BRR_BR_5 (0x00000020U)
+#define GPIO_BRR_BR_6 (0x00000040U)
+#define GPIO_BRR_BR_7 (0x00000080U)
+#define GPIO_BRR_BR_8 (0x00000100U)
+#define GPIO_BRR_BR_9 (0x00000200U)
+#define GPIO_BRR_BR_10 (0x00000400U)
+#define GPIO_BRR_BR_11 (0x00000800U)
+#define GPIO_BRR_BR_12 (0x00001000U)
+#define GPIO_BRR_BR_13 (0x00002000U)
+#define GPIO_BRR_BR_14 (0x00004000U)
+#define GPIO_BRR_BR_15 (0x00008000U)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos (1U)
+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos (2U)
+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos (3U)
+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos (4U)
+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos (5U)
+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos (6U)
+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos (7U)
+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos (8U)
+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos (12U)
+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos (14U)
+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos (15U)
+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos (16U)
+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos (17U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos (18U)
+#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos (19U)
+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos (20U)
+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos (21U)
+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos (22U)
+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos (23U)
+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD_Pos (0U)
+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos (10U)
+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos (11U)
+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos (12U)
+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos (13U)
+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
+#define I2C_CR2_STOP_Pos (14U)
+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos (15U)
+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos (16U)
+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos (24U)
+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos (25U)
+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos (26U)
+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1_Pos (0U)
+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos (10U)
+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos (15U)
+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2_Pos (1U)
+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos (8U)
+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos (8U)
+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos (9U)
+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos (8U)
+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos (10U)
+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos (8U)
+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos (9U)
+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos (8U)
+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos (15U)
+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos (0U)
+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos (8U)
+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos (16U)
+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos (20U)
+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos (28U)
+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE_Pos (0U)
+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos (1U)
+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos (2U)
+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos (3U)
+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos (4U)
+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos (5U)
+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos (6U)
+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos (7U)
+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos (8U)
+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
+#define I2C_ISR_ARLO_Pos (9U)
+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos (10U)
+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos (11U)
+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos (12U)
+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos (13U)
+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos (15U)
+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
+#define I2C_ISR_DIR_Pos (16U)
+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos (17U)
+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF_Pos (3U)
+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos (4U)
+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos (5U)
+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos (8U)
+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos (9U)
+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos (10U)
+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos (11U)
+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos (12U)
+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos (13U)
+#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define I2C_PECR_PEC_Pos (0U)
+#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA_Pos (0U)
+#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA_Pos (0U)
+#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos (2U)
+#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN_Pos (0U)
+#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM_Pos (0U)
+#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos (1U)
+#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos (2U)
+#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos (3U)
+#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos (4U)
+#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos (5U)
+#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos (6U)
+#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF_Pos (0U)
+#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos (1U)
+#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos (3U)
+#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos (4U)
+#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos (5U)
+#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos (6U)
+#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos (0U)
+#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos (1U)
+#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos (3U)
+#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos (4U)
+#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos (5U)
+#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos (6U)
+#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos (0U)
+#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos (1U)
+#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos (3U)
+#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos (6U)
+#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos (9U)
+#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos (17U)
+#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos (19U)
+#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos (20U)
+#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos (21U)
+#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos (22U)
+#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos (24U)
+#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE_Pos (0U)
+#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos (1U)
+#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos (2U)
+#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP_Pos (0U)
+#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR_Pos (0U)
+#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT_Pos (0U)
+#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
+
+/******************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPSDSR_Pos (0U)
+#define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP_Pos (9U)
+#define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /*!< 0x00000200 */
+#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
+#define PWR_CR_FWU_Pos (10U)
+#define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /*!< 0x00000400 */
+#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
+
+#define PWR_CR_VOS_Pos (11U)
+#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x00001800 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /*!< 0x00000800 */
+#define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /*!< 0x00001000 */
+#define PWR_CR_DSEEKOFF_Pos (13U)
+#define PWR_CR_DSEEKOFF_Msk (0x1UL << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */
+#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */
+#define PWR_CR_LPRUN_Pos (14U)
+#define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
+#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_VREFINTRDYF_Pos (3U)
+#define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
+#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF_Pos (4U)
+#define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
+#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF_Pos (5U)
+#define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
+#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1_Pos (8U)
+#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP3_Pos (10U)
+#define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
+#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos (1U)
+#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos (2U)
+#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIVEN_Pos (3U)
+#define RCC_CR_HSIDIVEN_Msk (0x1UL << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */
+#define RCC_CR_HSIDIVF_Pos (4U)
+#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */
+#define RCC_CR_HSIOUTEN_Pos (5U)
+#define RCC_CR_HSIOUTEN_Msk (0x1UL << RCC_CR_HSIOUTEN_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_Msk /*!< Internal High Speed clock out enable */
+#define RCC_CR_MSION_Pos (8U)
+#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000100 */
+#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY_Pos (9U)
+#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
+#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_RTCPRE_Pos (20U)
+#define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
+#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */
+#define RCC_CR_RTCPRE_0 (0x1UL << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */
+#define RCC_CR_RTCPRE_1 (0x2UL << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+/* Reference defines */
+
+/******************** Bit definition for RCC_ICSCR register *****************/
+#define RCC_ICSCR_HSICAL_Pos (0U)
+#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
+#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM_Pos (8U)
+#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
+#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE_Pos (13U)
+#define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
+#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
+#define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
+#define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
+#define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
+#define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
+#define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
+#define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
+#define RCC_ICSCR_MSICAL_Pos (16U)
+#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
+#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM_Pos (24U)
+#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
+#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos (15U)
+#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */
+
+/*!< PLL entry clock source*/
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
+
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL_Pos (18U)
+#define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV_Pos (22U)
+#define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
+
+#define RCC_CFGR_PLLDIV2_Pos (22U)
+#define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3_Pos (23U)
+#define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4_Pos (22U)
+#define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCOSEL_Pos (24U)
+#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
+#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
+
+#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
+#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCOSEL_HSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_MSI_Pos (24U)
+#define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
+#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_HSE_Pos (26U)
+#define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCOSEL_PLL_Pos (24U)
+#define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
+#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
+#define RCC_CFGR_MCOSEL_LSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
+#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
+#define RCC_CFGR_MCOSEL_LSE_Pos (24U)
+#define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
+
+#define RCC_CFGR_MCOPRE_Pos (28U)
+#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
+
+#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
+
+/* Legacy defines */
+#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
+#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
+#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
+#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
+#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
+#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
+#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
+#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
+#ifdef RCC_CFGR_MCOSEL_HSI48
+#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48
+#endif
+
+#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
+#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
+
+/*!<****************** Bit definition for RCC_CIER register ********************/
+#define RCC_CIER_LSIRDYIE_Pos (0U)
+#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIER_LSERDYIE_Pos (1U)
+#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIER_HSIRDYIE_Pos (2U)
+#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIER_HSERDYIE_Pos (3U)
+#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIER_PLLRDYIE_Pos (4U)
+#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIER_MSIRDYIE_Pos (5U)
+#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
+#define RCC_CIER_CSSLSE_Pos (7U)
+#define RCC_CIER_CSSLSE_Msk (0x1UL << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */
+
+/* Reference defines */
+#define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
+
+/*!<****************** Bit definition for RCC_CIFR register ********************/
+#define RCC_CIFR_LSIRDYF_Pos (0U)
+#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIFR_LSERDYF_Pos (1U)
+#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIFR_HSIRDYF_Pos (2U)
+#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIFR_HSERDYF_Pos (3U)
+#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIFR_PLLRDYF_Pos (4U)
+#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIFR_MSIRDYF_Pos (5U)
+#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
+#define RCC_CIFR_CSSLSEF_Pos (7U)
+#define RCC_CIFR_CSSLSEF_Msk (0x1UL << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */
+
+/* Reference defines */
+#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
+
+/*!<****************** Bit definition for RCC_CICR register ********************/
+#define RCC_CICR_LSIRDYC_Pos (0U)
+#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CICR_LSERDYC_Pos (1U)
+#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CICR_HSIRDYC_Pos (2U)
+#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CICR_HSERDYC_Pos (3U)
+#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CICR_PLLRDYC_Pos (4U)
+#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CICR_MSIRDYC_Pos (5U)
+#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
+#define RCC_CICR_CSSLSEC_Pos (7U)
+#define RCC_CICR_CSSLSEC_Msk (0x1UL << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */
+
+/* Reference defines */
+#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
+/***************** Bit definition for RCC_IOPRSTR register ******************/
+#define RCC_IOPRSTR_IOPARST_Pos (0U)
+#define RCC_IOPRSTR_IOPARST_Msk (0x1UL << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */
+#define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */
+#define RCC_IOPRSTR_IOPBRST_Pos (1U)
+#define RCC_IOPRSTR_IOPBRST_Msk (0x1UL << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */
+#define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */
+#define RCC_IOPRSTR_IOPCRST_Pos (2U)
+#define RCC_IOPRSTR_IOPCRST_Msk (0x1UL << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */
+#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */
+
+/* Reference defines */
+#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
+#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
+#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
+
+
+/****************** Bit definition for RCC_AHBRST register ******************/
+#define RCC_AHBRSTR_DMARST_Pos (0U)
+#define RCC_AHBRSTR_DMARST_Msk (0x1UL << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */
+#define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */
+#define RCC_AHBRSTR_MIFRST_Pos (8U)
+#define RCC_AHBRSTR_MIFRST_Msk (0x1UL << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */
+#define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset */
+#define RCC_AHBRSTR_CRCRST_Pos (12U)
+#define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */
+
+/* Reference defines */
+#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
+#define RCC_APB2RSTR_TIM21RST_Pos (2U)
+#define RCC_APB2RSTR_TIM21RST_Msk (0x1UL << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 reset */
+#define RCC_APB2RSTR_ADCRST_Pos (9U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
+#define RCC_APB2RSTR_DBGRST_Pos (22U)
+#define RCC_APB2RSTR_DBGRST_Msk (0x1UL << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU reset */
+
+/* Reference defines */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 reset */
+#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU reset */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_LPUART1RST_Pos (18U)
+#define RCC_APB1RSTR_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
+#define RCC_APB1RSTR_LPTIM1RST_Pos (31U)
+#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 reset */
+
+/***************** Bit definition for RCC_IOPENR register ******************/
+#define RCC_IOPENR_IOPAEN_Pos (0U)
+#define RCC_IOPENR_IOPAEN_Msk (0x1UL << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */
+#define RCC_IOPENR_IOPBEN_Pos (1U)
+#define RCC_IOPENR_IOPBEN_Msk (0x1UL << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */
+#define RCC_IOPENR_IOPCEN_Pos (2U)
+#define RCC_IOPENR_IOPCEN_Msk (0x1UL << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */
+
+/* Reference defines */
+#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
+#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
+#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
+
+/***************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMAEN_Pos (0U)
+#define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_MIFEN_Pos (8U)
+#define RCC_AHBENR_MIFEN_Msk (0x1UL << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */
+#define RCC_AHBENR_CRCEN_Pos (12U)
+#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+
+/* Reference defines */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register ******************/
+#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM21EN_Pos (2U)
+#define RCC_APB2ENR_TIM21EN_Msk (0x1UL << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */
+#define RCC_APB2ENR_FWEN_Pos (7U)
+#define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADCEN_Pos (9U)
+#define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
+#define RCC_APB2ENR_DBGEN_Pos (22U)
+#define RCC_APB2ENR_DBGEN_Msk (0x1UL << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */
+
+/* Reference defines */
+
+#define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
+#define RCC_APB1ENR_LPUART1EN_Pos (18U)
+#define RCC_APB1ENR_LPUART1EN_Msk (0x1UL << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
+#define RCC_APB1ENR_LPTIM1EN_Pos (31U)
+#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */
+
+/****************** Bit definition for RCC_IOPSMENR register ****************/
+#define RCC_IOPSMENR_IOPASMEN_Pos (0U)
+#define RCC_IOPSMENR_IOPASMEN_Msk (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPBSMEN_Pos (1U)
+#define RCC_IOPSMENR_IOPBSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPCSMEN_Pos (2U)
+#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_AHBSMENR register ******************/
+#define RCC_AHBSMENR_DMASMEN_Pos (0U)
+#define RCC_AHBSMENR_DMASMEN_Msk (0x1UL << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */
+#define RCC_AHBSMENR_MIFSMEN_Pos (8U)
+#define RCC_AHBSMENR_MIFSMEN_Msk (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */
+#define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
+#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRCSMEN_Pos (12U)
+#define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB2SMENR register ******************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM21SMEN_Pos (2U)
+#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */
+#define RCC_APB2SMENR_ADCSMEN_Pos (9U)
+#define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
+#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGSMEN_Pos (22U)
+#define RCC_APB2SMENR_DBGSMEN_Msk (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB1SMENR register ******************/
+#define RCC_APB1SMENR_TIM2SMEN_Pos (0U)
+#define RCC_APB1SMENR_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_WWDGSMEN_Pos (11U)
+#define RCC_APB1SMENR_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART2SMEN_Pos (17U)
+#define RCC_APB1SMENR_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPUART1SMEN_Pos (18U)
+#define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C1SMEN_Pos (21U)
+#define RCC_APB1SMENR_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_PWRSMEN_Pos (28U)
+#define RCC_APB1SMENR_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U)
+#define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */
+
+/*!< USART2 Clock source selection */
+#define RCC_CCIPR_USART2SEL_Pos (2U)
+#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */
+#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+/*!< LPUART1 Clock source selection */
+#define RCC_CCIPR_LPUART1SEL_Pos (10U)
+#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */
+#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */
+#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CCIPR_I2C1SEL_Pos (12U)
+#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */
+#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
+
+
+/*!< LPTIM1 Clock source selection */
+#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
+#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */
+#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+/******************* Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSEON_Pos (8U)
+#define RCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */
+#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_CSR_LSERDY_Pos (9U)
+#define RCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */
+#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP_Pos (10U)
+#define RCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */
+#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_CSR_LSEDRV_Pos (11U)
+#define RCC_CSR_LSEDRV_Msk (0x3UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */
+#define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_CSR_LSEDRV_0 (0x1UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */
+#define RCC_CSR_LSEDRV_1 (0x2UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */
+
+#define RCC_CSR_LSECSSON_Pos (13U)
+#define RCC_CSR_LSECSSON_Msk (0x1UL << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */
+#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */
+#define RCC_CSR_LSECSSD_Pos (14U)
+#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
+#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
+
+/*!< RTC congiguration */
+#define RCC_CSR_RTCSEL_Pos (16U)
+#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
+
+#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CSR_RTCSEL_LSE_Pos (16U)
+#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_LSI_Pos (17U)
+#define RCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */
+#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_HSE_Pos (16U)
+#define RCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */
+
+#define RCC_CSR_RTCEN_Pos (18U)
+#define RCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */
+#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_CSR_RTCRST_Pos (19U)
+#define RCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */
+#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */
+
+#define RCC_CSR_RMVF_Pos (23U)
+#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_OBLRSTF_Pos (25U)
+#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+/* Reference defines */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER2_SUPPORT
+#define RTC_TAMPER3_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk /*!< */
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk /*!< */
+#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk /*!< */
+#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */
+#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */
+#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk /*!< */
+#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk /*!< */
+#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk /*!< */
+#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk /*!< */
+#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */
+#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk /*!< */
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk /*!< */
+#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk /*!< */
+#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk /*!< */
+#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk /*!< */
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */
+#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk /*!< */
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< */
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */
+#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */
+#define RTC_ISR_TAMP3F_Pos (15U)
+#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk /*!< */
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */
+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */
+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */
+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */
+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */
+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */
+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */
+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */
+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */
+#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */
+#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */
+#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */
+#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */
+#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */
+#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */
+#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */
+#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */
+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */
+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */
+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */
+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */
+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */
+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */
+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */
+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */
+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */
+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CALR register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */
+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define RTC_CAL_CALP RTC_CALR_CALP
+#define RTC_CAL_CALW8 RTC_CALR_CALW8
+#define RTC_CAL_CALW16 RTC_CALR_CALW16
+#define RTC_CAL_CALM RTC_CALR_CALM
+#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
+
+/******************** Bits definition for RTC_TAMPCR register ****************/
+#define RTC_TAMPCR_TAMP3MF_Pos (24U)
+#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
+#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
+#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
+#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP3IE_Pos (22U)
+#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
+#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2MF_Pos (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2IE_Pos (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */
+#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */
+#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */
+#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos (7U)
+#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */
+#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
+#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
+#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP3E_Pos (5U)
+#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
+#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk /*!< */
+#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP2E_Pos (3U)
+#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */
+#define RTC_TAMPCR_TAMPIE_Pos (2U)
+#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_OR register ****************/
+#define RTC_OR_OUT_RMP_Pos (1U)
+#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */
+#define RTC_OR_ALARMOUTTYPE_Pos (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */
+
+/* Legacy defines */
+#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk /*!< */
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER (0x00000005U) /*!< */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/******************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
+#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR1_BOOT_MODE_Pos (8U)
+#define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
+#define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */
+#define SYSCFG_CFGR1_BOOT_MODE_0 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOT_MODE_1 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_FWDISEN_Pos (0U)
+#define SYSCFG_CFGR2_FWDISEN_Msk (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
+
+
+/***************** Bit definition for SYSCFG_CFGR3 register ****************/
+#define SYSCFG_CFGR3_EN_VREFINT_Pos (0U)
+#define SYSCFG_CFGR3_EN_VREFINT_Msk (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_EN_VREFINT SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
+#define SYSCFG_CFGR3_VREF_OUT_Pos (4U)
+#define SYSCFG_CFGR3_VREF_OUT_Msk (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
+#define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */
+#define SYSCFG_CFGR3_VREF_OUT_0 (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
+#define SYSCFG_CFGR3_VREF_OUT_1 (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U)
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U)
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U)
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
+#define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U)
+#define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
+#define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
+#define SYSCFG_CFGR3_REF_LOCK_Pos (31U)
+#define SYSCFG_CFGR3_REF_LOCK_Msk (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
+#define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */
+
+/* Legacy defines */
+
+#define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
+#define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
+#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
+#define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+
+/******************************************************************************/
+/* */
+/* Timers (TIM)*/
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
+#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
+ || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#else
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#endif
+
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFUL << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFUL << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM2_OR_ETR_RMP_Pos (0U)
+#define TIM2_OR_ETR_RMP_Msk (0x7UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000007 */
+#define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
+#define TIM2_OR_ETR_RMP_0 (0x1UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM2_OR_ETR_RMP_1 (0x2UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM2_OR_ETR_RMP_2 (0x4UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000004 */
+#define TIM2_OR_TI4_RMP_Pos (3U)
+#define TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000018 */
+#define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
+#define TIM2_OR_TI4_RMP_0 (0x1UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */
+#define TIM2_OR_TI4_RMP_1 (0x2UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000010 */
+
+#define TIM21_OR_ETR_RMP_Pos (0U)
+#define TIM21_OR_ETR_RMP_Msk (0x3UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
+#define TIM21_OR_ETR_RMP_0 (0x1UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM21_OR_ETR_RMP_1 (0x2UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM21_OR_TI1_RMP_Pos (2U)
+#define TIM21_OR_TI1_RMP_Msk (0x7UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x0000001C */
+#define TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
+#define TIM21_OR_TI1_RMP_0 (0x1UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM21_OR_TI1_RMP_1 (0x2UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+#define TIM21_OR_TI1_RMP_2 (0x4UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000010 */
+#define TIM21_OR_TI2_RMP_Pos (5U)
+#define TIM21_OR_TI2_RMP_Msk (0x1UL << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */
+#define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE_Pos (0U)
+#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+#define USART_CR1_UESM_Pos (1U)
+#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
+#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_M0_Pos (12U)
+#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
+#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos (13U)
+#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos (14U)
+#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos (16U)
+#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
+#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
+#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
+#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
+#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos (21U)
+#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
+#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
+#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
+#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
+#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos (26U)
+#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos (27U)
+#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos (28U)
+#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
+#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7_Pos (4U)
+#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos (15U)
+#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos (16U)
+#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos (17U)
+#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos (18U)
+#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos (19U)
+#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos (20U)
+#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos (21U)
+#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos (23U)
+#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos (24U)
+#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos (12U)
+#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos (13U)
+#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos (14U)
+#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos (15U)
+#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos (17U)
+#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos (20U)
+#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
+#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
+#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos (22U)
+#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
+#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
+#define USART_CR3_UCESM_Pos (23U)
+#define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
+#define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION_Pos (0U)
+#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos (4U)
+#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO_Pos (0U)
+#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos (24U)
+#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ_Pos (0U)
+#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
+#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos (1U)
+#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
+#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos (2U)
+#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
+#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos (3U)
+#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
+#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos (4U)
+#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
+#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE_Pos (0U)
+#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
+#define USART_ISR_FE_Pos (1U)
+#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
+#define USART_ISR_NE_Pos (2U)
+#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos (3U)
+#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos (4U)
+#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos (5U)
+#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos (6U)
+#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos (7U)
+#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
+#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos (8U)
+#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos (9U)
+#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos (10U)
+#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
+#define USART_ISR_RTOF_Pos (11U)
+#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos (12U)
+#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos (14U)
+#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos (15U)
+#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos (16U)
+#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
+#define USART_ISR_CMF_Pos (17U)
+#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos (18U)
+#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos (19U)
+#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos (20U)
+#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
+#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos (21U)
+#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos (22U)
+#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
+#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF_Pos (0U)
+#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos (1U)
+#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos (2U)
+#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */
+#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos (3U)
+#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos (4U)
+#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos (6U)
+#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF_Pos (8U)
+#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos (9U)
+#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos (11U)
+#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos (12U)
+#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos (17U)
+#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos (20U)
+#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
+#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
+
+/* Compatibility defines with other series */
+#define USART_ICR_NECF USART_ICR_NCF
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR_Pos (0U)
+#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR_Pos (0U)
+#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
+
+
+
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SMBUS Instances *****************************/
+#define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/************* LPTIM instances supporting the encoder mode feature ************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM21) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/******************* TIM Instances : output(s) OCXEC register *****************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (1 == 0)
+
+/****************** USART Instances : Auto Baud Rate detection ****************/
+
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (1 == 0)
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (1==0)
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (1==0)
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (1==0)
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32L0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32L0 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+
+#define RNG_LPUART1_IRQn LPUART1_IRQn
+#define AES_LPUART1_IRQn LPUART1_IRQn
+#define AES_RNG_LPUART1_IRQn LPUART1_IRQn
+#define RCC_CRS_IRQn RCC_IRQn
+#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
+#define ADC1_COMP_IRQn ADC1_IRQn
+
+/* Aliases for __IRQHandler */
+#define RNG_LPUART1_IRQHandler LPUART1_IRQHandler
+#define AES_LPUART1_IRQHandler LPUART1_IRQHandler
+#define AES_RNG_LPUART1_IRQHandler LPUART1_IRQHandler
+#define RCC_CRS_IRQHandler RCC_IRQHandler
+#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
+#define ADC1_COMP_IRQHandler ADC1_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L010x4_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/CMSIS/device/stm32l010x6.h b/CMSIS/device/stm32l010x6.h
new file mode 100644
index 0000000..013a745
--- /dev/null
+++ b/CMSIS/device/stm32l010x6.h
@@ -0,0 +1,5860 @@
+/**
+ ******************************************************************************
+ * @file stm32l010x6.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for stm32l010x6 devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright(c) 2018 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l010x6
+ * @{
+ */
+
+#ifndef __STM32L010x6_H
+#define __STM32L010x6_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 0U /*!< STM32L0xx provides no MPU */
+#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
+#define __NVIC_PRIO_BITS 2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief stm32l010x6 Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+/*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
+
+/****** STM32L-0 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */
+ RCC_IRQn = 4, /*!< RCC Interrupt */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
+ ADC1_IRQn = 12, /*!< ADC1 Interrupt */
+ LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 Interrupt */
+ TIM21_IRQn = 20, /*!< TIM21 Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ USART2_IRQn = 28, /*!< USART2 Interrupt */
+ LPUART1_IRQn = 29, /*!< LPUART1 Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0plus.h"
+#include "system_stm32l0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+ uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+} ADC_Common_TypeDef;
+
+
+
+/**
+* @brief CRC calculation unit
+*/
+
+typedef struct
+{
+__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+uint8_t RESERVED0; /*!< Reserved, 0x05 */
+uint16_t RESERVED1; /*!< Reserved, 0x06 */
+__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+uint32_t RESERVED2; /*!< Reserved, 0x0C */
+__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
+} DMA_Request_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
+ __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
+ __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
+ __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
+ __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
+ __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
+ __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
+ __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
+ __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
+ __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
+} OB_TypeDef;
+
+
+/**
+ * @brief General Purpose IO
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief LPTIMIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+} LPTIM_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+ * @brief Independent WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
+ __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
+ __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
+ __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
+ __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
+ __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
+ __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
+ __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
+ __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
+ __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
+ __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */
+
+#define DATA_EEPROM_BASE (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
+#define DATA_EEPROM_END (0x080800FFUL) /*!< DATA EEPROM end address in the alias region */
+#define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */
+#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8KBytes) */
+
+#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000UL)
+
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
+#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800UL)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
+#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL)
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL)
+#define TIM21_BASE (APBPERIPH_BASE + 0x00010800UL)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708UL)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
+#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL)
+
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
+#define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */
+#define FLASHSIZE_BASE (0x1FF8007CUL) /*!< FLASH Size register base address */
+#define UID_BASE (0x1FF80050UL) /*!< Unique device ID register base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
+
+#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL)
+#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL)
+#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL)
+#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00UL)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
+/* Legacy defines */
+#define ADC ADC1_COMMON
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_EOCAL_Pos (11U)
+#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
+#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
+#define ADC_ISR_AWD_Pos (7U)
+#define ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
+#define ADC_ISR_EOSEQ_Pos (3U)
+#define ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_EOCALIE_Pos (11U)
+#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
+#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
+#define ADC_IER_AWDIE_Pos (7U)
+#define ADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE_Pos (3U)
+#define ADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH_Pos (26U)
+#define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
+#define ADC_CFGR1_AWDEN_Pos (23U)
+#define ADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL_Pos (22U)
+#define ADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN_Pos (16U)
+#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF_Pos (15U)
+#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
+#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT_Pos (14U)
+#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
+#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT_Pos (13U)
+#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD_Pos (12U)
+#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN_Pos (10U)
+#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
+#define ADC_CFGR1_EXTSEL_Pos (6U)
+#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
+#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
+#define ADC_CFGR1_ALIGN_Pos (5U)
+#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
+#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
+#define ADC_CFGR1_RES_Pos (3U)
+#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
+#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
+#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
+#define ADC_CFGR1_SCANDIR_Pos (2U)
+#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG_Pos (1U)
+#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
+#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN_Pos (0U)
+#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
+#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_TOVS_Pos (9U)
+#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
+#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+#define ADC_CFGR2_OVSR_Pos (2U)
+#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
+#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+#define ADC_CFGR2_OVSE_Pos (0U)
+#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
+#define ADC_CFGR2_CKMODE_Pos (30U)
+#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
+#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
+#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
+#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
+
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP_Pos (0U)
+#define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
+#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
+#define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
+#define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define ADC_SMPR_SMPR ADC_SMPR_SMP
+#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
+#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
+#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT_Pos (16U)
+#define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
+#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
+#define ADC_TR_LT_Pos (0U)
+#define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL_Pos (0U)
+#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
+#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
+#define ADC_CHSELR_CHSEL18_Pos (18U)
+#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17_Pos (17U)
+#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
+#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL15_Pos (15U)
+#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
+#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14_Pos (14U)
+#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
+#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13_Pos (13U)
+#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
+#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12_Pos (12U)
+#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
+#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11_Pos (11U)
+#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
+#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10_Pos (10U)
+#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
+#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9_Pos (9U)
+#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
+#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8_Pos (8U)
+#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
+#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7_Pos (7U)
+#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
+#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6_Pos (6U)
+#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
+#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5_Pos (5U)
+#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
+#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4_Pos (4U)
+#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
+#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3_Pos (3U)
+#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
+#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2_Pos (2U)
+#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
+#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1_Pos (1U)
+#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
+#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0_Pos (0U)
+#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
+#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_CALFACT_Pos (0U)
+#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_LFMEN_Pos (25U)
+#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
+#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR (0xFFU) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos (3U)
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos (5U)
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos (7U)
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT_Pos (0U)
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL_Pos (0U)
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_Pos (0U)
+#define DBGMCU_CR_DBG_Msk (0x7UL << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
+#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+
+/******************* Bit definition for DMA_CSELR register *******************/
+#define DMA_CSELR_C1S_Pos (0U)
+#define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
+#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos (4U)
+#define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
+#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos (8U)
+#define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
+#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos (12U)
+#define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
+#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos (16U)
+#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
+#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S_Pos (20U)
+#define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
+#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S_Pos (24U)
+#define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
+#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_IM0_Pos (0U)
+#define EXTI_IMR_IM0_Msk (0x1UL << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_IM1_Pos (1U)
+#define EXTI_IMR_IM1_Msk (0x1UL << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_IM2_Pos (2U)
+#define EXTI_IMR_IM2_Msk (0x1UL << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_IM3_Pos (3U)
+#define EXTI_IMR_IM3_Msk (0x1UL << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_IM4_Pos (4U)
+#define EXTI_IMR_IM4_Msk (0x1UL << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_IM5_Pos (5U)
+#define EXTI_IMR_IM5_Msk (0x1UL << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_IM6_Pos (6U)
+#define EXTI_IMR_IM6_Msk (0x1UL << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_IM7_Pos (7U)
+#define EXTI_IMR_IM7_Msk (0x1UL << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_IM8_Pos (8U)
+#define EXTI_IMR_IM8_Msk (0x1UL << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_IM9_Pos (9U)
+#define EXTI_IMR_IM9_Msk (0x1UL << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_IM10_Pos (10U)
+#define EXTI_IMR_IM10_Msk (0x1UL << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_IM11_Pos (11U)
+#define EXTI_IMR_IM11_Msk (0x1UL << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_IM12_Pos (12U)
+#define EXTI_IMR_IM12_Msk (0x1UL << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_IM13_Pos (13U)
+#define EXTI_IMR_IM13_Msk (0x1UL << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_IM14_Pos (14U)
+#define EXTI_IMR_IM14_Msk (0x1UL << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_IM15_Pos (15U)
+#define EXTI_IMR_IM15_Msk (0x1UL << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_IM17_Pos (17U)
+#define EXTI_IMR_IM17_Msk (0x1UL << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_IM19_Pos (19U)
+#define EXTI_IMR_IM19_Msk (0x1UL << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_IM20_Pos (20U)
+#define EXTI_IMR_IM20_Msk (0x1UL << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_IM23_Pos (23U)
+#define EXTI_IMR_IM23_Msk (0x1UL << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
+#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_IM26_Pos (26U)
+#define EXTI_IMR_IM26_Msk (0x1UL << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
+#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_IM28_Pos (28U)
+#define EXTI_IMR_IM28_Msk (0x1UL << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
+#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_IM29_Pos (29U)
+#define EXTI_IMR_IM29_Msk (0x1UL << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
+#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
+
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x36FFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x36FFFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_EM0_Pos (0U)
+#define EXTI_EMR_EM0_Msk (0x1UL << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_EM1_Pos (1U)
+#define EXTI_EMR_EM1_Msk (0x1UL << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_EM2_Pos (2U)
+#define EXTI_EMR_EM2_Msk (0x1UL << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_EM3_Pos (3U)
+#define EXTI_EMR_EM3_Msk (0x1UL << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_EM4_Pos (4U)
+#define EXTI_EMR_EM4_Msk (0x1UL << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_EM5_Pos (5U)
+#define EXTI_EMR_EM5_Msk (0x1UL << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_EM6_Pos (6U)
+#define EXTI_EMR_EM6_Msk (0x1UL << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_EM7_Pos (7U)
+#define EXTI_EMR_EM7_Msk (0x1UL << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_EM8_Pos (8U)
+#define EXTI_EMR_EM8_Msk (0x1UL << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_EM9_Pos (9U)
+#define EXTI_EMR_EM9_Msk (0x1UL << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_EM10_Pos (10U)
+#define EXTI_EMR_EM10_Msk (0x1UL << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_EM11_Pos (11U)
+#define EXTI_EMR_EM11_Msk (0x1UL << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_EM12_Pos (12U)
+#define EXTI_EMR_EM12_Msk (0x1UL << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_EM13_Pos (13U)
+#define EXTI_EMR_EM13_Msk (0x1UL << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_EM14_Pos (14U)
+#define EXTI_EMR_EM14_Msk (0x1UL << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_EM15_Pos (15U)
+#define EXTI_EMR_EM15_Msk (0x1UL << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_EM17_Pos (17U)
+#define EXTI_EMR_EM17_Msk (0x1UL << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_EM19_Pos (19U)
+#define EXTI_EMR_EM19_Msk (0x1UL << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_EM20_Pos (20U)
+#define EXTI_EMR_EM20_Msk (0x1UL << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_EM23_Pos (23U)
+#define EXTI_EMR_EM23_Msk (0x1UL << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
+#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
+#define EXTI_EMR_EM26_Pos (26U)
+#define EXTI_EMR_EM26_Msk (0x1UL << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
+#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
+#define EXTI_EMR_EM28_Pos (28U)
+#define EXTI_EMR_EM28_Msk (0x1UL << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
+#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
+#define EXTI_EMR_EM29_Pos (29U)
+#define EXTI_EMR_EM29_Msk (0x1UL << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
+#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_RT0_Pos (0U)
+#define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_RT1_Pos (1U)
+#define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_RT2_Pos (2U)
+#define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_RT3_Pos (3U)
+#define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_RT4_Pos (4U)
+#define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_RT5_Pos (5U)
+#define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_RT6_Pos (6U)
+#define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_RT7_Pos (7U)
+#define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_RT8_Pos (8U)
+#define EXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_RT9_Pos (9U)
+#define EXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_RT10_Pos (10U)
+#define EXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_RT11_Pos (11U)
+#define EXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_RT12_Pos (12U)
+#define EXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_RT13_Pos (13U)
+#define EXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_RT14_Pos (14U)
+#define EXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_RT15_Pos (15U)
+#define EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_RT16_Pos (16U)
+#define EXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_RT17_Pos (17U)
+#define EXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_RT19_Pos (19U)
+#define EXTI_RTSR_RT19_Msk (0x1UL << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_RT20_Pos (20U)
+#define EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_RT21_Pos (21U)
+#define EXTI_RTSR_RT21_Msk (0x1UL << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_RT22_Pos (22U)
+#define EXTI_RTSR_RT22_Msk (0x1UL << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
+#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
+#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
+#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
+#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
+#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
+#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
+#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
+#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
+#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
+#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
+#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
+#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
+#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
+#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
+#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
+#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
+#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
+#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
+#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
+#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
+#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_FT0_Pos (0U)
+#define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_FT1_Pos (1U)
+#define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_FT2_Pos (2U)
+#define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_FT3_Pos (3U)
+#define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_FT4_Pos (4U)
+#define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_FT5_Pos (5U)
+#define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_FT6_Pos (6U)
+#define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_FT7_Pos (7U)
+#define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_FT8_Pos (8U)
+#define EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_FT9_Pos (9U)
+#define EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_FT10_Pos (10U)
+#define EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_FT11_Pos (11U)
+#define EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_FT12_Pos (12U)
+#define EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_FT13_Pos (13U)
+#define EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_FT14_Pos (14U)
+#define EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_FT15_Pos (15U)
+#define EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_FT16_Pos (16U)
+#define EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_FT17_Pos (17U)
+#define EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_FT19_Pos (19U)
+#define EXTI_FTSR_FT19_Msk (0x1UL << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_FT20_Pos (20U)
+#define EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_FT21_Pos (21U)
+#define EXTI_FTSR_FT21_Msk (0x1UL << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_FT22_Pos (22U)
+#define EXTI_FTSR_FT22_Msk (0x1UL << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
+#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
+#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
+#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
+#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
+#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
+#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
+#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
+#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
+#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
+#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
+#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
+#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
+#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
+#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
+#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
+#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
+#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
+#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
+#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
+#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
+#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWI0_Pos (0U)
+#define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWI1_Pos (1U)
+#define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWI2_Pos (2U)
+#define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWI3_Pos (3U)
+#define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWI4_Pos (4U)
+#define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWI5_Pos (5U)
+#define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWI6_Pos (6U)
+#define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWI7_Pos (7U)
+#define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWI8_Pos (8U)
+#define EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWI9_Pos (9U)
+#define EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWI10_Pos (10U)
+#define EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWI11_Pos (11U)
+#define EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWI12_Pos (12U)
+#define EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWI13_Pos (13U)
+#define EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWI14_Pos (14U)
+#define EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWI15_Pos (15U)
+#define EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWI16_Pos (16U)
+#define EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWI17_Pos (17U)
+#define EXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWI19_Pos (19U)
+#define EXTI_SWIER_SWI19_Msk (0x1UL << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWI20_Pos (20U)
+#define EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWI21_Pos (21U)
+#define EXTI_SWIER_SWI21_Msk (0x1UL << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWI22_Pos (22U)
+#define EXTI_SWIER_SWI22_Msk (0x1UL << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
+
+/* Legacy defines */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PIF0_Pos (0U)
+#define EXTI_PR_PIF0_Msk (0x1UL << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
+#define EXTI_PR_PIF1_Pos (1U)
+#define EXTI_PR_PIF1_Msk (0x1UL << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
+#define EXTI_PR_PIF2_Pos (2U)
+#define EXTI_PR_PIF2_Msk (0x1UL << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
+#define EXTI_PR_PIF3_Pos (3U)
+#define EXTI_PR_PIF3_Msk (0x1UL << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
+#define EXTI_PR_PIF4_Pos (4U)
+#define EXTI_PR_PIF4_Msk (0x1UL << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
+#define EXTI_PR_PIF5_Pos (5U)
+#define EXTI_PR_PIF5_Msk (0x1UL << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
+#define EXTI_PR_PIF6_Pos (6U)
+#define EXTI_PR_PIF6_Msk (0x1UL << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
+#define EXTI_PR_PIF7_Pos (7U)
+#define EXTI_PR_PIF7_Msk (0x1UL << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
+#define EXTI_PR_PIF8_Pos (8U)
+#define EXTI_PR_PIF8_Msk (0x1UL << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
+#define EXTI_PR_PIF9_Pos (9U)
+#define EXTI_PR_PIF9_Msk (0x1UL << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
+#define EXTI_PR_PIF10_Pos (10U)
+#define EXTI_PR_PIF10_Msk (0x1UL << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
+#define EXTI_PR_PIF11_Pos (11U)
+#define EXTI_PR_PIF11_Msk (0x1UL << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
+#define EXTI_PR_PIF12_Pos (12U)
+#define EXTI_PR_PIF12_Msk (0x1UL << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
+#define EXTI_PR_PIF13_Pos (13U)
+#define EXTI_PR_PIF13_Msk (0x1UL << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
+#define EXTI_PR_PIF14_Pos (14U)
+#define EXTI_PR_PIF14_Msk (0x1UL << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
+#define EXTI_PR_PIF15_Pos (15U)
+#define EXTI_PR_PIF15_Msk (0x1UL << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
+#define EXTI_PR_PIF16_Pos (16U)
+#define EXTI_PR_PIF16_Msk (0x1UL << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
+#define EXTI_PR_PIF17_Pos (17U)
+#define EXTI_PR_PIF17_Msk (0x1UL << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
+#define EXTI_PR_PIF19_Pos (19U)
+#define EXTI_PR_PIF19_Msk (0x1UL << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
+#define EXTI_PR_PIF20_Pos (20U)
+#define EXTI_PR_PIF20_Msk (0x1UL << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
+#define EXTI_PR_PIF21_Pos (21U)
+#define EXTI_PR_PIF21_Msk (0x1UL << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
+#define EXTI_PR_PIF22_Pos (22U)
+#define EXTI_PR_PIF22_Msk (0x1UL << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
+
+/* Legacy defines */
+#define EXTI_PR_PR0 EXTI_PR_PIF0
+#define EXTI_PR_PR1 EXTI_PR_PIF1
+#define EXTI_PR_PR2 EXTI_PR_PIF2
+#define EXTI_PR_PR3 EXTI_PR_PIF3
+#define EXTI_PR_PR4 EXTI_PR_PIF4
+#define EXTI_PR_PR5 EXTI_PR_PIF5
+#define EXTI_PR_PR6 EXTI_PR_PIF6
+#define EXTI_PR_PR7 EXTI_PR_PIF7
+#define EXTI_PR_PR8 EXTI_PR_PIF8
+#define EXTI_PR_PR9 EXTI_PR_PIF9
+#define EXTI_PR_PR10 EXTI_PR_PIF10
+#define EXTI_PR_PR11 EXTI_PR_PIF11
+#define EXTI_PR_PR12 EXTI_PR_PIF12
+#define EXTI_PR_PR13 EXTI_PR_PIF13
+#define EXTI_PR_PR14 EXTI_PR_PIF14
+#define EXTI_PR_PR15 EXTI_PR_PIF15
+#define EXTI_PR_PR16 EXTI_PR_PIF16
+#define EXTI_PR_PR17 EXTI_PR_PIF17
+#define EXTI_PR_PR19 EXTI_PR_PIF19
+#define EXTI_PR_PR20 EXTI_PR_PIF20
+#define EXTI_PR_PR21 EXTI_PR_PIF21
+#define EXTI_PR_PR22 EXTI_PR_PIF22
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
+#define FLASH_ACR_PRFTEN_Pos (1U)
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_SLEEP_PD_Pos (3U)
+#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD_Pos (4U)
+#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
+#define FLASH_ACR_DISAB_BUF_Pos (5U)
+#define FLASH_ACR_DISAB_BUF_Msk (0x1UL << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
+#define FLASH_ACR_PRE_READ_Pos (6U)
+#define FLASH_ACR_PRE_READ_Msk (0x1UL << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
+#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
+
+/******************* Bit definition for FLASH_PECR register ******************/
+#define FLASH_PECR_PELOCK_Pos (0U)
+#define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
+#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK_Pos (1U)
+#define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
+#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK_Pos (2U)
+#define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
+#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG_Pos (3U)
+#define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
+#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
+#define FLASH_PECR_DATA_Pos (4U)
+#define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
+#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
+#define FLASH_PECR_FIX_Pos (8U)
+#define FLASH_PECR_FIX_Msk (0x1UL << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
+#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE_Pos (9U)
+#define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
+#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
+#define FLASH_PECR_FPRG_Pos (10U)
+#define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
+#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_EOPIE_Pos (16U)
+#define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
+#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
+#define FLASH_PECR_ERRIE_Pos (17U)
+#define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
+#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
+#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
+#define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
+#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
+#define FLASH_PECR_HALF_ARRAY_Pos (19U)
+#define FLASH_PECR_HALF_ARRAY_Msk (0x1UL << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
+#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
+
+/****************** Bit definition for FLASH_PDKEYR register ******************/
+#define FLASH_PDKEYR_PDKEYR_Pos (0U)
+#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PEKEYR register ******************/
+#define FLASH_PEKEYR_PEKEYR_Pos (0U)
+#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PRGKEYR register ******************/
+#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
+#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
+
+/****************** Bit definition for FLASH_OPTKEYR register ******************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_EOP_Pos (1U)
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
+#define FLASH_SR_HVOFF_Pos (2U)
+#define FLASH_SR_HVOFF_Msk (0x1UL << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
+#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
+#define FLASH_SR_READY_Pos (3U)
+#define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */
+#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR_Pos (8U)
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
+#define FLASH_SR_PGAERR_Pos (9U)
+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR_Pos (10U)
+#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
+#define FLASH_SR_OPTVERR_Pos (11U)
+#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
+#define FLASH_SR_RDERR_Pos (13U)
+#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
+#define FLASH_SR_NOTZEROERR_Pos (16U)
+#define FLASH_SR_NOTZEROERR_Msk (0x1UL << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
+#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
+#define FLASH_SR_FWWERR_Pos (17U)
+#define FLASH_SR_FWWERR_Msk (0x1UL << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
+#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
+
+/* Legacy defines */
+#define FLASH_SR_FWWER FLASH_SR_FWWERR
+#define FLASH_SR_ENHV FLASH_SR_HVOFF
+#define FLASH_SR_ENDHV FLASH_SR_HVOFF
+
+/****************** Bit definition for FLASH_OPTR register *******************/
+#define FLASH_OPTR_RDPROT_Pos (0U)
+#define FLASH_OPTR_RDPROT_Msk (0xFFUL << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
+#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
+#define FLASH_OPTR_WPRMOD_Pos (8U)
+#define FLASH_OPTR_WPRMOD_Msk (0x1UL << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
+#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
+#define FLASH_OPTR_BOR_LEV_Pos (16U)
+#define FLASH_OPTR_BOR_LEV_Msk (0xFUL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
+#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OPTR_IWDG_SW_Pos (20U)
+#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
+#define FLASH_OPTR_nRST_STOP_Pos (21U)
+#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OPTR_nRST_STDBY_Pos (22U)
+#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OPTR_USER_Pos (20U)
+#define FLASH_OPTR_USER_Msk (0x7UL << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
+#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OPTR_BOOT1_Pos (31U)
+#define FLASH_OPTR_BOOT1_Msk (0x1UL << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
+#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 (0x00000001U)
+#define GPIO_OTYPER_OT_1 (0x00000002U)
+#define GPIO_OTYPER_OT_2 (0x00000004U)
+#define GPIO_OTYPER_OT_3 (0x00000008U)
+#define GPIO_OTYPER_OT_4 (0x00000010U)
+#define GPIO_OTYPER_OT_5 (0x00000020U)
+#define GPIO_OTYPER_OT_6 (0x00000040U)
+#define GPIO_OTYPER_OT_7 (0x00000080U)
+#define GPIO_OTYPER_OT_8 (0x00000100U)
+#define GPIO_OTYPER_OT_9 (0x00000200U)
+#define GPIO_OTYPER_OT_10 (0x00000400U)
+#define GPIO_OTYPER_OT_11 (0x00000800U)
+#define GPIO_OTYPER_OT_12 (0x00001000U)
+#define GPIO_OTYPER_OT_13 (0x00002000U)
+#define GPIO_OTYPER_OT_14 (0x00004000U)
+#define GPIO_OTYPER_OT_15 (0x00008000U)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDER_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
+#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDER_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
+#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDER_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
+#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDER_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
+#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDER_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
+#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDER_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
+#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDER_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
+#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDER_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
+#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDER_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
+#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDER_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
+#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDER_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
+#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDER_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
+#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDER_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
+#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDER_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
+#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDER_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
+#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDER_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
+#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 (0x00000001U)
+#define GPIO_BSRR_BS_1 (0x00000002U)
+#define GPIO_BSRR_BS_2 (0x00000004U)
+#define GPIO_BSRR_BS_3 (0x00000008U)
+#define GPIO_BSRR_BS_4 (0x00000010U)
+#define GPIO_BSRR_BS_5 (0x00000020U)
+#define GPIO_BSRR_BS_6 (0x00000040U)
+#define GPIO_BSRR_BS_7 (0x00000080U)
+#define GPIO_BSRR_BS_8 (0x00000100U)
+#define GPIO_BSRR_BS_9 (0x00000200U)
+#define GPIO_BSRR_BS_10 (0x00000400U)
+#define GPIO_BSRR_BS_11 (0x00000800U)
+#define GPIO_BSRR_BS_12 (0x00001000U)
+#define GPIO_BSRR_BS_13 (0x00002000U)
+#define GPIO_BSRR_BS_14 (0x00004000U)
+#define GPIO_BSRR_BS_15 (0x00008000U)
+#define GPIO_BSRR_BR_0 (0x00010000U)
+#define GPIO_BSRR_BR_1 (0x00020000U)
+#define GPIO_BSRR_BR_2 (0x00040000U)
+#define GPIO_BSRR_BR_3 (0x00080000U)
+#define GPIO_BSRR_BR_4 (0x00100000U)
+#define GPIO_BSRR_BR_5 (0x00200000U)
+#define GPIO_BSRR_BR_6 (0x00400000U)
+#define GPIO_BSRR_BR_7 (0x00800000U)
+#define GPIO_BSRR_BR_8 (0x01000000U)
+#define GPIO_BSRR_BR_9 (0x02000000U)
+#define GPIO_BSRR_BR_10 (0x04000000U)
+#define GPIO_BSRR_BR_11 (0x08000000U)
+#define GPIO_BSRR_BR_12 (0x10000000U)
+#define GPIO_BSRR_BR_13 (0x20000000U)
+#define GPIO_BSRR_BR_14 (0x40000000U)
+#define GPIO_BSRR_BR_15 (0x80000000U)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 (0x00000001U)
+#define GPIO_BRR_BR_1 (0x00000002U)
+#define GPIO_BRR_BR_2 (0x00000004U)
+#define GPIO_BRR_BR_3 (0x00000008U)
+#define GPIO_BRR_BR_4 (0x00000010U)
+#define GPIO_BRR_BR_5 (0x00000020U)
+#define GPIO_BRR_BR_6 (0x00000040U)
+#define GPIO_BRR_BR_7 (0x00000080U)
+#define GPIO_BRR_BR_8 (0x00000100U)
+#define GPIO_BRR_BR_9 (0x00000200U)
+#define GPIO_BRR_BR_10 (0x00000400U)
+#define GPIO_BRR_BR_11 (0x00000800U)
+#define GPIO_BRR_BR_12 (0x00001000U)
+#define GPIO_BRR_BR_13 (0x00002000U)
+#define GPIO_BRR_BR_14 (0x00004000U)
+#define GPIO_BRR_BR_15 (0x00008000U)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos (1U)
+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos (2U)
+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos (3U)
+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos (4U)
+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos (5U)
+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos (6U)
+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos (7U)
+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos (8U)
+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos (12U)
+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos (14U)
+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos (15U)
+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos (16U)
+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos (17U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos (18U)
+#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos (19U)
+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos (20U)
+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos (21U)
+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos (22U)
+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos (23U)
+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD_Pos (0U)
+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos (10U)
+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos (11U)
+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos (12U)
+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos (13U)
+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
+#define I2C_CR2_STOP_Pos (14U)
+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos (15U)
+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos (16U)
+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos (24U)
+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos (25U)
+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos (26U)
+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1_Pos (0U)
+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos (10U)
+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos (15U)
+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2_Pos (1U)
+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos (8U)
+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos (8U)
+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos (9U)
+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos (8U)
+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos (10U)
+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos (8U)
+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos (9U)
+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos (8U)
+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos (15U)
+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos (0U)
+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos (8U)
+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos (16U)
+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos (20U)
+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos (28U)
+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE_Pos (0U)
+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos (1U)
+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos (2U)
+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos (3U)
+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos (4U)
+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos (5U)
+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos (6U)
+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos (7U)
+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos (8U)
+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
+#define I2C_ISR_ARLO_Pos (9U)
+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos (10U)
+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos (11U)
+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos (12U)
+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos (13U)
+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos (15U)
+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
+#define I2C_ISR_DIR_Pos (16U)
+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos (17U)
+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF_Pos (3U)
+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos (4U)
+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos (5U)
+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos (8U)
+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos (9U)
+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos (10U)
+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos (11U)
+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos (12U)
+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos (13U)
+#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define I2C_PECR_PEC_Pos (0U)
+#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA_Pos (0U)
+#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA_Pos (0U)
+#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos (2U)
+#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN_Pos (0U)
+#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM_Pos (0U)
+#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos (1U)
+#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos (2U)
+#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos (3U)
+#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos (4U)
+#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos (5U)
+#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos (6U)
+#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF_Pos (0U)
+#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos (1U)
+#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos (3U)
+#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos (4U)
+#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos (5U)
+#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos (6U)
+#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos (0U)
+#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos (1U)
+#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos (3U)
+#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos (4U)
+#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos (5U)
+#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos (6U)
+#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos (0U)
+#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos (1U)
+#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos (3U)
+#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos (6U)
+#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos (9U)
+#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos (17U)
+#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos (19U)
+#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos (20U)
+#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos (21U)
+#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos (22U)
+#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos (24U)
+#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE_Pos (0U)
+#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos (1U)
+#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos (2U)
+#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP_Pos (0U)
+#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR_Pos (0U)
+#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT_Pos (0U)
+#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
+
+/******************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPSDSR_Pos (0U)
+#define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP_Pos (9U)
+#define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /*!< 0x00000200 */
+#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
+#define PWR_CR_FWU_Pos (10U)
+#define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /*!< 0x00000400 */
+#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
+
+#define PWR_CR_VOS_Pos (11U)
+#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x00001800 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /*!< 0x00000800 */
+#define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /*!< 0x00001000 */
+#define PWR_CR_DSEEKOFF_Pos (13U)
+#define PWR_CR_DSEEKOFF_Msk (0x1UL << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */
+#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */
+#define PWR_CR_LPRUN_Pos (14U)
+#define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
+#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_VREFINTRDYF_Pos (3U)
+#define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
+#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF_Pos (4U)
+#define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
+#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF_Pos (5U)
+#define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
+#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1_Pos (8U)
+#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2_Pos (9U)
+#define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
+#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP3_Pos (10U)
+#define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
+#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos (1U)
+#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos (2U)
+#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIVEN_Pos (3U)
+#define RCC_CR_HSIDIVEN_Msk (0x1UL << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */
+#define RCC_CR_HSIDIVF_Pos (4U)
+#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */
+#define RCC_CR_HSIOUTEN_Pos (5U)
+#define RCC_CR_HSIOUTEN_Msk (0x1UL << RCC_CR_HSIOUTEN_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_Msk /*!< Internal High Speed clock out enable */
+#define RCC_CR_MSION_Pos (8U)
+#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000100 */
+#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY_Pos (9U)
+#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
+#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON_Pos (19U)
+#define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */
+#define RCC_CR_RTCPRE_Pos (20U)
+#define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
+#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */
+#define RCC_CR_RTCPRE_0 (0x1UL << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */
+#define RCC_CR_RTCPRE_1 (0x2UL << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+/* Reference defines */
+#define RCC_CR_CSSON RCC_CR_CSSHSEON
+
+/******************** Bit definition for RCC_ICSCR register *****************/
+#define RCC_ICSCR_HSICAL_Pos (0U)
+#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
+#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM_Pos (8U)
+#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
+#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE_Pos (13U)
+#define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
+#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
+#define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
+#define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
+#define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
+#define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
+#define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
+#define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
+#define RCC_ICSCR_MSICAL_Pos (16U)
+#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
+#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM_Pos (24U)
+#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
+#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos (15U)
+#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */
+
+/*!< PLL entry clock source*/
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
+
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL_Pos (18U)
+#define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV_Pos (22U)
+#define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
+
+#define RCC_CFGR_PLLDIV2_Pos (22U)
+#define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3_Pos (23U)
+#define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4_Pos (22U)
+#define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCOSEL_Pos (24U)
+#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
+#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
+
+#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
+#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCOSEL_HSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_MSI_Pos (24U)
+#define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
+#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_HSE_Pos (26U)
+#define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCOSEL_PLL_Pos (24U)
+#define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
+#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
+#define RCC_CFGR_MCOSEL_LSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
+#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
+#define RCC_CFGR_MCOSEL_LSE_Pos (24U)
+#define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
+
+#define RCC_CFGR_MCOPRE_Pos (28U)
+#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
+
+#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
+
+/* Legacy defines */
+#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
+#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
+#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
+#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
+#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
+#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
+#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
+#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
+#ifdef RCC_CFGR_MCOSEL_HSI48
+#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48
+#endif
+
+#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
+#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
+
+/*!<****************** Bit definition for RCC_CIER register ********************/
+#define RCC_CIER_LSIRDYIE_Pos (0U)
+#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIER_LSERDYIE_Pos (1U)
+#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIER_HSIRDYIE_Pos (2U)
+#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIER_HSERDYIE_Pos (3U)
+#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIER_PLLRDYIE_Pos (4U)
+#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIER_MSIRDYIE_Pos (5U)
+#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
+#define RCC_CIER_CSSLSE_Pos (7U)
+#define RCC_CIER_CSSLSE_Msk (0x1UL << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */
+
+/* Reference defines */
+#define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
+
+/*!<****************** Bit definition for RCC_CIFR register ********************/
+#define RCC_CIFR_LSIRDYF_Pos (0U)
+#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIFR_LSERDYF_Pos (1U)
+#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIFR_HSIRDYF_Pos (2U)
+#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIFR_HSERDYF_Pos (3U)
+#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIFR_PLLRDYF_Pos (4U)
+#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIFR_MSIRDYF_Pos (5U)
+#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
+#define RCC_CIFR_CSSLSEF_Pos (7U)
+#define RCC_CIFR_CSSLSEF_Msk (0x1UL << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */
+#define RCC_CIFR_CSSHSEF_Pos (8U)
+#define RCC_CIFR_CSSHSEF_Msk (0x1UL << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */
+#define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */
+
+/* Reference defines */
+#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
+#define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
+
+/*!<****************** Bit definition for RCC_CICR register ********************/
+#define RCC_CICR_LSIRDYC_Pos (0U)
+#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CICR_LSERDYC_Pos (1U)
+#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CICR_HSIRDYC_Pos (2U)
+#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CICR_HSERDYC_Pos (3U)
+#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CICR_PLLRDYC_Pos (4U)
+#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CICR_MSIRDYC_Pos (5U)
+#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
+#define RCC_CICR_CSSLSEC_Pos (7U)
+#define RCC_CICR_CSSLSEC_Msk (0x1UL << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */
+#define RCC_CICR_CSSHSEC_Pos (8U)
+#define RCC_CICR_CSSHSEC_Msk (0x1UL << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */
+#define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */
+
+/* Reference defines */
+#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
+#define RCC_CICR_CSSC RCC_CICR_CSSHSEC
+/***************** Bit definition for RCC_IOPRSTR register ******************/
+#define RCC_IOPRSTR_IOPARST_Pos (0U)
+#define RCC_IOPRSTR_IOPARST_Msk (0x1UL << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */
+#define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */
+#define RCC_IOPRSTR_IOPBRST_Pos (1U)
+#define RCC_IOPRSTR_IOPBRST_Msk (0x1UL << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */
+#define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */
+#define RCC_IOPRSTR_IOPCRST_Pos (2U)
+#define RCC_IOPRSTR_IOPCRST_Msk (0x1UL << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */
+#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */
+#define RCC_IOPRSTR_IOPHRST_Pos (7U)
+#define RCC_IOPRSTR_IOPHRST_Msk (0x1UL << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */
+#define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */
+
+/* Reference defines */
+#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
+#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
+#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
+#define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
+
+
+/****************** Bit definition for RCC_AHBRST register ******************/
+#define RCC_AHBRSTR_DMARST_Pos (0U)
+#define RCC_AHBRSTR_DMARST_Msk (0x1UL << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */
+#define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */
+#define RCC_AHBRSTR_MIFRST_Pos (8U)
+#define RCC_AHBRSTR_MIFRST_Msk (0x1UL << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */
+#define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset */
+#define RCC_AHBRSTR_CRCRST_Pos (12U)
+#define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */
+
+/* Reference defines */
+#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
+#define RCC_APB2RSTR_TIM21RST_Pos (2U)
+#define RCC_APB2RSTR_TIM21RST_Msk (0x1UL << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 reset */
+#define RCC_APB2RSTR_ADCRST_Pos (9U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
+#define RCC_APB2RSTR_DBGRST_Pos (22U)
+#define RCC_APB2RSTR_DBGRST_Msk (0x1UL << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU reset */
+
+/* Reference defines */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 reset */
+#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU reset */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_LPUART1RST_Pos (18U)
+#define RCC_APB1RSTR_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
+#define RCC_APB1RSTR_LPTIM1RST_Pos (31U)
+#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 reset */
+
+/***************** Bit definition for RCC_IOPENR register ******************/
+#define RCC_IOPENR_IOPAEN_Pos (0U)
+#define RCC_IOPENR_IOPAEN_Msk (0x1UL << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */
+#define RCC_IOPENR_IOPBEN_Pos (1U)
+#define RCC_IOPENR_IOPBEN_Msk (0x1UL << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */
+#define RCC_IOPENR_IOPCEN_Pos (2U)
+#define RCC_IOPENR_IOPCEN_Msk (0x1UL << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */
+#define RCC_IOPENR_IOPHEN_Pos (7U)
+#define RCC_IOPENR_IOPHEN_Msk (0x1UL << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */
+
+/* Reference defines */
+#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
+#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
+#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
+#define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
+
+/***************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMAEN_Pos (0U)
+#define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_MIFEN_Pos (8U)
+#define RCC_AHBENR_MIFEN_Msk (0x1UL << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */
+#define RCC_AHBENR_CRCEN_Pos (12U)
+#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+
+/* Reference defines */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register ******************/
+#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM21EN_Pos (2U)
+#define RCC_APB2ENR_TIM21EN_Msk (0x1UL << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */
+#define RCC_APB2ENR_FWEN_Pos (7U)
+#define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADCEN_Pos (9U)
+#define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
+#define RCC_APB2ENR_DBGEN_Pos (22U)
+#define RCC_APB2ENR_DBGEN_Msk (0x1UL << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */
+
+/* Reference defines */
+
+#define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
+#define RCC_APB1ENR_LPUART1EN_Pos (18U)
+#define RCC_APB1ENR_LPUART1EN_Msk (0x1UL << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
+#define RCC_APB1ENR_LPTIM1EN_Pos (31U)
+#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */
+
+/****************** Bit definition for RCC_IOPSMENR register ****************/
+#define RCC_IOPSMENR_IOPASMEN_Pos (0U)
+#define RCC_IOPSMENR_IOPASMEN_Msk (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPBSMEN_Pos (1U)
+#define RCC_IOPSMENR_IOPBSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPCSMEN_Pos (2U)
+#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPHSMEN_Pos (7U)
+#define RCC_IOPSMENR_IOPHSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_AHBSMENR register ******************/
+#define RCC_AHBSMENR_DMASMEN_Pos (0U)
+#define RCC_AHBSMENR_DMASMEN_Msk (0x1UL << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */
+#define RCC_AHBSMENR_MIFSMEN_Pos (8U)
+#define RCC_AHBSMENR_MIFSMEN_Msk (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */
+#define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
+#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRCSMEN_Pos (12U)
+#define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB2SMENR register ******************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM21SMEN_Pos (2U)
+#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */
+#define RCC_APB2SMENR_ADCSMEN_Pos (9U)
+#define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
+#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGSMEN_Pos (22U)
+#define RCC_APB2SMENR_DBGSMEN_Msk (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB1SMENR register ******************/
+#define RCC_APB1SMENR_TIM2SMEN_Pos (0U)
+#define RCC_APB1SMENR_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_WWDGSMEN_Pos (11U)
+#define RCC_APB1SMENR_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART2SMEN_Pos (17U)
+#define RCC_APB1SMENR_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPUART1SMEN_Pos (18U)
+#define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C1SMEN_Pos (21U)
+#define RCC_APB1SMENR_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_PWRSMEN_Pos (28U)
+#define RCC_APB1SMENR_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U)
+#define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */
+
+/*!< USART2 Clock source selection */
+#define RCC_CCIPR_USART2SEL_Pos (2U)
+#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */
+#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+/*!< LPUART1 Clock source selection */
+#define RCC_CCIPR_LPUART1SEL_Pos (10U)
+#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */
+#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */
+#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CCIPR_I2C1SEL_Pos (12U)
+#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */
+#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
+
+
+/*!< LPTIM1 Clock source selection */
+#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
+#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */
+#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+/******************* Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSEON_Pos (8U)
+#define RCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */
+#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_CSR_LSERDY_Pos (9U)
+#define RCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */
+#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP_Pos (10U)
+#define RCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */
+#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_CSR_LSEDRV_Pos (11U)
+#define RCC_CSR_LSEDRV_Msk (0x3UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */
+#define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_CSR_LSEDRV_0 (0x1UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */
+#define RCC_CSR_LSEDRV_1 (0x2UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */
+
+#define RCC_CSR_LSECSSON_Pos (13U)
+#define RCC_CSR_LSECSSON_Msk (0x1UL << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */
+#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */
+#define RCC_CSR_LSECSSD_Pos (14U)
+#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
+#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
+
+/*!< RTC congiguration */
+#define RCC_CSR_RTCSEL_Pos (16U)
+#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
+
+#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CSR_RTCSEL_LSE_Pos (16U)
+#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_LSI_Pos (17U)
+#define RCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */
+#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_HSE_Pos (16U)
+#define RCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */
+
+#define RCC_CSR_RTCEN_Pos (18U)
+#define RCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */
+#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_CSR_RTCRST_Pos (19U)
+#define RCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */
+#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */
+
+#define RCC_CSR_RMVF_Pos (23U)
+#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_OBLRSTF_Pos (25U)
+#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+/* Reference defines */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER1_SUPPORT
+#define RTC_TAMPER2_SUPPORT
+#define RTC_TAMPER3_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk /*!< */
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk /*!< */
+#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk /*!< */
+#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */
+#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */
+#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk /*!< */
+#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk /*!< */
+#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk /*!< */
+#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk /*!< */
+#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */
+#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk /*!< */
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk /*!< */
+#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk /*!< */
+#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk /*!< */
+#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk /*!< */
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */
+#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk /*!< */
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< */
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */
+#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */
+#define RTC_ISR_TAMP3F_Pos (15U)
+#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk /*!< */
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */
+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */
+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */
+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */
+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */
+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */
+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */
+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */
+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */
+#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */
+#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */
+#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */
+#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */
+#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */
+#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */
+#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */
+#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */
+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */
+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */
+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */
+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */
+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */
+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */
+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */
+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */
+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */
+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CALR register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */
+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define RTC_CAL_CALP RTC_CALR_CALP
+#define RTC_CAL_CALW8 RTC_CALR_CALW8
+#define RTC_CAL_CALW16 RTC_CALR_CALW16
+#define RTC_CAL_CALM RTC_CALR_CALM
+#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
+
+/******************** Bits definition for RTC_TAMPCR register ****************/
+#define RTC_TAMPCR_TAMP3MF_Pos (24U)
+#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
+#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
+#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
+#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP3IE_Pos (22U)
+#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
+#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2MF_Pos (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2IE_Pos (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1MF_Pos (18U)
+#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
+#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1IE_Pos (16U)
+#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */
+#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */
+#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */
+#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos (7U)
+#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */
+#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
+#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
+#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP3E_Pos (5U)
+#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
+#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk /*!< */
+#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP2E_Pos (3U)
+#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */
+#define RTC_TAMPCR_TAMPIE_Pos (2U)
+#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
+#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP1E_Pos (0U)
+#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_OR register ****************/
+#define RTC_OR_OUT_RMP_Pos (1U)
+#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */
+#define RTC_OR_ALARMOUTTYPE_Pos (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */
+
+/* Legacy defines */
+#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk /*!< */
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER (0x00000005U) /*!< */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/******************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
+#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR1_BOOT_MODE_Pos (8U)
+#define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
+#define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */
+#define SYSCFG_CFGR1_BOOT_MODE_0 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOT_MODE_1 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_FWDISEN_Pos (0U)
+#define SYSCFG_CFGR2_FWDISEN_Msk (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
+
+
+/***************** Bit definition for SYSCFG_CFGR3 register ****************/
+#define SYSCFG_CFGR3_EN_VREFINT_Pos (0U)
+#define SYSCFG_CFGR3_EN_VREFINT_Msk (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_EN_VREFINT SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
+#define SYSCFG_CFGR3_VREF_OUT_Pos (4U)
+#define SYSCFG_CFGR3_VREF_OUT_Msk (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
+#define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */
+#define SYSCFG_CFGR3_VREF_OUT_0 (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
+#define SYSCFG_CFGR3_VREF_OUT_1 (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U)
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U)
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U)
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
+#define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U)
+#define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
+#define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
+#define SYSCFG_CFGR3_REF_LOCK_Pos (31U)
+#define SYSCFG_CFGR3_REF_LOCK_Msk (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
+#define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */
+
+/* Legacy defines */
+
+#define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
+#define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
+#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
+#define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+
+/******************************************************************************/
+/* */
+/* Timers (TIM)*/
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
+#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
+ || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#else
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#endif
+
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFUL << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFUL << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM2_OR_ETR_RMP_Pos (0U)
+#define TIM2_OR_ETR_RMP_Msk (0x7UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000007 */
+#define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
+#define TIM2_OR_ETR_RMP_0 (0x1UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM2_OR_ETR_RMP_1 (0x2UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM2_OR_ETR_RMP_2 (0x4UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000004 */
+#define TIM2_OR_TI4_RMP_Pos (3U)
+#define TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000018 */
+#define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
+#define TIM2_OR_TI4_RMP_0 (0x1UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */
+#define TIM2_OR_TI4_RMP_1 (0x2UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000010 */
+
+#define TIM21_OR_ETR_RMP_Pos (0U)
+#define TIM21_OR_ETR_RMP_Msk (0x3UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
+#define TIM21_OR_ETR_RMP_0 (0x1UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM21_OR_ETR_RMP_1 (0x2UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM21_OR_TI1_RMP_Pos (2U)
+#define TIM21_OR_TI1_RMP_Msk (0x7UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x0000001C */
+#define TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
+#define TIM21_OR_TI1_RMP_0 (0x1UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM21_OR_TI1_RMP_1 (0x2UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+#define TIM21_OR_TI1_RMP_2 (0x4UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000010 */
+#define TIM21_OR_TI2_RMP_Pos (5U)
+#define TIM21_OR_TI2_RMP_Msk (0x1UL << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */
+#define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE_Pos (0U)
+#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+#define USART_CR1_UESM_Pos (1U)
+#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
+#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_M0_Pos (12U)
+#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
+#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos (13U)
+#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos (14U)
+#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos (16U)
+#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
+#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
+#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
+#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
+#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos (21U)
+#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
+#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
+#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
+#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
+#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos (26U)
+#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos (27U)
+#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos (28U)
+#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
+#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7_Pos (4U)
+#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos (15U)
+#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos (16U)
+#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos (17U)
+#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos (18U)
+#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos (19U)
+#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos (20U)
+#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos (21U)
+#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos (23U)
+#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos (24U)
+#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos (12U)
+#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos (13U)
+#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos (14U)
+#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos (15U)
+#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos (17U)
+#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos (20U)
+#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
+#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
+#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos (22U)
+#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
+#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
+#define USART_CR3_UCESM_Pos (23U)
+#define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
+#define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION_Pos (0U)
+#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos (4U)
+#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO_Pos (0U)
+#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos (24U)
+#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ_Pos (0U)
+#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
+#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos (1U)
+#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
+#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos (2U)
+#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
+#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos (3U)
+#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
+#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos (4U)
+#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
+#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE_Pos (0U)
+#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
+#define USART_ISR_FE_Pos (1U)
+#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
+#define USART_ISR_NE_Pos (2U)
+#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos (3U)
+#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos (4U)
+#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos (5U)
+#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos (6U)
+#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos (7U)
+#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
+#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos (8U)
+#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos (9U)
+#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos (10U)
+#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
+#define USART_ISR_RTOF_Pos (11U)
+#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos (12U)
+#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos (14U)
+#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos (15U)
+#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos (16U)
+#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
+#define USART_ISR_CMF_Pos (17U)
+#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos (18U)
+#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos (19U)
+#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos (20U)
+#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
+#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos (21U)
+#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos (22U)
+#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
+#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF_Pos (0U)
+#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos (1U)
+#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos (2U)
+#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */
+#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos (3U)
+#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos (4U)
+#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos (6U)
+#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF_Pos (8U)
+#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos (9U)
+#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos (11U)
+#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos (12U)
+#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos (17U)
+#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos (20U)
+#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
+#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
+
+/* Compatibility defines with other series */
+#define USART_ICR_NECF USART_ICR_NCF
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR_Pos (0U)
+#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR_Pos (0U)
+#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOH))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
+
+
+
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SMBUS Instances *****************************/
+#define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/************* LPTIM instances supporting the encoder mode feature ************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM21) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/******************* TIM Instances : output(s) OCXEC register *****************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (1 == 0)
+
+/****************** USART Instances : Auto Baud Rate detection ****************/
+
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (1 == 0)
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (1==0)
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (1==0)
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (1==0)
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32L0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32L0 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+
+#define RNG_LPUART1_IRQn LPUART1_IRQn
+#define AES_LPUART1_IRQn LPUART1_IRQn
+#define AES_RNG_LPUART1_IRQn LPUART1_IRQn
+#define RCC_CRS_IRQn RCC_IRQn
+#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
+#define ADC1_COMP_IRQn ADC1_IRQn
+
+/* Aliases for __IRQHandler */
+#define RNG_LPUART1_IRQHandler LPUART1_IRQHandler
+#define AES_LPUART1_IRQHandler LPUART1_IRQHandler
+#define AES_RNG_LPUART1_IRQHandler LPUART1_IRQHandler
+#define RCC_CRS_IRQHandler RCC_IRQHandler
+#define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
+#define ADC1_COMP_IRQHandler ADC1_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L010x6_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/CMSIS/device/stm32l010x8.h b/CMSIS/device/stm32l010x8.h
new file mode 100644
index 0000000..444a53a
--- /dev/null
+++ b/CMSIS/device/stm32l010x8.h
@@ -0,0 +1,5856 @@
+/**
+ ******************************************************************************
+ * @file stm32l010x8.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for stm32l010x8 devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright(c) 2018 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l010x8
+ * @{
+ */
+
+#ifndef __STM32L010x8_H
+#define __STM32L010x8_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 0U /*!< STM32L0xx provides no MPU */
+#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
+#define __NVIC_PRIO_BITS 2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief stm32l010x8 Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+/*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
+
+/****** STM32L-0 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */
+ RCC_IRQn = 4, /*!< RCC Interrupt */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
+ ADC1_IRQn = 12, /*!< ADC1 Interrupt */
+ LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 Interrupt */
+ TIM21_IRQn = 20, /*!< TIM21 Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ USART2_IRQn = 28, /*!< USART2 Interrupt */
+ LPUART1_IRQn = 29, /*!< LPUART1 Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0plus.h"
+#include "system_stm32l0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+ uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+} ADC_Common_TypeDef;
+
+
+
+/**
+* @brief CRC calculation unit
+*/
+
+typedef struct
+{
+__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+uint8_t RESERVED0; /*!< Reserved, 0x05 */
+uint16_t RESERVED1; /*!< Reserved, 0x06 */
+__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+uint32_t RESERVED2; /*!< Reserved, 0x0C */
+__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
+} DMA_Request_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
+ __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
+ __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
+ __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
+ __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
+ __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
+ __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
+ __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
+ __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
+ __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
+} OB_TypeDef;
+
+
+/**
+ * @brief General Purpose IO
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief LPTIMIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+} LPTIM_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+ * @brief Independent WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
+ __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
+ __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
+ __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
+ __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
+ __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
+ __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
+ __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
+ __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
+ __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
+ __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */
+
+#define DATA_EEPROM_BASE (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
+#define DATA_EEPROM_END (0x080800FFUL) /*!< DATA EEPROM end address in the alias region */
+#define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */
+#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8KBytes) */
+
+#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000UL)
+
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
+#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800UL)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
+#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL)
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL)
+#define TIM21_BASE (APBPERIPH_BASE + 0x00010800UL)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708UL)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
+#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL)
+
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
+#define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */
+#define FLASHSIZE_BASE (0x1FF8007CUL) /*!< FLASH Size register base address */
+#define UID_BASE (0x1FF80050UL) /*!< Unique device ID register base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
+
+#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL)
+#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL)
+#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL)
+#define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00UL)
+#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00UL)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
+/* Legacy defines */
+#define ADC ADC1_COMMON
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_EOCAL_Pos (11U)
+#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
+#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
+#define ADC_ISR_AWD_Pos (7U)
+#define ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
+#define ADC_ISR_EOSEQ_Pos (3U)
+#define ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_EOCALIE_Pos (11U)
+#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
+#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
+#define ADC_IER_AWDIE_Pos (7U)
+#define ADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE_Pos (3U)
+#define ADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH_Pos (26U)
+#define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
+#define ADC_CFGR1_AWDEN_Pos (23U)
+#define ADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL_Pos (22U)
+#define ADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN_Pos (16U)
+#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF_Pos (15U)
+#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
+#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT_Pos (14U)
+#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
+#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT_Pos (13U)
+#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD_Pos (12U)
+#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN_Pos (10U)
+#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
+#define ADC_CFGR1_EXTSEL_Pos (6U)
+#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
+#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
+#define ADC_CFGR1_ALIGN_Pos (5U)
+#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
+#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
+#define ADC_CFGR1_RES_Pos (3U)
+#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
+#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
+#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
+#define ADC_CFGR1_SCANDIR_Pos (2U)
+#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG_Pos (1U)
+#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
+#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN_Pos (0U)
+#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
+#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_TOVS_Pos (9U)
+#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
+#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+#define ADC_CFGR2_OVSR_Pos (2U)
+#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
+#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+#define ADC_CFGR2_OVSE_Pos (0U)
+#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
+#define ADC_CFGR2_CKMODE_Pos (30U)
+#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
+#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
+#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
+#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
+
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP_Pos (0U)
+#define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
+#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
+#define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
+#define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define ADC_SMPR_SMPR ADC_SMPR_SMP
+#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
+#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
+#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT_Pos (16U)
+#define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
+#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
+#define ADC_TR_LT_Pos (0U)
+#define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL_Pos (0U)
+#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
+#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
+#define ADC_CHSELR_CHSEL18_Pos (18U)
+#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17_Pos (17U)
+#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
+#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL15_Pos (15U)
+#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
+#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14_Pos (14U)
+#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
+#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13_Pos (13U)
+#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
+#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12_Pos (12U)
+#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
+#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11_Pos (11U)
+#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
+#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10_Pos (10U)
+#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
+#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9_Pos (9U)
+#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
+#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8_Pos (8U)
+#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
+#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7_Pos (7U)
+#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
+#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6_Pos (6U)
+#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
+#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5_Pos (5U)
+#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
+#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4_Pos (4U)
+#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
+#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3_Pos (3U)
+#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
+#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2_Pos (2U)
+#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
+#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1_Pos (1U)
+#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
+#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0_Pos (0U)
+#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
+#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_CALFACT_Pos (0U)
+#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_LFMEN_Pos (25U)
+#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
+#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR (0xFFU) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos (3U)
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos (5U)
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos (7U)
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT_Pos (0U)
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL_Pos (0U)
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_Pos (0U)
+#define DBGMCU_CR_DBG_Msk (0x7UL << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
+#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+
+/******************* Bit definition for DMA_CSELR register *******************/
+#define DMA_CSELR_C1S_Pos (0U)
+#define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
+#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos (4U)
+#define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
+#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos (8U)
+#define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
+#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos (12U)
+#define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
+#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos (16U)
+#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
+#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S_Pos (20U)
+#define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
+#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S_Pos (24U)
+#define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
+#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_IM0_Pos (0U)
+#define EXTI_IMR_IM0_Msk (0x1UL << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_IM1_Pos (1U)
+#define EXTI_IMR_IM1_Msk (0x1UL << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_IM2_Pos (2U)
+#define EXTI_IMR_IM2_Msk (0x1UL << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_IM3_Pos (3U)
+#define EXTI_IMR_IM3_Msk (0x1UL << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_IM4_Pos (4U)
+#define EXTI_IMR_IM4_Msk (0x1UL << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_IM5_Pos (5U)
+#define EXTI_IMR_IM5_Msk (0x1UL << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_IM6_Pos (6U)
+#define EXTI_IMR_IM6_Msk (0x1UL << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_IM7_Pos (7U)
+#define EXTI_IMR_IM7_Msk (0x1UL << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_IM8_Pos (8U)
+#define EXTI_IMR_IM8_Msk (0x1UL << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_IM9_Pos (9U)
+#define EXTI_IMR_IM9_Msk (0x1UL << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_IM10_Pos (10U)
+#define EXTI_IMR_IM10_Msk (0x1UL << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_IM11_Pos (11U)
+#define EXTI_IMR_IM11_Msk (0x1UL << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_IM12_Pos (12U)
+#define EXTI_IMR_IM12_Msk (0x1UL << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_IM13_Pos (13U)
+#define EXTI_IMR_IM13_Msk (0x1UL << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_IM14_Pos (14U)
+#define EXTI_IMR_IM14_Msk (0x1UL << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_IM15_Pos (15U)
+#define EXTI_IMR_IM15_Msk (0x1UL << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_IM17_Pos (17U)
+#define EXTI_IMR_IM17_Msk (0x1UL << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_IM19_Pos (19U)
+#define EXTI_IMR_IM19_Msk (0x1UL << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_IM20_Pos (20U)
+#define EXTI_IMR_IM20_Msk (0x1UL << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_IM23_Pos (23U)
+#define EXTI_IMR_IM23_Msk (0x1UL << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
+#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_IM26_Pos (26U)
+#define EXTI_IMR_IM26_Msk (0x1UL << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
+#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_IM28_Pos (28U)
+#define EXTI_IMR_IM28_Msk (0x1UL << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
+#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_IM29_Pos (29U)
+#define EXTI_IMR_IM29_Msk (0x1UL << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
+#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
+
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x36FFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x36FFFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_EM0_Pos (0U)
+#define EXTI_EMR_EM0_Msk (0x1UL << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_EM1_Pos (1U)
+#define EXTI_EMR_EM1_Msk (0x1UL << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_EM2_Pos (2U)
+#define EXTI_EMR_EM2_Msk (0x1UL << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_EM3_Pos (3U)
+#define EXTI_EMR_EM3_Msk (0x1UL << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_EM4_Pos (4U)
+#define EXTI_EMR_EM4_Msk (0x1UL << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_EM5_Pos (5U)
+#define EXTI_EMR_EM5_Msk (0x1UL << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_EM6_Pos (6U)
+#define EXTI_EMR_EM6_Msk (0x1UL << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_EM7_Pos (7U)
+#define EXTI_EMR_EM7_Msk (0x1UL << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_EM8_Pos (8U)
+#define EXTI_EMR_EM8_Msk (0x1UL << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_EM9_Pos (9U)
+#define EXTI_EMR_EM9_Msk (0x1UL << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_EM10_Pos (10U)
+#define EXTI_EMR_EM10_Msk (0x1UL << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_EM11_Pos (11U)
+#define EXTI_EMR_EM11_Msk (0x1UL << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_EM12_Pos (12U)
+#define EXTI_EMR_EM12_Msk (0x1UL << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_EM13_Pos (13U)
+#define EXTI_EMR_EM13_Msk (0x1UL << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_EM14_Pos (14U)
+#define EXTI_EMR_EM14_Msk (0x1UL << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_EM15_Pos (15U)
+#define EXTI_EMR_EM15_Msk (0x1UL << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_EM17_Pos (17U)
+#define EXTI_EMR_EM17_Msk (0x1UL << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_EM19_Pos (19U)
+#define EXTI_EMR_EM19_Msk (0x1UL << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_EM20_Pos (20U)
+#define EXTI_EMR_EM20_Msk (0x1UL << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_EM23_Pos (23U)
+#define EXTI_EMR_EM23_Msk (0x1UL << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
+#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
+#define EXTI_EMR_EM26_Pos (26U)
+#define EXTI_EMR_EM26_Msk (0x1UL << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
+#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
+#define EXTI_EMR_EM28_Pos (28U)
+#define EXTI_EMR_EM28_Msk (0x1UL << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
+#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
+#define EXTI_EMR_EM29_Pos (29U)
+#define EXTI_EMR_EM29_Msk (0x1UL << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
+#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_RT0_Pos (0U)
+#define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_RT1_Pos (1U)
+#define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_RT2_Pos (2U)
+#define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_RT3_Pos (3U)
+#define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_RT4_Pos (4U)
+#define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_RT5_Pos (5U)
+#define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_RT6_Pos (6U)
+#define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_RT7_Pos (7U)
+#define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_RT8_Pos (8U)
+#define EXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_RT9_Pos (9U)
+#define EXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_RT10_Pos (10U)
+#define EXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_RT11_Pos (11U)
+#define EXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_RT12_Pos (12U)
+#define EXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_RT13_Pos (13U)
+#define EXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_RT14_Pos (14U)
+#define EXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_RT15_Pos (15U)
+#define EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_RT16_Pos (16U)
+#define EXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_RT17_Pos (17U)
+#define EXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_RT19_Pos (19U)
+#define EXTI_RTSR_RT19_Msk (0x1UL << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_RT20_Pos (20U)
+#define EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_RT21_Pos (21U)
+#define EXTI_RTSR_RT21_Msk (0x1UL << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_RT22_Pos (22U)
+#define EXTI_RTSR_RT22_Msk (0x1UL << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
+#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
+#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
+#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
+#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
+#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
+#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
+#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
+#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
+#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
+#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
+#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
+#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
+#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
+#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
+#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
+#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
+#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
+#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
+#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
+#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
+#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_FT0_Pos (0U)
+#define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_FT1_Pos (1U)
+#define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_FT2_Pos (2U)
+#define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_FT3_Pos (3U)
+#define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_FT4_Pos (4U)
+#define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_FT5_Pos (5U)
+#define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_FT6_Pos (6U)
+#define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_FT7_Pos (7U)
+#define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_FT8_Pos (8U)
+#define EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_FT9_Pos (9U)
+#define EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_FT10_Pos (10U)
+#define EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_FT11_Pos (11U)
+#define EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_FT12_Pos (12U)
+#define EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_FT13_Pos (13U)
+#define EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_FT14_Pos (14U)
+#define EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_FT15_Pos (15U)
+#define EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_FT16_Pos (16U)
+#define EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_FT17_Pos (17U)
+#define EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_FT19_Pos (19U)
+#define EXTI_FTSR_FT19_Msk (0x1UL << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_FT20_Pos (20U)
+#define EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_FT21_Pos (21U)
+#define EXTI_FTSR_FT21_Msk (0x1UL << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_FT22_Pos (22U)
+#define EXTI_FTSR_FT22_Msk (0x1UL << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
+#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
+#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
+#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
+#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
+#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
+#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
+#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
+#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
+#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
+#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
+#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
+#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
+#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
+#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
+#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
+#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
+#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
+#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
+#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
+#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
+#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWI0_Pos (0U)
+#define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWI1_Pos (1U)
+#define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWI2_Pos (2U)
+#define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWI3_Pos (3U)
+#define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWI4_Pos (4U)
+#define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWI5_Pos (5U)
+#define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWI6_Pos (6U)
+#define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWI7_Pos (7U)
+#define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWI8_Pos (8U)
+#define EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWI9_Pos (9U)
+#define EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWI10_Pos (10U)
+#define EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWI11_Pos (11U)
+#define EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWI12_Pos (12U)
+#define EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWI13_Pos (13U)
+#define EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWI14_Pos (14U)
+#define EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWI15_Pos (15U)
+#define EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWI16_Pos (16U)
+#define EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWI17_Pos (17U)
+#define EXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWI19_Pos (19U)
+#define EXTI_SWIER_SWI19_Msk (0x1UL << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWI20_Pos (20U)
+#define EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWI21_Pos (21U)
+#define EXTI_SWIER_SWI21_Msk (0x1UL << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWI22_Pos (22U)
+#define EXTI_SWIER_SWI22_Msk (0x1UL << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
+
+/* Legacy defines */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PIF0_Pos (0U)
+#define EXTI_PR_PIF0_Msk (0x1UL << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
+#define EXTI_PR_PIF1_Pos (1U)
+#define EXTI_PR_PIF1_Msk (0x1UL << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
+#define EXTI_PR_PIF2_Pos (2U)
+#define EXTI_PR_PIF2_Msk (0x1UL << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
+#define EXTI_PR_PIF3_Pos (3U)
+#define EXTI_PR_PIF3_Msk (0x1UL << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
+#define EXTI_PR_PIF4_Pos (4U)
+#define EXTI_PR_PIF4_Msk (0x1UL << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
+#define EXTI_PR_PIF5_Pos (5U)
+#define EXTI_PR_PIF5_Msk (0x1UL << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
+#define EXTI_PR_PIF6_Pos (6U)
+#define EXTI_PR_PIF6_Msk (0x1UL << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
+#define EXTI_PR_PIF7_Pos (7U)
+#define EXTI_PR_PIF7_Msk (0x1UL << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
+#define EXTI_PR_PIF8_Pos (8U)
+#define EXTI_PR_PIF8_Msk (0x1UL << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
+#define EXTI_PR_PIF9_Pos (9U)
+#define EXTI_PR_PIF9_Msk (0x1UL << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
+#define EXTI_PR_PIF10_Pos (10U)
+#define EXTI_PR_PIF10_Msk (0x1UL << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
+#define EXTI_PR_PIF11_Pos (11U)
+#define EXTI_PR_PIF11_Msk (0x1UL << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
+#define EXTI_PR_PIF12_Pos (12U)
+#define EXTI_PR_PIF12_Msk (0x1UL << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
+#define EXTI_PR_PIF13_Pos (13U)
+#define EXTI_PR_PIF13_Msk (0x1UL << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
+#define EXTI_PR_PIF14_Pos (14U)
+#define EXTI_PR_PIF14_Msk (0x1UL << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
+#define EXTI_PR_PIF15_Pos (15U)
+#define EXTI_PR_PIF15_Msk (0x1UL << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
+#define EXTI_PR_PIF16_Pos (16U)
+#define EXTI_PR_PIF16_Msk (0x1UL << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
+#define EXTI_PR_PIF17_Pos (17U)
+#define EXTI_PR_PIF17_Msk (0x1UL << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
+#define EXTI_PR_PIF19_Pos (19U)
+#define EXTI_PR_PIF19_Msk (0x1UL << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
+#define EXTI_PR_PIF20_Pos (20U)
+#define EXTI_PR_PIF20_Msk (0x1UL << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
+#define EXTI_PR_PIF21_Pos (21U)
+#define EXTI_PR_PIF21_Msk (0x1UL << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
+#define EXTI_PR_PIF22_Pos (22U)
+#define EXTI_PR_PIF22_Msk (0x1UL << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
+
+/* Legacy defines */
+#define EXTI_PR_PR0 EXTI_PR_PIF0
+#define EXTI_PR_PR1 EXTI_PR_PIF1
+#define EXTI_PR_PR2 EXTI_PR_PIF2
+#define EXTI_PR_PR3 EXTI_PR_PIF3
+#define EXTI_PR_PR4 EXTI_PR_PIF4
+#define EXTI_PR_PR5 EXTI_PR_PIF5
+#define EXTI_PR_PR6 EXTI_PR_PIF6
+#define EXTI_PR_PR7 EXTI_PR_PIF7
+#define EXTI_PR_PR8 EXTI_PR_PIF8
+#define EXTI_PR_PR9 EXTI_PR_PIF9
+#define EXTI_PR_PR10 EXTI_PR_PIF10
+#define EXTI_PR_PR11 EXTI_PR_PIF11
+#define EXTI_PR_PR12 EXTI_PR_PIF12
+#define EXTI_PR_PR13 EXTI_PR_PIF13
+#define EXTI_PR_PR14 EXTI_PR_PIF14
+#define EXTI_PR_PR15 EXTI_PR_PIF15
+#define EXTI_PR_PR16 EXTI_PR_PIF16
+#define EXTI_PR_PR17 EXTI_PR_PIF17
+#define EXTI_PR_PR19 EXTI_PR_PIF19
+#define EXTI_PR_PR20 EXTI_PR_PIF20
+#define EXTI_PR_PR21 EXTI_PR_PIF21
+#define EXTI_PR_PR22 EXTI_PR_PIF22
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
+#define FLASH_ACR_PRFTEN_Pos (1U)
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_SLEEP_PD_Pos (3U)
+#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD_Pos (4U)
+#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
+#define FLASH_ACR_DISAB_BUF_Pos (5U)
+#define FLASH_ACR_DISAB_BUF_Msk (0x1UL << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
+#define FLASH_ACR_PRE_READ_Pos (6U)
+#define FLASH_ACR_PRE_READ_Msk (0x1UL << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
+#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
+
+/******************* Bit definition for FLASH_PECR register ******************/
+#define FLASH_PECR_PELOCK_Pos (0U)
+#define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
+#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK_Pos (1U)
+#define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
+#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK_Pos (2U)
+#define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
+#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG_Pos (3U)
+#define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
+#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
+#define FLASH_PECR_DATA_Pos (4U)
+#define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
+#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
+#define FLASH_PECR_FIX_Pos (8U)
+#define FLASH_PECR_FIX_Msk (0x1UL << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
+#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE_Pos (9U)
+#define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
+#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
+#define FLASH_PECR_FPRG_Pos (10U)
+#define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
+#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_EOPIE_Pos (16U)
+#define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
+#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
+#define FLASH_PECR_ERRIE_Pos (17U)
+#define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
+#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
+#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
+#define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
+#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
+#define FLASH_PECR_HALF_ARRAY_Pos (19U)
+#define FLASH_PECR_HALF_ARRAY_Msk (0x1UL << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
+#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
+
+/****************** Bit definition for FLASH_PDKEYR register ******************/
+#define FLASH_PDKEYR_PDKEYR_Pos (0U)
+#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PEKEYR register ******************/
+#define FLASH_PEKEYR_PEKEYR_Pos (0U)
+#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PRGKEYR register ******************/
+#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
+#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
+
+/****************** Bit definition for FLASH_OPTKEYR register ******************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_EOP_Pos (1U)
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
+#define FLASH_SR_HVOFF_Pos (2U)
+#define FLASH_SR_HVOFF_Msk (0x1UL << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
+#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
+#define FLASH_SR_READY_Pos (3U)
+#define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */
+#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR_Pos (8U)
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
+#define FLASH_SR_PGAERR_Pos (9U)
+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR_Pos (10U)
+#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
+#define FLASH_SR_OPTVERR_Pos (11U)
+#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
+#define FLASH_SR_RDERR_Pos (13U)
+#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
+#define FLASH_SR_NOTZEROERR_Pos (16U)
+#define FLASH_SR_NOTZEROERR_Msk (0x1UL << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
+#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
+#define FLASH_SR_FWWERR_Pos (17U)
+#define FLASH_SR_FWWERR_Msk (0x1UL << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
+#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
+
+/* Legacy defines */
+#define FLASH_SR_FWWER FLASH_SR_FWWERR
+#define FLASH_SR_ENHV FLASH_SR_HVOFF
+#define FLASH_SR_ENDHV FLASH_SR_HVOFF
+
+/****************** Bit definition for FLASH_OPTR register *******************/
+#define FLASH_OPTR_RDPROT_Pos (0U)
+#define FLASH_OPTR_RDPROT_Msk (0xFFUL << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
+#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
+#define FLASH_OPTR_WPRMOD_Pos (8U)
+#define FLASH_OPTR_WPRMOD_Msk (0x1UL << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
+#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
+#define FLASH_OPTR_BOR_LEV_Pos (16U)
+#define FLASH_OPTR_BOR_LEV_Msk (0xFUL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
+#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OPTR_IWDG_SW_Pos (20U)
+#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
+#define FLASH_OPTR_nRST_STOP_Pos (21U)
+#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OPTR_nRST_STDBY_Pos (22U)
+#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OPTR_USER_Pos (20U)
+#define FLASH_OPTR_USER_Msk (0x7UL << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
+#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OPTR_BOOT1_Pos (31U)
+#define FLASH_OPTR_BOOT1_Msk (0x1UL << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
+#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 (0x00000001U)
+#define GPIO_OTYPER_OT_1 (0x00000002U)
+#define GPIO_OTYPER_OT_2 (0x00000004U)
+#define GPIO_OTYPER_OT_3 (0x00000008U)
+#define GPIO_OTYPER_OT_4 (0x00000010U)
+#define GPIO_OTYPER_OT_5 (0x00000020U)
+#define GPIO_OTYPER_OT_6 (0x00000040U)
+#define GPIO_OTYPER_OT_7 (0x00000080U)
+#define GPIO_OTYPER_OT_8 (0x00000100U)
+#define GPIO_OTYPER_OT_9 (0x00000200U)
+#define GPIO_OTYPER_OT_10 (0x00000400U)
+#define GPIO_OTYPER_OT_11 (0x00000800U)
+#define GPIO_OTYPER_OT_12 (0x00001000U)
+#define GPIO_OTYPER_OT_13 (0x00002000U)
+#define GPIO_OTYPER_OT_14 (0x00004000U)
+#define GPIO_OTYPER_OT_15 (0x00008000U)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDER_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
+#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDER_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
+#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDER_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
+#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDER_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
+#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDER_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
+#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDER_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
+#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDER_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
+#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDER_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
+#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDER_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
+#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDER_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
+#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDER_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
+#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDER_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
+#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDER_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
+#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDER_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
+#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDER_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
+#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDER_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
+#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 (0x00000001U)
+#define GPIO_BSRR_BS_1 (0x00000002U)
+#define GPIO_BSRR_BS_2 (0x00000004U)
+#define GPIO_BSRR_BS_3 (0x00000008U)
+#define GPIO_BSRR_BS_4 (0x00000010U)
+#define GPIO_BSRR_BS_5 (0x00000020U)
+#define GPIO_BSRR_BS_6 (0x00000040U)
+#define GPIO_BSRR_BS_7 (0x00000080U)
+#define GPIO_BSRR_BS_8 (0x00000100U)
+#define GPIO_BSRR_BS_9 (0x00000200U)
+#define GPIO_BSRR_BS_10 (0x00000400U)
+#define GPIO_BSRR_BS_11 (0x00000800U)
+#define GPIO_BSRR_BS_12 (0x00001000U)
+#define GPIO_BSRR_BS_13 (0x00002000U)
+#define GPIO_BSRR_BS_14 (0x00004000U)
+#define GPIO_BSRR_BS_15 (0x00008000U)
+#define GPIO_BSRR_BR_0 (0x00010000U)
+#define GPIO_BSRR_BR_1 (0x00020000U)
+#define GPIO_BSRR_BR_2 (0x00040000U)
+#define GPIO_BSRR_BR_3 (0x00080000U)
+#define GPIO_BSRR_BR_4 (0x00100000U)
+#define GPIO_BSRR_BR_5 (0x00200000U)
+#define GPIO_BSRR_BR_6 (0x00400000U)
+#define GPIO_BSRR_BR_7 (0x00800000U)
+#define GPIO_BSRR_BR_8 (0x01000000U)
+#define GPIO_BSRR_BR_9 (0x02000000U)
+#define GPIO_BSRR_BR_10 (0x04000000U)
+#define GPIO_BSRR_BR_11 (0x08000000U)
+#define GPIO_BSRR_BR_12 (0x10000000U)
+#define GPIO_BSRR_BR_13 (0x20000000U)
+#define GPIO_BSRR_BR_14 (0x40000000U)
+#define GPIO_BSRR_BR_15 (0x80000000U)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 (0x00000001U)
+#define GPIO_BRR_BR_1 (0x00000002U)
+#define GPIO_BRR_BR_2 (0x00000004U)
+#define GPIO_BRR_BR_3 (0x00000008U)
+#define GPIO_BRR_BR_4 (0x00000010U)
+#define GPIO_BRR_BR_5 (0x00000020U)
+#define GPIO_BRR_BR_6 (0x00000040U)
+#define GPIO_BRR_BR_7 (0x00000080U)
+#define GPIO_BRR_BR_8 (0x00000100U)
+#define GPIO_BRR_BR_9 (0x00000200U)
+#define GPIO_BRR_BR_10 (0x00000400U)
+#define GPIO_BRR_BR_11 (0x00000800U)
+#define GPIO_BRR_BR_12 (0x00001000U)
+#define GPIO_BRR_BR_13 (0x00002000U)
+#define GPIO_BRR_BR_14 (0x00004000U)
+#define GPIO_BRR_BR_15 (0x00008000U)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos (1U)
+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos (2U)
+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos (3U)
+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos (4U)
+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos (5U)
+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos (6U)
+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos (7U)
+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos (8U)
+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos (12U)
+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos (14U)
+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos (15U)
+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos (16U)
+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos (17U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos (18U)
+#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos (19U)
+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos (20U)
+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos (21U)
+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos (22U)
+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos (23U)
+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD_Pos (0U)
+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos (10U)
+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos (11U)
+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos (12U)
+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos (13U)
+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
+#define I2C_CR2_STOP_Pos (14U)
+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos (15U)
+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos (16U)
+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos (24U)
+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos (25U)
+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos (26U)
+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1_Pos (0U)
+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos (10U)
+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos (15U)
+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2_Pos (1U)
+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos (8U)
+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos (8U)
+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos (9U)
+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos (8U)
+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos (10U)
+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos (8U)
+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos (9U)
+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos (8U)
+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos (15U)
+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos (0U)
+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos (8U)
+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos (16U)
+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos (20U)
+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos (28U)
+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE_Pos (0U)
+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos (1U)
+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos (2U)
+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos (3U)
+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos (4U)
+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos (5U)
+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos (6U)
+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos (7U)
+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos (8U)
+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
+#define I2C_ISR_ARLO_Pos (9U)
+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos (10U)
+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos (11U)
+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos (12U)
+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos (13U)
+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos (15U)
+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
+#define I2C_ISR_DIR_Pos (16U)
+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos (17U)
+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF_Pos (3U)
+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos (4U)
+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos (5U)
+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos (8U)
+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos (9U)
+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos (10U)
+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos (11U)
+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos (12U)
+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos (13U)
+#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define I2C_PECR_PEC_Pos (0U)
+#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA_Pos (0U)
+#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA_Pos (0U)
+#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos (2U)
+#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN_Pos (0U)
+#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM_Pos (0U)
+#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos (1U)
+#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos (2U)
+#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos (3U)
+#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos (4U)
+#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos (5U)
+#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos (6U)
+#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF_Pos (0U)
+#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos (1U)
+#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos (3U)
+#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos (4U)
+#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos (5U)
+#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos (6U)
+#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos (0U)
+#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos (1U)
+#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos (3U)
+#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos (4U)
+#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos (5U)
+#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos (6U)
+#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos (0U)
+#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos (1U)
+#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos (3U)
+#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos (6U)
+#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos (9U)
+#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos (17U)
+#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos (19U)
+#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos (20U)
+#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos (21U)
+#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos (22U)
+#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos (24U)
+#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE_Pos (0U)
+#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos (1U)
+#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos (2U)
+#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP_Pos (0U)
+#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR_Pos (0U)
+#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT_Pos (0U)
+#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
+
+/******************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPSDSR_Pos (0U)
+#define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP_Pos (9U)
+#define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /*!< 0x00000200 */
+#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
+#define PWR_CR_FWU_Pos (10U)
+#define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /*!< 0x00000400 */
+#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
+
+#define PWR_CR_VOS_Pos (11U)
+#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x00001800 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /*!< 0x00000800 */
+#define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /*!< 0x00001000 */
+#define PWR_CR_DSEEKOFF_Pos (13U)
+#define PWR_CR_DSEEKOFF_Msk (0x1UL << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */
+#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */
+#define PWR_CR_LPRUN_Pos (14U)
+#define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
+#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_VREFINTRDYF_Pos (3U)
+#define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
+#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF_Pos (4U)
+#define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
+#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF_Pos (5U)
+#define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
+#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1_Pos (8U)
+#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2_Pos (9U)
+#define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
+#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos (1U)
+#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos (2U)
+#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIVEN_Pos (3U)
+#define RCC_CR_HSIDIVEN_Msk (0x1UL << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */
+#define RCC_CR_HSIDIVF_Pos (4U)
+#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */
+#define RCC_CR_HSIOUTEN_Pos (5U)
+#define RCC_CR_HSIOUTEN_Msk (0x1UL << RCC_CR_HSIOUTEN_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_Msk /*!< Internal High Speed clock out enable */
+#define RCC_CR_MSION_Pos (8U)
+#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000100 */
+#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY_Pos (9U)
+#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
+#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON_Pos (19U)
+#define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */
+#define RCC_CR_RTCPRE_Pos (20U)
+#define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
+#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */
+#define RCC_CR_RTCPRE_0 (0x1UL << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */
+#define RCC_CR_RTCPRE_1 (0x2UL << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+/* Reference defines */
+#define RCC_CR_CSSON RCC_CR_CSSHSEON
+
+/******************** Bit definition for RCC_ICSCR register *****************/
+#define RCC_ICSCR_HSICAL_Pos (0U)
+#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
+#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM_Pos (8U)
+#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
+#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE_Pos (13U)
+#define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
+#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
+#define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
+#define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
+#define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
+#define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
+#define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
+#define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
+#define RCC_ICSCR_MSICAL_Pos (16U)
+#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
+#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM_Pos (24U)
+#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
+#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos (15U)
+#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */
+
+/*!< PLL entry clock source*/
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
+
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL_Pos (18U)
+#define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV_Pos (22U)
+#define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
+
+#define RCC_CFGR_PLLDIV2_Pos (22U)
+#define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3_Pos (23U)
+#define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4_Pos (22U)
+#define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCOSEL_Pos (24U)
+#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
+#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
+
+#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
+#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCOSEL_HSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_MSI_Pos (24U)
+#define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
+#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_HSE_Pos (26U)
+#define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCOSEL_PLL_Pos (24U)
+#define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
+#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
+#define RCC_CFGR_MCOSEL_LSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
+#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
+#define RCC_CFGR_MCOSEL_LSE_Pos (24U)
+#define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
+
+#define RCC_CFGR_MCOPRE_Pos (28U)
+#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
+
+#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
+
+/* Legacy defines */
+#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
+#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
+#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
+#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
+#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
+#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
+#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
+#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
+#ifdef RCC_CFGR_MCOSEL_HSI48
+#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48
+#endif
+
+#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
+#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
+
+/*!<****************** Bit definition for RCC_CIER register ********************/
+#define RCC_CIER_LSIRDYIE_Pos (0U)
+#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIER_LSERDYIE_Pos (1U)
+#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIER_HSIRDYIE_Pos (2U)
+#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIER_HSERDYIE_Pos (3U)
+#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIER_PLLRDYIE_Pos (4U)
+#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIER_MSIRDYIE_Pos (5U)
+#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
+#define RCC_CIER_CSSLSE_Pos (7U)
+#define RCC_CIER_CSSLSE_Msk (0x1UL << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */
+
+/* Reference defines */
+#define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
+
+/*!<****************** Bit definition for RCC_CIFR register ********************/
+#define RCC_CIFR_LSIRDYF_Pos (0U)
+#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIFR_LSERDYF_Pos (1U)
+#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIFR_HSIRDYF_Pos (2U)
+#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIFR_HSERDYF_Pos (3U)
+#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIFR_PLLRDYF_Pos (4U)
+#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIFR_MSIRDYF_Pos (5U)
+#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
+#define RCC_CIFR_CSSLSEF_Pos (7U)
+#define RCC_CIFR_CSSLSEF_Msk (0x1UL << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */
+#define RCC_CIFR_CSSHSEF_Pos (8U)
+#define RCC_CIFR_CSSHSEF_Msk (0x1UL << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */
+#define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */
+
+/* Reference defines */
+#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
+#define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
+
+/*!<****************** Bit definition for RCC_CICR register ********************/
+#define RCC_CICR_LSIRDYC_Pos (0U)
+#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CICR_LSERDYC_Pos (1U)
+#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CICR_HSIRDYC_Pos (2U)
+#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CICR_HSERDYC_Pos (3U)
+#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CICR_PLLRDYC_Pos (4U)
+#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CICR_MSIRDYC_Pos (5U)
+#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
+#define RCC_CICR_CSSLSEC_Pos (7U)
+#define RCC_CICR_CSSLSEC_Msk (0x1UL << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */
+#define RCC_CICR_CSSHSEC_Pos (8U)
+#define RCC_CICR_CSSHSEC_Msk (0x1UL << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */
+#define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */
+
+/* Reference defines */
+#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
+#define RCC_CICR_CSSC RCC_CICR_CSSHSEC
+/***************** Bit definition for RCC_IOPRSTR register ******************/
+#define RCC_IOPRSTR_IOPARST_Pos (0U)
+#define RCC_IOPRSTR_IOPARST_Msk (0x1UL << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */
+#define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */
+#define RCC_IOPRSTR_IOPBRST_Pos (1U)
+#define RCC_IOPRSTR_IOPBRST_Msk (0x1UL << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */
+#define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */
+#define RCC_IOPRSTR_IOPCRST_Pos (2U)
+#define RCC_IOPRSTR_IOPCRST_Msk (0x1UL << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */
+#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */
+#define RCC_IOPRSTR_IOPDRST_Pos (3U)
+#define RCC_IOPRSTR_IOPDRST_Msk (0x1UL << RCC_IOPRSTR_IOPDRST_Pos) /*!< 0x00000008 */
+#define RCC_IOPRSTR_IOPDRST RCC_IOPRSTR_IOPDRST_Msk /*!< GPIO port D reset */
+#define RCC_IOPRSTR_IOPHRST_Pos (7U)
+#define RCC_IOPRSTR_IOPHRST_Msk (0x1UL << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */
+#define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */
+
+/* Reference defines */
+#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
+#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
+#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
+#define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_IOPDRST /*!< GPIO port D reset */
+#define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
+
+
+/****************** Bit definition for RCC_AHBRST register ******************/
+#define RCC_AHBRSTR_DMARST_Pos (0U)
+#define RCC_AHBRSTR_DMARST_Msk (0x1UL << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */
+#define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */
+#define RCC_AHBRSTR_MIFRST_Pos (8U)
+#define RCC_AHBRSTR_MIFRST_Msk (0x1UL << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */
+#define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset */
+#define RCC_AHBRSTR_CRCRST_Pos (12U)
+#define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */
+
+/* Reference defines */
+#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
+#define RCC_APB2RSTR_TIM21RST_Pos (2U)
+#define RCC_APB2RSTR_TIM21RST_Msk (0x1UL << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 reset */
+#define RCC_APB2RSTR_ADCRST_Pos (9U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
+#define RCC_APB2RSTR_DBGRST_Pos (22U)
+#define RCC_APB2RSTR_DBGRST_Msk (0x1UL << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU reset */
+
+/* Reference defines */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 reset */
+#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU reset */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_LPUART1RST_Pos (18U)
+#define RCC_APB1RSTR_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
+#define RCC_APB1RSTR_LPTIM1RST_Pos (31U)
+#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 reset */
+
+/***************** Bit definition for RCC_IOPENR register ******************/
+#define RCC_IOPENR_IOPAEN_Pos (0U)
+#define RCC_IOPENR_IOPAEN_Msk (0x1UL << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */
+#define RCC_IOPENR_IOPBEN_Pos (1U)
+#define RCC_IOPENR_IOPBEN_Msk (0x1UL << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */
+#define RCC_IOPENR_IOPCEN_Pos (2U)
+#define RCC_IOPENR_IOPCEN_Msk (0x1UL << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */
+#define RCC_IOPENR_IOPDEN_Pos (3U)
+#define RCC_IOPENR_IOPDEN_Msk (0x1UL << RCC_IOPENR_IOPDEN_Pos) /*!< 0x00000008 */
+#define RCC_IOPENR_IOPDEN RCC_IOPENR_IOPDEN_Msk /*!< GPIO port D clock enable */
+#define RCC_IOPENR_IOPHEN_Pos (7U)
+#define RCC_IOPENR_IOPHEN_Msk (0x1UL << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */
+
+/* Reference defines */
+#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
+#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
+#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
+#define RCC_IOPENR_GPIODEN RCC_IOPENR_IOPDEN /*!< GPIO port D clock enable */
+#define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
+
+/***************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMAEN_Pos (0U)
+#define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_MIFEN_Pos (8U)
+#define RCC_AHBENR_MIFEN_Msk (0x1UL << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */
+#define RCC_AHBENR_CRCEN_Pos (12U)
+#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+
+/* Reference defines */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register ******************/
+#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM21EN_Pos (2U)
+#define RCC_APB2ENR_TIM21EN_Msk (0x1UL << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */
+#define RCC_APB2ENR_FWEN_Pos (7U)
+#define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADCEN_Pos (9U)
+#define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
+#define RCC_APB2ENR_DBGEN_Pos (22U)
+#define RCC_APB2ENR_DBGEN_Msk (0x1UL << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */
+
+/* Reference defines */
+
+#define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
+#define RCC_APB1ENR_LPUART1EN_Pos (18U)
+#define RCC_APB1ENR_LPUART1EN_Msk (0x1UL << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
+#define RCC_APB1ENR_LPTIM1EN_Pos (31U)
+#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */
+
+/****************** Bit definition for RCC_IOPSMENR register ****************/
+#define RCC_IOPSMENR_IOPASMEN_Pos (0U)
+#define RCC_IOPSMENR_IOPASMEN_Msk (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPBSMEN_Pos (1U)
+#define RCC_IOPSMENR_IOPBSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPCSMEN_Pos (2U)
+#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPDSMEN_Pos (3U)
+#define RCC_IOPSMENR_IOPDSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos) /*!< 0x00000008 */
+#define RCC_IOPSMENR_IOPDSMEN RCC_IOPSMENR_IOPDSMEN_Msk /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPHSMEN_Pos (7U)
+#define RCC_IOPSMENR_IOPHSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_IOPDSMEN /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_AHBSMENR register ******************/
+#define RCC_AHBSMENR_DMASMEN_Pos (0U)
+#define RCC_AHBSMENR_DMASMEN_Msk (0x1UL << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */
+#define RCC_AHBSMENR_MIFSMEN_Pos (8U)
+#define RCC_AHBSMENR_MIFSMEN_Msk (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */
+#define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
+#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRCSMEN_Pos (12U)
+#define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB2SMENR register ******************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM21SMEN_Pos (2U)
+#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */
+#define RCC_APB2SMENR_ADCSMEN_Pos (9U)
+#define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
+#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGSMEN_Pos (22U)
+#define RCC_APB2SMENR_DBGSMEN_Msk (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB1SMENR register ******************/
+#define RCC_APB1SMENR_TIM2SMEN_Pos (0U)
+#define RCC_APB1SMENR_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_WWDGSMEN_Pos (11U)
+#define RCC_APB1SMENR_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART2SMEN_Pos (17U)
+#define RCC_APB1SMENR_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPUART1SMEN_Pos (18U)
+#define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C1SMEN_Pos (21U)
+#define RCC_APB1SMENR_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_PWRSMEN_Pos (28U)
+#define RCC_APB1SMENR_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U)
+#define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */
+
+/*!< USART2 Clock source selection */
+#define RCC_CCIPR_USART2SEL_Pos (2U)
+#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */
+#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+/*!< LPUART1 Clock source selection */
+#define RCC_CCIPR_LPUART1SEL_Pos (10U)
+#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */
+#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */
+#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CCIPR_I2C1SEL_Pos (12U)
+#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */
+#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
+
+
+/*!< LPTIM1 Clock source selection */
+#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
+#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */
+#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+/******************* Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSEON_Pos (8U)
+#define RCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */
+#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_CSR_LSERDY_Pos (9U)
+#define RCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */
+#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP_Pos (10U)
+#define RCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */
+#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_CSR_LSEDRV_Pos (11U)
+#define RCC_CSR_LSEDRV_Msk (0x3UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */
+#define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_CSR_LSEDRV_0 (0x1UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */
+#define RCC_CSR_LSEDRV_1 (0x2UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */
+
+#define RCC_CSR_LSECSSON_Pos (13U)
+#define RCC_CSR_LSECSSON_Msk (0x1UL << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */
+#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */
+#define RCC_CSR_LSECSSD_Pos (14U)
+#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
+#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
+
+/*!< RTC congiguration */
+#define RCC_CSR_RTCSEL_Pos (16U)
+#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
+
+#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CSR_RTCSEL_LSE_Pos (16U)
+#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_LSI_Pos (17U)
+#define RCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */
+#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_HSE_Pos (16U)
+#define RCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */
+
+#define RCC_CSR_RTCEN_Pos (18U)
+#define RCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */
+#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_CSR_RTCRST_Pos (19U)
+#define RCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */
+#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */
+
+#define RCC_CSR_RMVF_Pos (23U)
+#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_OBLRSTF_Pos (25U)
+#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+/* Reference defines */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER1_SUPPORT
+#define RTC_TAMPER2_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk /*!< */
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk /*!< */
+#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk /*!< */
+#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */
+#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */
+#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk /*!< */
+#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk /*!< */
+#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk /*!< */
+#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk /*!< */
+#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */
+#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk /*!< */
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk /*!< */
+#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk /*!< */
+#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk /*!< */
+#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk /*!< */
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */
+#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk /*!< */
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< */
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */
+#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */
+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */
+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */
+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */
+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */
+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */
+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */
+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */
+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */
+#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */
+#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */
+#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */
+#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */
+#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */
+#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */
+#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */
+#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */
+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */
+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */
+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */
+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */
+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */
+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */
+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */
+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */
+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */
+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CALR register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */
+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define RTC_CAL_CALP RTC_CALR_CALP
+#define RTC_CAL_CALW8 RTC_CALR_CALW8
+#define RTC_CAL_CALW16 RTC_CALR_CALW16
+#define RTC_CAL_CALM RTC_CALR_CALM
+#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
+
+/******************** Bits definition for RTC_TAMPCR register ****************/
+#define RTC_TAMPCR_TAMP2MF_Pos (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2IE_Pos (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1MF_Pos (18U)
+#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
+#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1IE_Pos (16U)
+#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */
+#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */
+#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */
+#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos (7U)
+#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */
+#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP2E_Pos (3U)
+#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */
+#define RTC_TAMPCR_TAMPIE_Pos (2U)
+#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
+#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP1E_Pos (0U)
+#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_OR register ****************/
+#define RTC_OR_OUT_RMP_Pos (1U)
+#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */
+#define RTC_OR_ALARMOUTTYPE_Pos (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */
+
+/* Legacy defines */
+#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk /*!< */
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER (0x00000005U) /*!< */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/******************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
+#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR1_BOOT_MODE_Pos (8U)
+#define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
+#define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */
+#define SYSCFG_CFGR1_BOOT_MODE_0 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOT_MODE_1 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_FWDISEN_Pos (0U)
+#define SYSCFG_CFGR2_FWDISEN_Msk (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
+
+
+/***************** Bit definition for SYSCFG_CFGR3 register ****************/
+#define SYSCFG_CFGR3_EN_VREFINT_Pos (0U)
+#define SYSCFG_CFGR3_EN_VREFINT_Msk (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_EN_VREFINT SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
+#define SYSCFG_CFGR3_VREF_OUT_Pos (4U)
+#define SYSCFG_CFGR3_VREF_OUT_Msk (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
+#define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */
+#define SYSCFG_CFGR3_VREF_OUT_0 (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
+#define SYSCFG_CFGR3_VREF_OUT_1 (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U)
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U)
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U)
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
+#define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U)
+#define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
+#define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
+#define SYSCFG_CFGR3_REF_LOCK_Pos (31U)
+#define SYSCFG_CFGR3_REF_LOCK_Msk (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
+#define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */
+
+/* Legacy defines */
+
+#define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
+#define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
+#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
+#define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+
+/******************************************************************************/
+/* */
+/* Timers (TIM)*/
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
+#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
+ || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#else
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#endif
+
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFUL << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFUL << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM2_OR_ETR_RMP_Pos (0U)
+#define TIM2_OR_ETR_RMP_Msk (0x7UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000007 */
+#define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
+#define TIM2_OR_ETR_RMP_0 (0x1UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM2_OR_ETR_RMP_1 (0x2UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM2_OR_ETR_RMP_2 (0x4UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000004 */
+#define TIM2_OR_TI4_RMP_Pos (3U)
+#define TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000018 */
+#define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
+#define TIM2_OR_TI4_RMP_0 (0x1UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */
+#define TIM2_OR_TI4_RMP_1 (0x2UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000010 */
+
+#define TIM21_OR_ETR_RMP_Pos (0U)
+#define TIM21_OR_ETR_RMP_Msk (0x3UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
+#define TIM21_OR_ETR_RMP_0 (0x1UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM21_OR_ETR_RMP_1 (0x2UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM21_OR_TI1_RMP_Pos (2U)
+#define TIM21_OR_TI1_RMP_Msk (0x7UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x0000001C */
+#define TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
+#define TIM21_OR_TI1_RMP_0 (0x1UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM21_OR_TI1_RMP_1 (0x2UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+#define TIM21_OR_TI1_RMP_2 (0x4UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000010 */
+#define TIM21_OR_TI2_RMP_Pos (5U)
+#define TIM21_OR_TI2_RMP_Msk (0x1UL << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */
+#define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE_Pos (0U)
+#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+#define USART_CR1_UESM_Pos (1U)
+#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
+#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_M0_Pos (12U)
+#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
+#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos (13U)
+#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos (14U)
+#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos (16U)
+#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
+#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
+#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
+#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
+#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos (21U)
+#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
+#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
+#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
+#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
+#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos (26U)
+#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos (27U)
+#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos (28U)
+#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
+#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7_Pos (4U)
+#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos (15U)
+#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos (16U)
+#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos (17U)
+#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos (18U)
+#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos (19U)
+#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos (20U)
+#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos (21U)
+#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos (23U)
+#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos (24U)
+#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos (12U)
+#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos (13U)
+#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos (14U)
+#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos (15U)
+#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos (17U)
+#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos (20U)
+#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
+#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
+#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos (22U)
+#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
+#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
+#define USART_CR3_UCESM_Pos (23U)
+#define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
+#define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION_Pos (0U)
+#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos (4U)
+#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO_Pos (0U)
+#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos (24U)
+#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ_Pos (0U)
+#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
+#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos (1U)
+#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
+#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos (2U)
+#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
+#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos (3U)
+#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
+#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos (4U)
+#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
+#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE_Pos (0U)
+#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
+#define USART_ISR_FE_Pos (1U)
+#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
+#define USART_ISR_NE_Pos (2U)
+#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos (3U)
+#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos (4U)
+#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos (5U)
+#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos (6U)
+#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos (7U)
+#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
+#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos (8U)
+#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos (9U)
+#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos (10U)
+#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
+#define USART_ISR_RTOF_Pos (11U)
+#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos (12U)
+#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos (14U)
+#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos (15U)
+#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos (16U)
+#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
+#define USART_ISR_CMF_Pos (17U)
+#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos (18U)
+#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos (19U)
+#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos (20U)
+#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
+#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos (21U)
+#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos (22U)
+#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
+#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF_Pos (0U)
+#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos (1U)
+#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos (2U)
+#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */
+#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos (3U)
+#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos (4U)
+#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos (6U)
+#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF_Pos (8U)
+#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos (9U)
+#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos (11U)
+#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos (12U)
+#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos (17U)
+#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos (20U)
+#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
+#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
+
+/* Compatibility defines with other series */
+#define USART_ICR_NECF USART_ICR_NCF
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR_Pos (0U)
+#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR_Pos (0U)
+#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOH))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
+
+
+
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SMBUS Instances *****************************/
+#define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/************* LPTIM instances supporting the encoder mode feature ************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM21) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/******************* TIM Instances : output(s) OCXEC register *****************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/****************** USART Instances : Auto Baud Rate detection ****************/
+
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (1==0)
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32L0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32L0 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+
+#define RNG_LPUART1_IRQn LPUART1_IRQn
+#define AES_LPUART1_IRQn LPUART1_IRQn
+#define AES_RNG_LPUART1_IRQn LPUART1_IRQn
+#define RCC_CRS_IRQn RCC_IRQn
+#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
+#define ADC1_COMP_IRQn ADC1_IRQn
+
+/* Aliases for __IRQHandler */
+#define RNG_LPUART1_IRQHandler LPUART1_IRQHandler
+#define AES_LPUART1_IRQHandler LPUART1_IRQHandler
+#define AES_RNG_LPUART1_IRQHandler LPUART1_IRQHandler
+#define RCC_CRS_IRQHandler RCC_IRQHandler
+#define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
+#define ADC1_COMP_IRQHandler ADC1_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L010x8_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/CMSIS/device/stm32l010xb.h b/CMSIS/device/stm32l010xb.h
new file mode 100644
index 0000000..397e6ae
--- /dev/null
+++ b/CMSIS/device/stm32l010xb.h
@@ -0,0 +1,5932 @@
+/**
+ ******************************************************************************
+ * @file stm32l010xb.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for stm32l010xb devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright(c) 2018 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l010xb
+ * @{
+ */
+
+#ifndef __STM32L010xB_H
+#define __STM32L010xB_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 0U /*!< STM32L0xx provides no MPU */
+#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
+#define __NVIC_PRIO_BITS 2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief stm32l010xb Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+/*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
+
+/****** STM32L-0 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */
+ RCC_IRQn = 4, /*!< RCC Interrupt */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
+ ADC1_IRQn = 12, /*!< ADC1 Interrupt */
+ LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 Interrupt */
+ TIM21_IRQn = 20, /*!< TIM21 Interrupt */
+ TIM22_IRQn = 22, /*!< TIM22 Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ USART2_IRQn = 28, /*!< USART2 Interrupt */
+ LPUART1_IRQn = 29, /*!< LPUART1 Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0plus.h"
+#include "system_stm32l0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+ uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+} ADC_Common_TypeDef;
+
+
+
+/**
+* @brief CRC calculation unit
+*/
+
+typedef struct
+{
+__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+uint8_t RESERVED0; /*!< Reserved, 0x05 */
+uint16_t RESERVED1; /*!< Reserved, 0x06 */
+__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+uint32_t RESERVED2; /*!< Reserved, 0x0C */
+__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
+} DMA_Request_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
+ __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
+ __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
+ __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
+ __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
+ __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
+ __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
+ __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
+ __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
+ __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
+} OB_TypeDef;
+
+
+/**
+ * @brief General Purpose IO
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief LPTIMIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+} LPTIM_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+ * @brief Independent WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
+ __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
+ __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
+ __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
+ __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
+ __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
+ __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
+ __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
+ __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
+ __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
+ __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */
+
+#define DATA_EEPROM_BASE (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
+#define DATA_EEPROM_END (0x080801FFUL) /*!< DATA EEPROM end address in the alias region */
+#define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */
+#define SRAM_SIZE_MAX (0x00005000UL) /*!< maximum SRAM size (up to 20KBytes) */
+
+#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000UL)
+
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
+#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800UL)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
+#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL)
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL)
+#define TIM21_BASE (APBPERIPH_BASE + 0x00010800UL)
+#define TIM22_BASE (APBPERIPH_BASE + 0x00011400UL)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708UL)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
+#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL)
+
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
+#define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */
+#define FLASHSIZE_BASE (0x1FF8007CUL) /*!< FLASH Size register base address */
+#define UID_BASE (0x1FF80050UL) /*!< Unique device ID register base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
+
+#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL)
+#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL)
+#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL)
+#define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00UL)
+#define GPIOE_BASE (IOPPERIPH_BASE + 0x00001000UL)
+#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00UL)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
+#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
+/* Legacy defines */
+#define ADC ADC1_COMMON
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_EOCAL_Pos (11U)
+#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
+#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
+#define ADC_ISR_AWD_Pos (7U)
+#define ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
+#define ADC_ISR_EOSEQ_Pos (3U)
+#define ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_EOCALIE_Pos (11U)
+#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
+#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
+#define ADC_IER_AWDIE_Pos (7U)
+#define ADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE_Pos (3U)
+#define ADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH_Pos (26U)
+#define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
+#define ADC_CFGR1_AWDEN_Pos (23U)
+#define ADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL_Pos (22U)
+#define ADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN_Pos (16U)
+#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF_Pos (15U)
+#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
+#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT_Pos (14U)
+#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
+#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT_Pos (13U)
+#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD_Pos (12U)
+#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN_Pos (10U)
+#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
+#define ADC_CFGR1_EXTSEL_Pos (6U)
+#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
+#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
+#define ADC_CFGR1_ALIGN_Pos (5U)
+#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
+#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
+#define ADC_CFGR1_RES_Pos (3U)
+#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
+#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
+#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
+#define ADC_CFGR1_SCANDIR_Pos (2U)
+#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG_Pos (1U)
+#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
+#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN_Pos (0U)
+#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
+#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_TOVS_Pos (9U)
+#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
+#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+#define ADC_CFGR2_OVSR_Pos (2U)
+#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
+#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+#define ADC_CFGR2_OVSE_Pos (0U)
+#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
+#define ADC_CFGR2_CKMODE_Pos (30U)
+#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
+#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
+#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
+#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
+
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP_Pos (0U)
+#define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
+#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
+#define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
+#define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define ADC_SMPR_SMPR ADC_SMPR_SMP
+#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
+#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
+#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT_Pos (16U)
+#define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
+#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
+#define ADC_TR_LT_Pos (0U)
+#define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL_Pos (0U)
+#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
+#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
+#define ADC_CHSELR_CHSEL18_Pos (18U)
+#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17_Pos (17U)
+#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
+#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL15_Pos (15U)
+#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
+#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14_Pos (14U)
+#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
+#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13_Pos (13U)
+#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
+#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12_Pos (12U)
+#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
+#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11_Pos (11U)
+#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
+#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10_Pos (10U)
+#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
+#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9_Pos (9U)
+#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
+#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8_Pos (8U)
+#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
+#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7_Pos (7U)
+#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
+#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6_Pos (6U)
+#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
+#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5_Pos (5U)
+#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
+#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4_Pos (4U)
+#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
+#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3_Pos (3U)
+#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
+#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2_Pos (2U)
+#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
+#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1_Pos (1U)
+#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
+#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0_Pos (0U)
+#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
+#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_CALFACT_Pos (0U)
+#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_LFMEN_Pos (25U)
+#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
+#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR (0xFFU) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos (3U)
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos (5U)
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos (7U)
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT_Pos (0U)
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL_Pos (0U)
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_Pos (0U)
+#define DBGMCU_CR_DBG_Msk (0x7UL << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
+#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+
+/******************* Bit definition for DMA_CSELR register *******************/
+#define DMA_CSELR_C1S_Pos (0U)
+#define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
+#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos (4U)
+#define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
+#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos (8U)
+#define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
+#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos (12U)
+#define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
+#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos (16U)
+#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
+#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S_Pos (20U)
+#define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
+#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S_Pos (24U)
+#define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
+#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_IM0_Pos (0U)
+#define EXTI_IMR_IM0_Msk (0x1UL << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_IM1_Pos (1U)
+#define EXTI_IMR_IM1_Msk (0x1UL << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_IM2_Pos (2U)
+#define EXTI_IMR_IM2_Msk (0x1UL << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_IM3_Pos (3U)
+#define EXTI_IMR_IM3_Msk (0x1UL << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_IM4_Pos (4U)
+#define EXTI_IMR_IM4_Msk (0x1UL << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_IM5_Pos (5U)
+#define EXTI_IMR_IM5_Msk (0x1UL << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_IM6_Pos (6U)
+#define EXTI_IMR_IM6_Msk (0x1UL << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_IM7_Pos (7U)
+#define EXTI_IMR_IM7_Msk (0x1UL << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_IM8_Pos (8U)
+#define EXTI_IMR_IM8_Msk (0x1UL << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_IM9_Pos (9U)
+#define EXTI_IMR_IM9_Msk (0x1UL << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_IM10_Pos (10U)
+#define EXTI_IMR_IM10_Msk (0x1UL << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_IM11_Pos (11U)
+#define EXTI_IMR_IM11_Msk (0x1UL << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_IM12_Pos (12U)
+#define EXTI_IMR_IM12_Msk (0x1UL << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_IM13_Pos (13U)
+#define EXTI_IMR_IM13_Msk (0x1UL << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_IM14_Pos (14U)
+#define EXTI_IMR_IM14_Msk (0x1UL << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_IM15_Pos (15U)
+#define EXTI_IMR_IM15_Msk (0x1UL << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_IM17_Pos (17U)
+#define EXTI_IMR_IM17_Msk (0x1UL << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_IM19_Pos (19U)
+#define EXTI_IMR_IM19_Msk (0x1UL << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_IM20_Pos (20U)
+#define EXTI_IMR_IM20_Msk (0x1UL << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_IM23_Pos (23U)
+#define EXTI_IMR_IM23_Msk (0x1UL << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
+#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_IM26_Pos (26U)
+#define EXTI_IMR_IM26_Msk (0x1UL << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
+#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_IM28_Pos (28U)
+#define EXTI_IMR_IM28_Msk (0x1UL << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
+#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_IM29_Pos (29U)
+#define EXTI_IMR_IM29_Msk (0x1UL << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
+#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
+
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x36FFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x36FFFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_EM0_Pos (0U)
+#define EXTI_EMR_EM0_Msk (0x1UL << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_EM1_Pos (1U)
+#define EXTI_EMR_EM1_Msk (0x1UL << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_EM2_Pos (2U)
+#define EXTI_EMR_EM2_Msk (0x1UL << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_EM3_Pos (3U)
+#define EXTI_EMR_EM3_Msk (0x1UL << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_EM4_Pos (4U)
+#define EXTI_EMR_EM4_Msk (0x1UL << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_EM5_Pos (5U)
+#define EXTI_EMR_EM5_Msk (0x1UL << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_EM6_Pos (6U)
+#define EXTI_EMR_EM6_Msk (0x1UL << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_EM7_Pos (7U)
+#define EXTI_EMR_EM7_Msk (0x1UL << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_EM8_Pos (8U)
+#define EXTI_EMR_EM8_Msk (0x1UL << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_EM9_Pos (9U)
+#define EXTI_EMR_EM9_Msk (0x1UL << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_EM10_Pos (10U)
+#define EXTI_EMR_EM10_Msk (0x1UL << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_EM11_Pos (11U)
+#define EXTI_EMR_EM11_Msk (0x1UL << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_EM12_Pos (12U)
+#define EXTI_EMR_EM12_Msk (0x1UL << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_EM13_Pos (13U)
+#define EXTI_EMR_EM13_Msk (0x1UL << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_EM14_Pos (14U)
+#define EXTI_EMR_EM14_Msk (0x1UL << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_EM15_Pos (15U)
+#define EXTI_EMR_EM15_Msk (0x1UL << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_EM17_Pos (17U)
+#define EXTI_EMR_EM17_Msk (0x1UL << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_EM19_Pos (19U)
+#define EXTI_EMR_EM19_Msk (0x1UL << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_EM20_Pos (20U)
+#define EXTI_EMR_EM20_Msk (0x1UL << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_EM23_Pos (23U)
+#define EXTI_EMR_EM23_Msk (0x1UL << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
+#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
+#define EXTI_EMR_EM26_Pos (26U)
+#define EXTI_EMR_EM26_Msk (0x1UL << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
+#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
+#define EXTI_EMR_EM28_Pos (28U)
+#define EXTI_EMR_EM28_Msk (0x1UL << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
+#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
+#define EXTI_EMR_EM29_Pos (29U)
+#define EXTI_EMR_EM29_Msk (0x1UL << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
+#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_RT0_Pos (0U)
+#define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_RT1_Pos (1U)
+#define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_RT2_Pos (2U)
+#define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_RT3_Pos (3U)
+#define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_RT4_Pos (4U)
+#define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_RT5_Pos (5U)
+#define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_RT6_Pos (6U)
+#define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_RT7_Pos (7U)
+#define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_RT8_Pos (8U)
+#define EXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_RT9_Pos (9U)
+#define EXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_RT10_Pos (10U)
+#define EXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_RT11_Pos (11U)
+#define EXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_RT12_Pos (12U)
+#define EXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_RT13_Pos (13U)
+#define EXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_RT14_Pos (14U)
+#define EXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_RT15_Pos (15U)
+#define EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_RT16_Pos (16U)
+#define EXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_RT17_Pos (17U)
+#define EXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_RT19_Pos (19U)
+#define EXTI_RTSR_RT19_Msk (0x1UL << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_RT20_Pos (20U)
+#define EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_RT21_Pos (21U)
+#define EXTI_RTSR_RT21_Msk (0x1UL << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_RT22_Pos (22U)
+#define EXTI_RTSR_RT22_Msk (0x1UL << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
+#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
+#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
+#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
+#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
+#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
+#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
+#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
+#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
+#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
+#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
+#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
+#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
+#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
+#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
+#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
+#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
+#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
+#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
+#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
+#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
+#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_FT0_Pos (0U)
+#define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_FT1_Pos (1U)
+#define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_FT2_Pos (2U)
+#define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_FT3_Pos (3U)
+#define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_FT4_Pos (4U)
+#define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_FT5_Pos (5U)
+#define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_FT6_Pos (6U)
+#define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_FT7_Pos (7U)
+#define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_FT8_Pos (8U)
+#define EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_FT9_Pos (9U)
+#define EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_FT10_Pos (10U)
+#define EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_FT11_Pos (11U)
+#define EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_FT12_Pos (12U)
+#define EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_FT13_Pos (13U)
+#define EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_FT14_Pos (14U)
+#define EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_FT15_Pos (15U)
+#define EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_FT16_Pos (16U)
+#define EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_FT17_Pos (17U)
+#define EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_FT19_Pos (19U)
+#define EXTI_FTSR_FT19_Msk (0x1UL << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_FT20_Pos (20U)
+#define EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_FT21_Pos (21U)
+#define EXTI_FTSR_FT21_Msk (0x1UL << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_FT22_Pos (22U)
+#define EXTI_FTSR_FT22_Msk (0x1UL << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
+#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
+#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
+#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
+#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
+#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
+#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
+#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
+#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
+#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
+#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
+#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
+#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
+#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
+#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
+#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
+#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
+#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
+#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
+#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
+#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
+#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWI0_Pos (0U)
+#define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWI1_Pos (1U)
+#define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWI2_Pos (2U)
+#define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWI3_Pos (3U)
+#define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWI4_Pos (4U)
+#define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWI5_Pos (5U)
+#define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWI6_Pos (6U)
+#define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWI7_Pos (7U)
+#define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWI8_Pos (8U)
+#define EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWI9_Pos (9U)
+#define EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWI10_Pos (10U)
+#define EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWI11_Pos (11U)
+#define EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWI12_Pos (12U)
+#define EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWI13_Pos (13U)
+#define EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWI14_Pos (14U)
+#define EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWI15_Pos (15U)
+#define EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWI16_Pos (16U)
+#define EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWI17_Pos (17U)
+#define EXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWI19_Pos (19U)
+#define EXTI_SWIER_SWI19_Msk (0x1UL << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWI20_Pos (20U)
+#define EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWI21_Pos (21U)
+#define EXTI_SWIER_SWI21_Msk (0x1UL << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWI22_Pos (22U)
+#define EXTI_SWIER_SWI22_Msk (0x1UL << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
+
+/* Legacy defines */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PIF0_Pos (0U)
+#define EXTI_PR_PIF0_Msk (0x1UL << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
+#define EXTI_PR_PIF1_Pos (1U)
+#define EXTI_PR_PIF1_Msk (0x1UL << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
+#define EXTI_PR_PIF2_Pos (2U)
+#define EXTI_PR_PIF2_Msk (0x1UL << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
+#define EXTI_PR_PIF3_Pos (3U)
+#define EXTI_PR_PIF3_Msk (0x1UL << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
+#define EXTI_PR_PIF4_Pos (4U)
+#define EXTI_PR_PIF4_Msk (0x1UL << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
+#define EXTI_PR_PIF5_Pos (5U)
+#define EXTI_PR_PIF5_Msk (0x1UL << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
+#define EXTI_PR_PIF6_Pos (6U)
+#define EXTI_PR_PIF6_Msk (0x1UL << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
+#define EXTI_PR_PIF7_Pos (7U)
+#define EXTI_PR_PIF7_Msk (0x1UL << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
+#define EXTI_PR_PIF8_Pos (8U)
+#define EXTI_PR_PIF8_Msk (0x1UL << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
+#define EXTI_PR_PIF9_Pos (9U)
+#define EXTI_PR_PIF9_Msk (0x1UL << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
+#define EXTI_PR_PIF10_Pos (10U)
+#define EXTI_PR_PIF10_Msk (0x1UL << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
+#define EXTI_PR_PIF11_Pos (11U)
+#define EXTI_PR_PIF11_Msk (0x1UL << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
+#define EXTI_PR_PIF12_Pos (12U)
+#define EXTI_PR_PIF12_Msk (0x1UL << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
+#define EXTI_PR_PIF13_Pos (13U)
+#define EXTI_PR_PIF13_Msk (0x1UL << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
+#define EXTI_PR_PIF14_Pos (14U)
+#define EXTI_PR_PIF14_Msk (0x1UL << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
+#define EXTI_PR_PIF15_Pos (15U)
+#define EXTI_PR_PIF15_Msk (0x1UL << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
+#define EXTI_PR_PIF16_Pos (16U)
+#define EXTI_PR_PIF16_Msk (0x1UL << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
+#define EXTI_PR_PIF17_Pos (17U)
+#define EXTI_PR_PIF17_Msk (0x1UL << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
+#define EXTI_PR_PIF19_Pos (19U)
+#define EXTI_PR_PIF19_Msk (0x1UL << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
+#define EXTI_PR_PIF20_Pos (20U)
+#define EXTI_PR_PIF20_Msk (0x1UL << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
+#define EXTI_PR_PIF21_Pos (21U)
+#define EXTI_PR_PIF21_Msk (0x1UL << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
+#define EXTI_PR_PIF22_Pos (22U)
+#define EXTI_PR_PIF22_Msk (0x1UL << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
+
+/* Legacy defines */
+#define EXTI_PR_PR0 EXTI_PR_PIF0
+#define EXTI_PR_PR1 EXTI_PR_PIF1
+#define EXTI_PR_PR2 EXTI_PR_PIF2
+#define EXTI_PR_PR3 EXTI_PR_PIF3
+#define EXTI_PR_PR4 EXTI_PR_PIF4
+#define EXTI_PR_PR5 EXTI_PR_PIF5
+#define EXTI_PR_PR6 EXTI_PR_PIF6
+#define EXTI_PR_PR7 EXTI_PR_PIF7
+#define EXTI_PR_PR8 EXTI_PR_PIF8
+#define EXTI_PR_PR9 EXTI_PR_PIF9
+#define EXTI_PR_PR10 EXTI_PR_PIF10
+#define EXTI_PR_PR11 EXTI_PR_PIF11
+#define EXTI_PR_PR12 EXTI_PR_PIF12
+#define EXTI_PR_PR13 EXTI_PR_PIF13
+#define EXTI_PR_PR14 EXTI_PR_PIF14
+#define EXTI_PR_PR15 EXTI_PR_PIF15
+#define EXTI_PR_PR16 EXTI_PR_PIF16
+#define EXTI_PR_PR17 EXTI_PR_PIF17
+#define EXTI_PR_PR19 EXTI_PR_PIF19
+#define EXTI_PR_PR20 EXTI_PR_PIF20
+#define EXTI_PR_PR21 EXTI_PR_PIF21
+#define EXTI_PR_PR22 EXTI_PR_PIF22
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
+#define FLASH_ACR_PRFTEN_Pos (1U)
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_SLEEP_PD_Pos (3U)
+#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD_Pos (4U)
+#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
+#define FLASH_ACR_DISAB_BUF_Pos (5U)
+#define FLASH_ACR_DISAB_BUF_Msk (0x1UL << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
+#define FLASH_ACR_PRE_READ_Pos (6U)
+#define FLASH_ACR_PRE_READ_Msk (0x1UL << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
+#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
+
+/******************* Bit definition for FLASH_PECR register ******************/
+#define FLASH_PECR_PELOCK_Pos (0U)
+#define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
+#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK_Pos (1U)
+#define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
+#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK_Pos (2U)
+#define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
+#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG_Pos (3U)
+#define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
+#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
+#define FLASH_PECR_DATA_Pos (4U)
+#define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
+#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
+#define FLASH_PECR_FIX_Pos (8U)
+#define FLASH_PECR_FIX_Msk (0x1UL << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
+#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE_Pos (9U)
+#define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
+#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
+#define FLASH_PECR_FPRG_Pos (10U)
+#define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
+#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_EOPIE_Pos (16U)
+#define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
+#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
+#define FLASH_PECR_ERRIE_Pos (17U)
+#define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
+#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
+#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
+#define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
+#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
+#define FLASH_PECR_HALF_ARRAY_Pos (19U)
+#define FLASH_PECR_HALF_ARRAY_Msk (0x1UL << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
+#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
+
+/****************** Bit definition for FLASH_PDKEYR register ******************/
+#define FLASH_PDKEYR_PDKEYR_Pos (0U)
+#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PEKEYR register ******************/
+#define FLASH_PEKEYR_PEKEYR_Pos (0U)
+#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PRGKEYR register ******************/
+#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
+#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
+
+/****************** Bit definition for FLASH_OPTKEYR register ******************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_EOP_Pos (1U)
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
+#define FLASH_SR_HVOFF_Pos (2U)
+#define FLASH_SR_HVOFF_Msk (0x1UL << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
+#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
+#define FLASH_SR_READY_Pos (3U)
+#define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */
+#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR_Pos (8U)
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
+#define FLASH_SR_PGAERR_Pos (9U)
+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR_Pos (10U)
+#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
+#define FLASH_SR_OPTVERR_Pos (11U)
+#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
+#define FLASH_SR_RDERR_Pos (13U)
+#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
+#define FLASH_SR_NOTZEROERR_Pos (16U)
+#define FLASH_SR_NOTZEROERR_Msk (0x1UL << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
+#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
+#define FLASH_SR_FWWERR_Pos (17U)
+#define FLASH_SR_FWWERR_Msk (0x1UL << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
+#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
+
+/* Legacy defines */
+#define FLASH_SR_FWWER FLASH_SR_FWWERR
+#define FLASH_SR_ENHV FLASH_SR_HVOFF
+#define FLASH_SR_ENDHV FLASH_SR_HVOFF
+
+/****************** Bit definition for FLASH_OPTR register *******************/
+#define FLASH_OPTR_RDPROT_Pos (0U)
+#define FLASH_OPTR_RDPROT_Msk (0xFFUL << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
+#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
+#define FLASH_OPTR_WPRMOD_Pos (8U)
+#define FLASH_OPTR_WPRMOD_Msk (0x1UL << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
+#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
+#define FLASH_OPTR_BOR_LEV_Pos (16U)
+#define FLASH_OPTR_BOR_LEV_Msk (0xFUL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
+#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OPTR_IWDG_SW_Pos (20U)
+#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
+#define FLASH_OPTR_nRST_STOP_Pos (21U)
+#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OPTR_nRST_STDBY_Pos (22U)
+#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OPTR_USER_Pos (20U)
+#define FLASH_OPTR_USER_Msk (0x7UL << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
+#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OPTR_BOOT1_Pos (31U)
+#define FLASH_OPTR_BOOT1_Msk (0x1UL << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
+#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 (0x00000001U)
+#define GPIO_OTYPER_OT_1 (0x00000002U)
+#define GPIO_OTYPER_OT_2 (0x00000004U)
+#define GPIO_OTYPER_OT_3 (0x00000008U)
+#define GPIO_OTYPER_OT_4 (0x00000010U)
+#define GPIO_OTYPER_OT_5 (0x00000020U)
+#define GPIO_OTYPER_OT_6 (0x00000040U)
+#define GPIO_OTYPER_OT_7 (0x00000080U)
+#define GPIO_OTYPER_OT_8 (0x00000100U)
+#define GPIO_OTYPER_OT_9 (0x00000200U)
+#define GPIO_OTYPER_OT_10 (0x00000400U)
+#define GPIO_OTYPER_OT_11 (0x00000800U)
+#define GPIO_OTYPER_OT_12 (0x00001000U)
+#define GPIO_OTYPER_OT_13 (0x00002000U)
+#define GPIO_OTYPER_OT_14 (0x00004000U)
+#define GPIO_OTYPER_OT_15 (0x00008000U)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDER_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
+#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDER_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
+#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDER_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
+#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDER_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
+#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDER_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
+#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDER_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
+#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDER_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
+#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDER_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
+#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDER_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
+#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDER_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
+#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDER_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
+#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDER_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
+#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDER_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
+#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDER_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
+#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDER_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
+#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDER_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
+#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 (0x00000001U)
+#define GPIO_BSRR_BS_1 (0x00000002U)
+#define GPIO_BSRR_BS_2 (0x00000004U)
+#define GPIO_BSRR_BS_3 (0x00000008U)
+#define GPIO_BSRR_BS_4 (0x00000010U)
+#define GPIO_BSRR_BS_5 (0x00000020U)
+#define GPIO_BSRR_BS_6 (0x00000040U)
+#define GPIO_BSRR_BS_7 (0x00000080U)
+#define GPIO_BSRR_BS_8 (0x00000100U)
+#define GPIO_BSRR_BS_9 (0x00000200U)
+#define GPIO_BSRR_BS_10 (0x00000400U)
+#define GPIO_BSRR_BS_11 (0x00000800U)
+#define GPIO_BSRR_BS_12 (0x00001000U)
+#define GPIO_BSRR_BS_13 (0x00002000U)
+#define GPIO_BSRR_BS_14 (0x00004000U)
+#define GPIO_BSRR_BS_15 (0x00008000U)
+#define GPIO_BSRR_BR_0 (0x00010000U)
+#define GPIO_BSRR_BR_1 (0x00020000U)
+#define GPIO_BSRR_BR_2 (0x00040000U)
+#define GPIO_BSRR_BR_3 (0x00080000U)
+#define GPIO_BSRR_BR_4 (0x00100000U)
+#define GPIO_BSRR_BR_5 (0x00200000U)
+#define GPIO_BSRR_BR_6 (0x00400000U)
+#define GPIO_BSRR_BR_7 (0x00800000U)
+#define GPIO_BSRR_BR_8 (0x01000000U)
+#define GPIO_BSRR_BR_9 (0x02000000U)
+#define GPIO_BSRR_BR_10 (0x04000000U)
+#define GPIO_BSRR_BR_11 (0x08000000U)
+#define GPIO_BSRR_BR_12 (0x10000000U)
+#define GPIO_BSRR_BR_13 (0x20000000U)
+#define GPIO_BSRR_BR_14 (0x40000000U)
+#define GPIO_BSRR_BR_15 (0x80000000U)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 (0x00000001U)
+#define GPIO_BRR_BR_1 (0x00000002U)
+#define GPIO_BRR_BR_2 (0x00000004U)
+#define GPIO_BRR_BR_3 (0x00000008U)
+#define GPIO_BRR_BR_4 (0x00000010U)
+#define GPIO_BRR_BR_5 (0x00000020U)
+#define GPIO_BRR_BR_6 (0x00000040U)
+#define GPIO_BRR_BR_7 (0x00000080U)
+#define GPIO_BRR_BR_8 (0x00000100U)
+#define GPIO_BRR_BR_9 (0x00000200U)
+#define GPIO_BRR_BR_10 (0x00000400U)
+#define GPIO_BRR_BR_11 (0x00000800U)
+#define GPIO_BRR_BR_12 (0x00001000U)
+#define GPIO_BRR_BR_13 (0x00002000U)
+#define GPIO_BRR_BR_14 (0x00004000U)
+#define GPIO_BRR_BR_15 (0x00008000U)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos (1U)
+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos (2U)
+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos (3U)
+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos (4U)
+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos (5U)
+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos (6U)
+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos (7U)
+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos (8U)
+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos (12U)
+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos (14U)
+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos (15U)
+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos (16U)
+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos (17U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos (18U)
+#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos (19U)
+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos (20U)
+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos (21U)
+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos (22U)
+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos (23U)
+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD_Pos (0U)
+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos (10U)
+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos (11U)
+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos (12U)
+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos (13U)
+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
+#define I2C_CR2_STOP_Pos (14U)
+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos (15U)
+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos (16U)
+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos (24U)
+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos (25U)
+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos (26U)
+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1_Pos (0U)
+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos (10U)
+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos (15U)
+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2_Pos (1U)
+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos (8U)
+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos (8U)
+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos (9U)
+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos (8U)
+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos (10U)
+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos (8U)
+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos (9U)
+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos (8U)
+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos (15U)
+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos (0U)
+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos (8U)
+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos (16U)
+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos (20U)
+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos (28U)
+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE_Pos (0U)
+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos (1U)
+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos (2U)
+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos (3U)
+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos (4U)
+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos (5U)
+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos (6U)
+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos (7U)
+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos (8U)
+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
+#define I2C_ISR_ARLO_Pos (9U)
+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos (10U)
+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos (11U)
+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos (12U)
+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos (13U)
+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos (15U)
+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
+#define I2C_ISR_DIR_Pos (16U)
+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos (17U)
+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF_Pos (3U)
+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos (4U)
+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos (5U)
+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos (8U)
+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos (9U)
+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos (10U)
+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos (11U)
+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos (12U)
+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos (13U)
+#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define I2C_PECR_PEC_Pos (0U)
+#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA_Pos (0U)
+#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA_Pos (0U)
+#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos (2U)
+#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN_Pos (0U)
+#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM_Pos (0U)
+#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos (1U)
+#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos (2U)
+#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos (3U)
+#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos (4U)
+#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos (5U)
+#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos (6U)
+#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF_Pos (0U)
+#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos (1U)
+#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos (3U)
+#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos (4U)
+#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos (5U)
+#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos (6U)
+#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos (0U)
+#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos (1U)
+#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos (3U)
+#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos (4U)
+#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos (5U)
+#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos (6U)
+#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos (0U)
+#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos (1U)
+#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos (3U)
+#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos (6U)
+#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos (9U)
+#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos (17U)
+#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos (19U)
+#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos (20U)
+#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos (21U)
+#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos (22U)
+#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos (24U)
+#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE_Pos (0U)
+#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos (1U)
+#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos (2U)
+#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP_Pos (0U)
+#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR_Pos (0U)
+#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT_Pos (0U)
+#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
+
+/******************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPSDSR_Pos (0U)
+#define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP_Pos (9U)
+#define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /*!< 0x00000200 */
+#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
+#define PWR_CR_FWU_Pos (10U)
+#define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /*!< 0x00000400 */
+#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
+
+#define PWR_CR_VOS_Pos (11U)
+#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x00001800 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /*!< 0x00000800 */
+#define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /*!< 0x00001000 */
+#define PWR_CR_DSEEKOFF_Pos (13U)
+#define PWR_CR_DSEEKOFF_Msk (0x1UL << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */
+#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */
+#define PWR_CR_LPRUN_Pos (14U)
+#define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
+#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_VREFINTRDYF_Pos (3U)
+#define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
+#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF_Pos (4U)
+#define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
+#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF_Pos (5U)
+#define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
+#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1_Pos (8U)
+#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2_Pos (9U)
+#define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
+#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos (1U)
+#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos (2U)
+#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIVEN_Pos (3U)
+#define RCC_CR_HSIDIVEN_Msk (0x1UL << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */
+#define RCC_CR_HSIDIVF_Pos (4U)
+#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */
+#define RCC_CR_HSIOUTEN_Pos (5U)
+#define RCC_CR_HSIOUTEN_Msk (0x1UL << RCC_CR_HSIOUTEN_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_Msk /*!< Internal High Speed clock out enable */
+#define RCC_CR_MSION_Pos (8U)
+#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000100 */
+#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY_Pos (9U)
+#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
+#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON_Pos (19U)
+#define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */
+#define RCC_CR_RTCPRE_Pos (20U)
+#define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
+#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */
+#define RCC_CR_RTCPRE_0 (0x1UL << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */
+#define RCC_CR_RTCPRE_1 (0x2UL << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+/* Reference defines */
+#define RCC_CR_CSSON RCC_CR_CSSHSEON
+
+/******************** Bit definition for RCC_ICSCR register *****************/
+#define RCC_ICSCR_HSICAL_Pos (0U)
+#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
+#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM_Pos (8U)
+#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
+#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE_Pos (13U)
+#define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
+#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
+#define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
+#define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
+#define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
+#define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
+#define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
+#define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
+#define RCC_ICSCR_MSICAL_Pos (16U)
+#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
+#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM_Pos (24U)
+#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
+#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos (15U)
+#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */
+
+/*!< PLL entry clock source*/
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
+
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL_Pos (18U)
+#define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV_Pos (22U)
+#define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
+
+#define RCC_CFGR_PLLDIV2_Pos (22U)
+#define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3_Pos (23U)
+#define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4_Pos (22U)
+#define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCOSEL_Pos (24U)
+#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
+#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
+
+#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
+#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCOSEL_HSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_MSI_Pos (24U)
+#define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
+#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_HSE_Pos (26U)
+#define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCOSEL_PLL_Pos (24U)
+#define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
+#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
+#define RCC_CFGR_MCOSEL_LSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
+#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
+#define RCC_CFGR_MCOSEL_LSE_Pos (24U)
+#define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
+
+#define RCC_CFGR_MCOPRE_Pos (28U)
+#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
+
+#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
+
+/* Legacy defines */
+#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
+#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
+#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
+#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
+#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
+#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
+#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
+#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
+#ifdef RCC_CFGR_MCOSEL_HSI48
+#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48
+#endif
+
+#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
+#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
+
+/*!<****************** Bit definition for RCC_CIER register ********************/
+#define RCC_CIER_LSIRDYIE_Pos (0U)
+#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIER_LSERDYIE_Pos (1U)
+#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIER_HSIRDYIE_Pos (2U)
+#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIER_HSERDYIE_Pos (3U)
+#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIER_PLLRDYIE_Pos (4U)
+#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIER_MSIRDYIE_Pos (5U)
+#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
+#define RCC_CIER_CSSLSE_Pos (7U)
+#define RCC_CIER_CSSLSE_Msk (0x1UL << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */
+
+/* Reference defines */
+#define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
+
+/*!<****************** Bit definition for RCC_CIFR register ********************/
+#define RCC_CIFR_LSIRDYF_Pos (0U)
+#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIFR_LSERDYF_Pos (1U)
+#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIFR_HSIRDYF_Pos (2U)
+#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIFR_HSERDYF_Pos (3U)
+#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIFR_PLLRDYF_Pos (4U)
+#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIFR_MSIRDYF_Pos (5U)
+#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
+#define RCC_CIFR_CSSLSEF_Pos (7U)
+#define RCC_CIFR_CSSLSEF_Msk (0x1UL << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */
+#define RCC_CIFR_CSSHSEF_Pos (8U)
+#define RCC_CIFR_CSSHSEF_Msk (0x1UL << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */
+#define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */
+
+/* Reference defines */
+#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
+#define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
+
+/*!<****************** Bit definition for RCC_CICR register ********************/
+#define RCC_CICR_LSIRDYC_Pos (0U)
+#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CICR_LSERDYC_Pos (1U)
+#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CICR_HSIRDYC_Pos (2U)
+#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CICR_HSERDYC_Pos (3U)
+#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CICR_PLLRDYC_Pos (4U)
+#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CICR_MSIRDYC_Pos (5U)
+#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
+#define RCC_CICR_CSSLSEC_Pos (7U)
+#define RCC_CICR_CSSLSEC_Msk (0x1UL << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */
+#define RCC_CICR_CSSHSEC_Pos (8U)
+#define RCC_CICR_CSSHSEC_Msk (0x1UL << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */
+#define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */
+
+/* Reference defines */
+#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
+#define RCC_CICR_CSSC RCC_CICR_CSSHSEC
+/***************** Bit definition for RCC_IOPRSTR register ******************/
+#define RCC_IOPRSTR_IOPARST_Pos (0U)
+#define RCC_IOPRSTR_IOPARST_Msk (0x1UL << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */
+#define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */
+#define RCC_IOPRSTR_IOPBRST_Pos (1U)
+#define RCC_IOPRSTR_IOPBRST_Msk (0x1UL << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */
+#define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */
+#define RCC_IOPRSTR_IOPCRST_Pos (2U)
+#define RCC_IOPRSTR_IOPCRST_Msk (0x1UL << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */
+#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */
+#define RCC_IOPRSTR_IOPDRST_Pos (3U)
+#define RCC_IOPRSTR_IOPDRST_Msk (0x1UL << RCC_IOPRSTR_IOPDRST_Pos) /*!< 0x00000008 */
+#define RCC_IOPRSTR_IOPDRST RCC_IOPRSTR_IOPDRST_Msk /*!< GPIO port D reset */
+#define RCC_IOPRSTR_IOPERST_Pos (4U)
+#define RCC_IOPRSTR_IOPERST_Msk (0x1UL << RCC_IOPRSTR_IOPERST_Pos) /*!< 0x00000010 */
+#define RCC_IOPRSTR_IOPERST RCC_IOPRSTR_IOPERST_Msk /*!< GPIO port E reset */
+#define RCC_IOPRSTR_IOPHRST_Pos (7U)
+#define RCC_IOPRSTR_IOPHRST_Msk (0x1UL << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */
+#define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */
+
+/* Reference defines */
+#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
+#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
+#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
+#define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_IOPDRST /*!< GPIO port D reset */
+#define RCC_IOPRSTR_GPIOERST RCC_IOPRSTR_IOPERST /*!< GPIO port E reset */
+#define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
+
+
+/****************** Bit definition for RCC_AHBRST register ******************/
+#define RCC_AHBRSTR_DMARST_Pos (0U)
+#define RCC_AHBRSTR_DMARST_Msk (0x1UL << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */
+#define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */
+#define RCC_AHBRSTR_MIFRST_Pos (8U)
+#define RCC_AHBRSTR_MIFRST_Msk (0x1UL << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */
+#define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset */
+#define RCC_AHBRSTR_CRCRST_Pos (12U)
+#define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */
+
+/* Reference defines */
+#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
+#define RCC_APB2RSTR_TIM21RST_Pos (2U)
+#define RCC_APB2RSTR_TIM21RST_Msk (0x1UL << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 reset */
+#define RCC_APB2RSTR_TIM22RST_Pos (5U)
+#define RCC_APB2RSTR_TIM22RST_Msk (0x1UL << RCC_APB2RSTR_TIM22RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk /*!< TIM22 reset */
+#define RCC_APB2RSTR_ADCRST_Pos (9U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
+#define RCC_APB2RSTR_DBGRST_Pos (22U)
+#define RCC_APB2RSTR_DBGRST_Msk (0x1UL << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU reset */
+
+/* Reference defines */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 reset */
+#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU reset */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_LPUART1RST_Pos (18U)
+#define RCC_APB1RSTR_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
+#define RCC_APB1RSTR_LPTIM1RST_Pos (31U)
+#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 reset */
+
+/***************** Bit definition for RCC_IOPENR register ******************/
+#define RCC_IOPENR_IOPAEN_Pos (0U)
+#define RCC_IOPENR_IOPAEN_Msk (0x1UL << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */
+#define RCC_IOPENR_IOPBEN_Pos (1U)
+#define RCC_IOPENR_IOPBEN_Msk (0x1UL << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */
+#define RCC_IOPENR_IOPCEN_Pos (2U)
+#define RCC_IOPENR_IOPCEN_Msk (0x1UL << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */
+#define RCC_IOPENR_IOPDEN_Pos (3U)
+#define RCC_IOPENR_IOPDEN_Msk (0x1UL << RCC_IOPENR_IOPDEN_Pos) /*!< 0x00000008 */
+#define RCC_IOPENR_IOPDEN RCC_IOPENR_IOPDEN_Msk /*!< GPIO port D clock enable */
+#define RCC_IOPENR_IOPEEN_Pos (4U)
+#define RCC_IOPENR_IOPEEN_Msk (0x1UL << RCC_IOPENR_IOPEEN_Pos) /*!< 0x00000010 */
+#define RCC_IOPENR_IOPEEN RCC_IOPENR_IOPEEN_Msk /*!< GPIO port E clock enable */
+#define RCC_IOPENR_IOPHEN_Pos (7U)
+#define RCC_IOPENR_IOPHEN_Msk (0x1UL << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */
+
+/* Reference defines */
+#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
+#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
+#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
+#define RCC_IOPENR_GPIODEN RCC_IOPENR_IOPDEN /*!< GPIO port D clock enable */
+#define RCC_IOPENR_GPIOEEN RCC_IOPENR_IOPEEN /*!< GPIO port E clock enable */
+#define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
+
+/***************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMAEN_Pos (0U)
+#define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_MIFEN_Pos (8U)
+#define RCC_AHBENR_MIFEN_Msk (0x1UL << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */
+#define RCC_AHBENR_CRCEN_Pos (12U)
+#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+
+/* Reference defines */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register ******************/
+#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM21EN_Pos (2U)
+#define RCC_APB2ENR_TIM21EN_Msk (0x1UL << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */
+#define RCC_APB2ENR_TIM22EN_Pos (5U)
+#define RCC_APB2ENR_TIM22EN_Msk (0x1UL << RCC_APB2ENR_TIM22EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk /*!< TIM22 clock enable */
+#define RCC_APB2ENR_FWEN_Pos (7U)
+#define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADCEN_Pos (9U)
+#define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
+#define RCC_APB2ENR_DBGEN_Pos (22U)
+#define RCC_APB2ENR_DBGEN_Msk (0x1UL << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */
+
+/* Reference defines */
+
+#define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
+#define RCC_APB1ENR_LPUART1EN_Pos (18U)
+#define RCC_APB1ENR_LPUART1EN_Msk (0x1UL << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
+#define RCC_APB1ENR_LPTIM1EN_Pos (31U)
+#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */
+
+/****************** Bit definition for RCC_IOPSMENR register ****************/
+#define RCC_IOPSMENR_IOPASMEN_Pos (0U)
+#define RCC_IOPSMENR_IOPASMEN_Msk (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPBSMEN_Pos (1U)
+#define RCC_IOPSMENR_IOPBSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPCSMEN_Pos (2U)
+#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPDSMEN_Pos (3U)
+#define RCC_IOPSMENR_IOPDSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos) /*!< 0x00000008 */
+#define RCC_IOPSMENR_IOPDSMEN RCC_IOPSMENR_IOPDSMEN_Msk /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPESMEN_Pos (4U)
+#define RCC_IOPSMENR_IOPESMEN_Msk (0x1UL << RCC_IOPSMENR_IOPESMEN_Pos) /*!< 0x00000010 */
+#define RCC_IOPSMENR_IOPESMEN RCC_IOPSMENR_IOPESMEN_Msk /*!< GPIO port E clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPHSMEN_Pos (7U)
+#define RCC_IOPSMENR_IOPHSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_IOPDSMEN /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOESMEN RCC_IOPSMENR_IOPESMEN /*!< GPIO port E clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_AHBSMENR register ******************/
+#define RCC_AHBSMENR_DMASMEN_Pos (0U)
+#define RCC_AHBSMENR_DMASMEN_Msk (0x1UL << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */
+#define RCC_AHBSMENR_MIFSMEN_Pos (8U)
+#define RCC_AHBSMENR_MIFSMEN_Msk (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */
+#define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
+#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRCSMEN_Pos (12U)
+#define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB2SMENR register ******************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM21SMEN_Pos (2U)
+#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM22SMEN_Pos (5U)
+#define RCC_APB2SMENR_TIM22SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk /*!< TIM22 clock enabled in sleep mode */
+#define RCC_APB2SMENR_ADCSMEN_Pos (9U)
+#define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
+#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGSMEN_Pos (22U)
+#define RCC_APB2SMENR_DBGSMEN_Msk (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB1SMENR register ******************/
+#define RCC_APB1SMENR_TIM2SMEN_Pos (0U)
+#define RCC_APB1SMENR_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_WWDGSMEN_Pos (11U)
+#define RCC_APB1SMENR_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART2SMEN_Pos (17U)
+#define RCC_APB1SMENR_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPUART1SMEN_Pos (18U)
+#define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C1SMEN_Pos (21U)
+#define RCC_APB1SMENR_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_PWRSMEN_Pos (28U)
+#define RCC_APB1SMENR_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U)
+#define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */
+
+/*!< USART2 Clock source selection */
+#define RCC_CCIPR_USART2SEL_Pos (2U)
+#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */
+#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+/*!< LPUART1 Clock source selection */
+#define RCC_CCIPR_LPUART1SEL_Pos (10U)
+#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */
+#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */
+#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CCIPR_I2C1SEL_Pos (12U)
+#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */
+#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
+
+
+/*!< LPTIM1 Clock source selection */
+#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
+#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */
+#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+/******************* Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSEON_Pos (8U)
+#define RCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */
+#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_CSR_LSERDY_Pos (9U)
+#define RCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */
+#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP_Pos (10U)
+#define RCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */
+#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_CSR_LSEDRV_Pos (11U)
+#define RCC_CSR_LSEDRV_Msk (0x3UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */
+#define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_CSR_LSEDRV_0 (0x1UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */
+#define RCC_CSR_LSEDRV_1 (0x2UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */
+
+#define RCC_CSR_LSECSSON_Pos (13U)
+#define RCC_CSR_LSECSSON_Msk (0x1UL << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */
+#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */
+#define RCC_CSR_LSECSSD_Pos (14U)
+#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
+#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
+
+/*!< RTC congiguration */
+#define RCC_CSR_RTCSEL_Pos (16U)
+#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
+
+#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CSR_RTCSEL_LSE_Pos (16U)
+#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_LSI_Pos (17U)
+#define RCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */
+#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_HSE_Pos (16U)
+#define RCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */
+
+#define RCC_CSR_RTCEN_Pos (18U)
+#define RCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */
+#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_CSR_RTCRST_Pos (19U)
+#define RCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */
+#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */
+
+#define RCC_CSR_RMVF_Pos (23U)
+#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_OBLRSTF_Pos (25U)
+#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+/* Reference defines */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER1_SUPPORT
+#define RTC_TAMPER2_SUPPORT
+#define RTC_TAMPER3_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk /*!< */
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk /*!< */
+#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk /*!< */
+#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */
+#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */
+#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk /*!< */
+#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk /*!< */
+#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk /*!< */
+#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk /*!< */
+#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */
+#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk /*!< */
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk /*!< */
+#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk /*!< */
+#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk /*!< */
+#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk /*!< */
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */
+#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk /*!< */
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< */
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */
+#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */
+#define RTC_ISR_TAMP3F_Pos (15U)
+#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk /*!< */
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */
+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */
+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */
+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */
+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */
+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */
+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */
+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */
+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */
+#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */
+#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */
+#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */
+#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */
+#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */
+#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */
+#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */
+#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */
+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */
+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */
+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */
+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */
+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */
+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */
+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */
+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */
+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */
+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CALR register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */
+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define RTC_CAL_CALP RTC_CALR_CALP
+#define RTC_CAL_CALW8 RTC_CALR_CALW8
+#define RTC_CAL_CALW16 RTC_CALR_CALW16
+#define RTC_CAL_CALM RTC_CALR_CALM
+#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
+
+/******************** Bits definition for RTC_TAMPCR register ****************/
+#define RTC_TAMPCR_TAMP3MF_Pos (24U)
+#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
+#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
+#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
+#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP3IE_Pos (22U)
+#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
+#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2MF_Pos (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2IE_Pos (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1MF_Pos (18U)
+#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
+#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1IE_Pos (16U)
+#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */
+#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */
+#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */
+#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos (7U)
+#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */
+#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
+#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
+#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP3E_Pos (5U)
+#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
+#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk /*!< */
+#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP2E_Pos (3U)
+#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */
+#define RTC_TAMPCR_TAMPIE_Pos (2U)
+#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
+#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP1E_Pos (0U)
+#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_OR register ****************/
+#define RTC_OR_OUT_RMP_Pos (1U)
+#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */
+#define RTC_OR_ALARMOUTTYPE_Pos (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */
+
+/* Legacy defines */
+#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk /*!< */
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER (0x00000005U) /*!< */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/******************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
+#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR1_BOOT_MODE_Pos (8U)
+#define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
+#define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */
+#define SYSCFG_CFGR1_BOOT_MODE_0 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOT_MODE_1 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_FWDISEN_Pos (0U)
+#define SYSCFG_CFGR2_FWDISEN_Msk (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
+
+
+/***************** Bit definition for SYSCFG_CFGR3 register ****************/
+#define SYSCFG_CFGR3_EN_VREFINT_Pos (0U)
+#define SYSCFG_CFGR3_EN_VREFINT_Msk (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_EN_VREFINT SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
+#define SYSCFG_CFGR3_VREF_OUT_Pos (4U)
+#define SYSCFG_CFGR3_VREF_OUT_Msk (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
+#define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */
+#define SYSCFG_CFGR3_VREF_OUT_0 (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
+#define SYSCFG_CFGR3_VREF_OUT_1 (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U)
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U)
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U)
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
+#define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U)
+#define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
+#define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
+#define SYSCFG_CFGR3_REF_LOCK_Pos (31U)
+#define SYSCFG_CFGR3_REF_LOCK_Msk (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
+#define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */
+
+/* Legacy defines */
+
+#define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
+#define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
+#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
+#define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+
+/******************************************************************************/
+/* */
+/* Timers (TIM)*/
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
+#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
+ || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#else
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#endif
+
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFUL << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFUL << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM2_OR_ETR_RMP_Pos (0U)
+#define TIM2_OR_ETR_RMP_Msk (0x7UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000007 */
+#define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
+#define TIM2_OR_ETR_RMP_0 (0x1UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM2_OR_ETR_RMP_1 (0x2UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM2_OR_ETR_RMP_2 (0x4UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000004 */
+#define TIM2_OR_TI4_RMP_Pos (3U)
+#define TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000018 */
+#define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
+#define TIM2_OR_TI4_RMP_0 (0x1UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */
+#define TIM2_OR_TI4_RMP_1 (0x2UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000010 */
+
+#define TIM21_OR_ETR_RMP_Pos (0U)
+#define TIM21_OR_ETR_RMP_Msk (0x3UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
+#define TIM21_OR_ETR_RMP_0 (0x1UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM21_OR_ETR_RMP_1 (0x2UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM21_OR_TI1_RMP_Pos (2U)
+#define TIM21_OR_TI1_RMP_Msk (0x7UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x0000001C */
+#define TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
+#define TIM21_OR_TI1_RMP_0 (0x1UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM21_OR_TI1_RMP_1 (0x2UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+#define TIM21_OR_TI1_RMP_2 (0x4UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000010 */
+#define TIM21_OR_TI2_RMP_Pos (5U)
+#define TIM21_OR_TI2_RMP_Msk (0x1UL << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */
+#define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */
+
+#define TIM22_OR_ETR_RMP_Pos (0U)
+#define TIM22_OR_ETR_RMP_Msk (0x3UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM22_OR_ETR_RMP TIM22_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
+#define TIM22_OR_ETR_RMP_0 (0x1UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM22_OR_ETR_RMP_1 (0x2UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM22_OR_TI1_RMP_Pos (2U)
+#define TIM22_OR_TI1_RMP_Msk (0x3UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x0000000C */
+#define TIM22_OR_TI1_RMP TIM22_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
+#define TIM22_OR_TI1_RMP_0 (0x1UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM22_OR_TI1_RMP_1 (0x2UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE_Pos (0U)
+#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+#define USART_CR1_UESM_Pos (1U)
+#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
+#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_M0_Pos (12U)
+#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
+#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos (13U)
+#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos (14U)
+#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos (16U)
+#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
+#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
+#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
+#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
+#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos (21U)
+#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
+#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
+#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
+#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
+#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos (26U)
+#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos (27U)
+#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos (28U)
+#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
+#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7_Pos (4U)
+#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos (15U)
+#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos (16U)
+#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos (17U)
+#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos (18U)
+#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos (19U)
+#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos (20U)
+#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos (21U)
+#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos (23U)
+#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos (24U)
+#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos (12U)
+#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos (13U)
+#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos (14U)
+#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos (15U)
+#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos (17U)
+#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos (20U)
+#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
+#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
+#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos (22U)
+#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
+#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
+#define USART_CR3_UCESM_Pos (23U)
+#define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
+#define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION_Pos (0U)
+#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos (4U)
+#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO_Pos (0U)
+#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos (24U)
+#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ_Pos (0U)
+#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
+#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos (1U)
+#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
+#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos (2U)
+#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
+#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos (3U)
+#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
+#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos (4U)
+#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
+#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE_Pos (0U)
+#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
+#define USART_ISR_FE_Pos (1U)
+#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
+#define USART_ISR_NE_Pos (2U)
+#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos (3U)
+#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos (4U)
+#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos (5U)
+#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos (6U)
+#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos (7U)
+#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
+#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos (8U)
+#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos (9U)
+#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos (10U)
+#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
+#define USART_ISR_RTOF_Pos (11U)
+#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos (12U)
+#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos (14U)
+#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos (15U)
+#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos (16U)
+#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
+#define USART_ISR_CMF_Pos (17U)
+#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos (18U)
+#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos (19U)
+#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos (20U)
+#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
+#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos (21U)
+#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos (22U)
+#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
+#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF_Pos (0U)
+#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos (1U)
+#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos (2U)
+#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */
+#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos (3U)
+#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos (4U)
+#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos (6U)
+#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF_Pos (8U)
+#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos (9U)
+#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos (11U)
+#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos (12U)
+#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos (17U)
+#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos (20U)
+#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
+#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
+
+/* Compatibility defines with other series */
+#define USART_ICR_NECF USART_ICR_NCF
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR_Pos (0U)
+#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR_Pos (0U)
+#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOH))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
+
+
+
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SMBUS Instances *****************************/
+#define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/************* LPTIM instances supporting the encoder mode feature ************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM21) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM22) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/******************* TIM Instances : output(s) OCXEC register *****************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/****************** USART Instances : Auto Baud Rate detection ****************/
+
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32L0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32L0 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+
+#define RNG_LPUART1_IRQn LPUART1_IRQn
+#define AES_LPUART1_IRQn LPUART1_IRQn
+#define AES_RNG_LPUART1_IRQn LPUART1_IRQn
+#define RCC_CRS_IRQn RCC_IRQn
+#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
+#define ADC1_COMP_IRQn ADC1_IRQn
+
+/* Aliases for __IRQHandler */
+#define RNG_LPUART1_IRQHandler LPUART1_IRQHandler
+#define AES_LPUART1_IRQHandler LPUART1_IRQHandler
+#define AES_RNG_LPUART1_IRQHandler LPUART1_IRQHandler
+#define RCC_CRS_IRQHandler RCC_IRQHandler
+#define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
+#define ADC1_COMP_IRQHandler ADC1_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L010xB_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/CMSIS/device/stm32l011xx.h b/CMSIS/device/stm32l011xx.h
new file mode 100644
index 0000000..94a3797
--- /dev/null
+++ b/CMSIS/device/stm32l011xx.h
@@ -0,0 +1,5945 @@
+/**
+ ******************************************************************************
+ * @file stm32l011xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for stm32l011xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright(c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l011xx
+ * @{
+ */
+
+#ifndef __STM32L011xx_H
+#define __STM32L011xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 0U /*!< STM32L0xx provides no MPU */
+#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
+#define __NVIC_PRIO_BITS 2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief stm32l011xx Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+/*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
+
+/****** STM32L-0 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */
+ RCC_IRQn = 4, /*!< RCC Interrupt */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
+ ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
+ LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 Interrupt */
+ TIM21_IRQn = 20, /*!< TIM21 Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ USART2_IRQn = 28, /*!< USART2 Interrupt */
+ LPUART1_IRQn = 29, /*!< LPUART1 Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0plus.h"
+#include "system_stm32l0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+ uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Comparator
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
+} COMP_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+
+/**
+* @brief CRC calculation unit
+*/
+
+typedef struct
+{
+__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+uint8_t RESERVED0; /*!< Reserved, 0x05 */
+uint16_t RESERVED1; /*!< Reserved, 0x06 */
+__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+uint32_t RESERVED2; /*!< Reserved, 0x0C */
+__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
+} DMA_Request_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
+ __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
+ __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
+ __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
+ __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
+ __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
+ __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
+ __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
+ __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
+ __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
+} OB_TypeDef;
+
+
+/**
+ * @brief General Purpose IO
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief LPTIMIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+} LPTIM_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+ * @brief Independent WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
+ __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
+ __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
+ __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
+ __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
+ __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
+ __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
+ __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
+ __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
+ __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
+ __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */
+
+#define DATA_EEPROM_BASE (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
+#define DATA_EEPROM_END (0x080801FFUL) /*!< DATA EEPROM end address in the alias region */
+#define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */
+#define SRAM_SIZE_MAX (0x00000800UL) /*!< maximum SRAM size (up to 2KBytes) */
+
+#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000UL)
+
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
+#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800UL)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
+#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL)
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
+#define COMP1_BASE (APBPERIPH_BASE + 0x00010018UL)
+#define COMP2_BASE (APBPERIPH_BASE + 0x0001001CUL)
+#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL)
+#define TIM21_BASE (APBPERIPH_BASE + 0x00010800UL)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708UL)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
+#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL)
+
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
+#define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */
+#define FLASHSIZE_BASE (0x1FF8007CUL) /*!< FLASH Size register base address */
+#define UID_BASE (0x1FF80050UL) /*!< Unique device ID register base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
+
+#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL)
+#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL)
+#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
+/* Legacy defines */
+#define ADC ADC1_COMMON
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_EOCAL_Pos (11U)
+#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
+#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
+#define ADC_ISR_AWD_Pos (7U)
+#define ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
+#define ADC_ISR_EOSEQ_Pos (3U)
+#define ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_EOCALIE_Pos (11U)
+#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
+#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
+#define ADC_IER_AWDIE_Pos (7U)
+#define ADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE_Pos (3U)
+#define ADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH_Pos (26U)
+#define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
+#define ADC_CFGR1_AWDEN_Pos (23U)
+#define ADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL_Pos (22U)
+#define ADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN_Pos (16U)
+#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF_Pos (15U)
+#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
+#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT_Pos (14U)
+#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
+#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT_Pos (13U)
+#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD_Pos (12U)
+#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN_Pos (10U)
+#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
+#define ADC_CFGR1_EXTSEL_Pos (6U)
+#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
+#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
+#define ADC_CFGR1_ALIGN_Pos (5U)
+#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
+#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
+#define ADC_CFGR1_RES_Pos (3U)
+#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
+#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
+#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
+#define ADC_CFGR1_SCANDIR_Pos (2U)
+#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG_Pos (1U)
+#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
+#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN_Pos (0U)
+#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
+#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_TOVS_Pos (9U)
+#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
+#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+#define ADC_CFGR2_OVSR_Pos (2U)
+#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
+#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+#define ADC_CFGR2_OVSE_Pos (0U)
+#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
+#define ADC_CFGR2_CKMODE_Pos (30U)
+#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
+#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
+#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
+#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
+
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP_Pos (0U)
+#define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
+#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
+#define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
+#define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define ADC_SMPR_SMPR ADC_SMPR_SMP
+#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
+#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
+#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT_Pos (16U)
+#define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
+#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
+#define ADC_TR_LT_Pos (0U)
+#define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL_Pos (0U)
+#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
+#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
+#define ADC_CHSELR_CHSEL18_Pos (18U)
+#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17_Pos (17U)
+#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
+#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL15_Pos (15U)
+#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
+#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14_Pos (14U)
+#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
+#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13_Pos (13U)
+#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
+#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12_Pos (12U)
+#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
+#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11_Pos (11U)
+#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
+#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10_Pos (10U)
+#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
+#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9_Pos (9U)
+#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
+#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8_Pos (8U)
+#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
+#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7_Pos (7U)
+#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
+#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6_Pos (6U)
+#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
+#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5_Pos (5U)
+#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
+#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4_Pos (4U)
+#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
+#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3_Pos (3U)
+#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
+#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2_Pos (2U)
+#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
+#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1_Pos (1U)
+#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
+#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0_Pos (0U)
+#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
+#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_CALFACT_Pos (0U)
+#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_LFMEN_Pos (25U)
+#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
+#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
+#define ADC_CCR_TSEN_Pos (23U)
+#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+/************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN_Pos (0U)
+#define COMP_CSR_COMP1EN_Msk (0x1UL << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
+#define COMP_CSR_COMP1INNSEL_Pos (4U)
+#define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
+#define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP1WM_Pos (8U)
+#define COMP_CSR_COMP1WM_Msk (0x1UL << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */
+#define COMP_CSR_COMP1LPTIM1IN1_Pos (12U)
+#define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP1POLARITY_Pos (15U)
+#define COMP_CSR_COMP1POLARITY_Msk (0x1UL << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1VALUE_Pos (30U)
+#define COMP_CSR_COMP1VALUE_Msk (0x1UL << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK_Pos (31U)
+#define COMP_CSR_COMP1LOCK_Msk (0x1UL << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN_Pos (0U)
+#define COMP_CSR_COMP2EN_Msk (0x1UL << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
+#define COMP_CSR_COMP2SPEED_Pos (3U)
+#define COMP_CSR_COMP2SPEED_Msk (0x1UL << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */
+#define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */
+#define COMP_CSR_COMP2INNSEL_Pos (4U)
+#define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */
+#define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
+#define COMP_CSR_COMP2INPSEL_Pos (8U)
+#define COMP_CSR_COMP2INPSEL_Msk (0x7UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */
+#define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2INPSEL_0 (0x1UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP2INPSEL_1 (0x2UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */
+#define COMP_CSR_COMP2INPSEL_2 (0x4UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */
+#define COMP_CSR_COMP2LPTIM1IN2_Pos (12U)
+#define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */
+#define COMP_CSR_COMP2LPTIM1IN1_Pos (13U)
+#define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */
+#define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP2POLARITY_Pos (15U)
+#define COMP_CSR_COMP2POLARITY_Msk (0x1UL << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2VALUE_Pos (30U)
+#define COMP_CSR_COMP2VALUE_Msk (0x1UL << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK_Pos (31U)
+#define COMP_CSR_COMP2LOCK_Msk (0x1UL << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
+
+/********************** Bit definition for COMP_CSR register common ****************/
+#define COMP_CSR_COMPxEN_Pos (0U)
+#define COMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
+#define COMP_CSR_COMPxPOLARITY_Pos (15U)
+#define COMP_CSR_COMPxPOLARITY_Msk (0x1UL << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */
+#define COMP_CSR_COMPxOUTVALUE_Pos (30U)
+#define COMP_CSR_COMPxOUTVALUE_Msk (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK_Pos (31U)
+#define COMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
+
+/* Reference defines */
+#define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR (0xFFU) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos (3U)
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos (5U)
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos (7U)
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT_Pos (0U)
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL_Pos (0U)
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_Pos (0U)
+#define DBGMCU_CR_DBG_Msk (0x7UL << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
+#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+
+/******************* Bit definition for DMA_CSELR register *******************/
+#define DMA_CSELR_C1S_Pos (0U)
+#define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
+#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos (4U)
+#define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
+#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos (8U)
+#define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
+#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos (12U)
+#define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
+#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos (16U)
+#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
+#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_IM0_Pos (0U)
+#define EXTI_IMR_IM0_Msk (0x1UL << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_IM1_Pos (1U)
+#define EXTI_IMR_IM1_Msk (0x1UL << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_IM2_Pos (2U)
+#define EXTI_IMR_IM2_Msk (0x1UL << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_IM3_Pos (3U)
+#define EXTI_IMR_IM3_Msk (0x1UL << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_IM4_Pos (4U)
+#define EXTI_IMR_IM4_Msk (0x1UL << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_IM5_Pos (5U)
+#define EXTI_IMR_IM5_Msk (0x1UL << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_IM6_Pos (6U)
+#define EXTI_IMR_IM6_Msk (0x1UL << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_IM7_Pos (7U)
+#define EXTI_IMR_IM7_Msk (0x1UL << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_IM8_Pos (8U)
+#define EXTI_IMR_IM8_Msk (0x1UL << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_IM9_Pos (9U)
+#define EXTI_IMR_IM9_Msk (0x1UL << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_IM10_Pos (10U)
+#define EXTI_IMR_IM10_Msk (0x1UL << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_IM11_Pos (11U)
+#define EXTI_IMR_IM11_Msk (0x1UL << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_IM12_Pos (12U)
+#define EXTI_IMR_IM12_Msk (0x1UL << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_IM13_Pos (13U)
+#define EXTI_IMR_IM13_Msk (0x1UL << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_IM14_Pos (14U)
+#define EXTI_IMR_IM14_Msk (0x1UL << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_IM15_Pos (15U)
+#define EXTI_IMR_IM15_Msk (0x1UL << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_IM16_Pos (16U)
+#define EXTI_IMR_IM16_Msk (0x1UL << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_IM17_Pos (17U)
+#define EXTI_IMR_IM17_Msk (0x1UL << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_IM18_Pos (18U)
+#define EXTI_IMR_IM18_Msk (0x1UL << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_IM19_Pos (19U)
+#define EXTI_IMR_IM19_Msk (0x1UL << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_IM20_Pos (20U)
+#define EXTI_IMR_IM20_Msk (0x1UL << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_IM21_Pos (21U)
+#define EXTI_IMR_IM21_Msk (0x1UL << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_IM22_Pos (22U)
+#define EXTI_IMR_IM22_Msk (0x1UL << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_IM23_Pos (23U)
+#define EXTI_IMR_IM23_Msk (0x1UL << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
+#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_IM25_Pos (25U)
+#define EXTI_IMR_IM25_Msk (0x1UL << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */
+#define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_IM26_Pos (26U)
+#define EXTI_IMR_IM26_Msk (0x1UL << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
+#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_IM28_Pos (28U)
+#define EXTI_IMR_IM28_Msk (0x1UL << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
+#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_IM29_Pos (29U)
+#define EXTI_IMR_IM29_Msk (0x1UL << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
+#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
+
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x36FFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x36FFFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_EM0_Pos (0U)
+#define EXTI_EMR_EM0_Msk (0x1UL << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_EM1_Pos (1U)
+#define EXTI_EMR_EM1_Msk (0x1UL << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_EM2_Pos (2U)
+#define EXTI_EMR_EM2_Msk (0x1UL << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_EM3_Pos (3U)
+#define EXTI_EMR_EM3_Msk (0x1UL << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_EM4_Pos (4U)
+#define EXTI_EMR_EM4_Msk (0x1UL << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_EM5_Pos (5U)
+#define EXTI_EMR_EM5_Msk (0x1UL << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_EM6_Pos (6U)
+#define EXTI_EMR_EM6_Msk (0x1UL << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_EM7_Pos (7U)
+#define EXTI_EMR_EM7_Msk (0x1UL << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_EM8_Pos (8U)
+#define EXTI_EMR_EM8_Msk (0x1UL << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_EM9_Pos (9U)
+#define EXTI_EMR_EM9_Msk (0x1UL << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_EM10_Pos (10U)
+#define EXTI_EMR_EM10_Msk (0x1UL << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_EM11_Pos (11U)
+#define EXTI_EMR_EM11_Msk (0x1UL << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_EM12_Pos (12U)
+#define EXTI_EMR_EM12_Msk (0x1UL << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_EM13_Pos (13U)
+#define EXTI_EMR_EM13_Msk (0x1UL << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_EM14_Pos (14U)
+#define EXTI_EMR_EM14_Msk (0x1UL << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_EM15_Pos (15U)
+#define EXTI_EMR_EM15_Msk (0x1UL << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_EM16_Pos (16U)
+#define EXTI_EMR_EM16_Msk (0x1UL << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_EM17_Pos (17U)
+#define EXTI_EMR_EM17_Msk (0x1UL << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_EM18_Pos (18U)
+#define EXTI_EMR_EM18_Msk (0x1UL << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_EM19_Pos (19U)
+#define EXTI_EMR_EM19_Msk (0x1UL << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_EM20_Pos (20U)
+#define EXTI_EMR_EM20_Msk (0x1UL << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_EM21_Pos (21U)
+#define EXTI_EMR_EM21_Msk (0x1UL << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_EM22_Pos (22U)
+#define EXTI_EMR_EM22_Msk (0x1UL << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */
+#define EXTI_EMR_EM23_Pos (23U)
+#define EXTI_EMR_EM23_Msk (0x1UL << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
+#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
+#define EXTI_EMR_EM25_Pos (25U)
+#define EXTI_EMR_EM25_Msk (0x1UL << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */
+#define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */
+#define EXTI_EMR_EM26_Pos (26U)
+#define EXTI_EMR_EM26_Msk (0x1UL << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
+#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
+#define EXTI_EMR_EM28_Pos (28U)
+#define EXTI_EMR_EM28_Msk (0x1UL << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
+#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
+#define EXTI_EMR_EM29_Pos (29U)
+#define EXTI_EMR_EM29_Msk (0x1UL << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
+#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_RT0_Pos (0U)
+#define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_RT1_Pos (1U)
+#define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_RT2_Pos (2U)
+#define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_RT3_Pos (3U)
+#define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_RT4_Pos (4U)
+#define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_RT5_Pos (5U)
+#define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_RT6_Pos (6U)
+#define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_RT7_Pos (7U)
+#define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_RT8_Pos (8U)
+#define EXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_RT9_Pos (9U)
+#define EXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_RT10_Pos (10U)
+#define EXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_RT11_Pos (11U)
+#define EXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_RT12_Pos (12U)
+#define EXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_RT13_Pos (13U)
+#define EXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_RT14_Pos (14U)
+#define EXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_RT15_Pos (15U)
+#define EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_RT16_Pos (16U)
+#define EXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_RT17_Pos (17U)
+#define EXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_RT19_Pos (19U)
+#define EXTI_RTSR_RT19_Msk (0x1UL << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_RT20_Pos (20U)
+#define EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_RT21_Pos (21U)
+#define EXTI_RTSR_RT21_Msk (0x1UL << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_RT22_Pos (22U)
+#define EXTI_RTSR_RT22_Msk (0x1UL << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
+#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
+#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
+#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
+#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
+#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
+#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
+#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
+#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
+#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
+#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
+#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
+#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
+#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
+#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
+#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
+#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
+#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
+#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
+#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
+#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
+#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_FT0_Pos (0U)
+#define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_FT1_Pos (1U)
+#define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_FT2_Pos (2U)
+#define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_FT3_Pos (3U)
+#define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_FT4_Pos (4U)
+#define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_FT5_Pos (5U)
+#define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_FT6_Pos (6U)
+#define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_FT7_Pos (7U)
+#define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_FT8_Pos (8U)
+#define EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_FT9_Pos (9U)
+#define EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_FT10_Pos (10U)
+#define EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_FT11_Pos (11U)
+#define EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_FT12_Pos (12U)
+#define EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_FT13_Pos (13U)
+#define EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_FT14_Pos (14U)
+#define EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_FT15_Pos (15U)
+#define EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_FT16_Pos (16U)
+#define EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_FT17_Pos (17U)
+#define EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_FT19_Pos (19U)
+#define EXTI_FTSR_FT19_Msk (0x1UL << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_FT20_Pos (20U)
+#define EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_FT21_Pos (21U)
+#define EXTI_FTSR_FT21_Msk (0x1UL << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_FT22_Pos (22U)
+#define EXTI_FTSR_FT22_Msk (0x1UL << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
+#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
+#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
+#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
+#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
+#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
+#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
+#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
+#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
+#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
+#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
+#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
+#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
+#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
+#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
+#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
+#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
+#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
+#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
+#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
+#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
+#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWI0_Pos (0U)
+#define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWI1_Pos (1U)
+#define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWI2_Pos (2U)
+#define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWI3_Pos (3U)
+#define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWI4_Pos (4U)
+#define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWI5_Pos (5U)
+#define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWI6_Pos (6U)
+#define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWI7_Pos (7U)
+#define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWI8_Pos (8U)
+#define EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWI9_Pos (9U)
+#define EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWI10_Pos (10U)
+#define EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWI11_Pos (11U)
+#define EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWI12_Pos (12U)
+#define EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWI13_Pos (13U)
+#define EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWI14_Pos (14U)
+#define EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWI15_Pos (15U)
+#define EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWI16_Pos (16U)
+#define EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWI17_Pos (17U)
+#define EXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWI19_Pos (19U)
+#define EXTI_SWIER_SWI19_Msk (0x1UL << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWI20_Pos (20U)
+#define EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWI21_Pos (21U)
+#define EXTI_SWIER_SWI21_Msk (0x1UL << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWI22_Pos (22U)
+#define EXTI_SWIER_SWI22_Msk (0x1UL << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
+
+/* Legacy defines */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PIF0_Pos (0U)
+#define EXTI_PR_PIF0_Msk (0x1UL << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
+#define EXTI_PR_PIF1_Pos (1U)
+#define EXTI_PR_PIF1_Msk (0x1UL << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
+#define EXTI_PR_PIF2_Pos (2U)
+#define EXTI_PR_PIF2_Msk (0x1UL << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
+#define EXTI_PR_PIF3_Pos (3U)
+#define EXTI_PR_PIF3_Msk (0x1UL << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
+#define EXTI_PR_PIF4_Pos (4U)
+#define EXTI_PR_PIF4_Msk (0x1UL << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
+#define EXTI_PR_PIF5_Pos (5U)
+#define EXTI_PR_PIF5_Msk (0x1UL << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
+#define EXTI_PR_PIF6_Pos (6U)
+#define EXTI_PR_PIF6_Msk (0x1UL << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
+#define EXTI_PR_PIF7_Pos (7U)
+#define EXTI_PR_PIF7_Msk (0x1UL << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
+#define EXTI_PR_PIF8_Pos (8U)
+#define EXTI_PR_PIF8_Msk (0x1UL << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
+#define EXTI_PR_PIF9_Pos (9U)
+#define EXTI_PR_PIF9_Msk (0x1UL << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
+#define EXTI_PR_PIF10_Pos (10U)
+#define EXTI_PR_PIF10_Msk (0x1UL << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
+#define EXTI_PR_PIF11_Pos (11U)
+#define EXTI_PR_PIF11_Msk (0x1UL << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
+#define EXTI_PR_PIF12_Pos (12U)
+#define EXTI_PR_PIF12_Msk (0x1UL << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
+#define EXTI_PR_PIF13_Pos (13U)
+#define EXTI_PR_PIF13_Msk (0x1UL << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
+#define EXTI_PR_PIF14_Pos (14U)
+#define EXTI_PR_PIF14_Msk (0x1UL << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
+#define EXTI_PR_PIF15_Pos (15U)
+#define EXTI_PR_PIF15_Msk (0x1UL << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
+#define EXTI_PR_PIF16_Pos (16U)
+#define EXTI_PR_PIF16_Msk (0x1UL << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
+#define EXTI_PR_PIF17_Pos (17U)
+#define EXTI_PR_PIF17_Msk (0x1UL << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
+#define EXTI_PR_PIF19_Pos (19U)
+#define EXTI_PR_PIF19_Msk (0x1UL << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
+#define EXTI_PR_PIF20_Pos (20U)
+#define EXTI_PR_PIF20_Msk (0x1UL << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
+#define EXTI_PR_PIF21_Pos (21U)
+#define EXTI_PR_PIF21_Msk (0x1UL << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
+#define EXTI_PR_PIF22_Pos (22U)
+#define EXTI_PR_PIF22_Msk (0x1UL << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
+
+/* Legacy defines */
+#define EXTI_PR_PR0 EXTI_PR_PIF0
+#define EXTI_PR_PR1 EXTI_PR_PIF1
+#define EXTI_PR_PR2 EXTI_PR_PIF2
+#define EXTI_PR_PR3 EXTI_PR_PIF3
+#define EXTI_PR_PR4 EXTI_PR_PIF4
+#define EXTI_PR_PR5 EXTI_PR_PIF5
+#define EXTI_PR_PR6 EXTI_PR_PIF6
+#define EXTI_PR_PR7 EXTI_PR_PIF7
+#define EXTI_PR_PR8 EXTI_PR_PIF8
+#define EXTI_PR_PR9 EXTI_PR_PIF9
+#define EXTI_PR_PR10 EXTI_PR_PIF10
+#define EXTI_PR_PR11 EXTI_PR_PIF11
+#define EXTI_PR_PR12 EXTI_PR_PIF12
+#define EXTI_PR_PR13 EXTI_PR_PIF13
+#define EXTI_PR_PR14 EXTI_PR_PIF14
+#define EXTI_PR_PR15 EXTI_PR_PIF15
+#define EXTI_PR_PR16 EXTI_PR_PIF16
+#define EXTI_PR_PR17 EXTI_PR_PIF17
+#define EXTI_PR_PR19 EXTI_PR_PIF19
+#define EXTI_PR_PR20 EXTI_PR_PIF20
+#define EXTI_PR_PR21 EXTI_PR_PIF21
+#define EXTI_PR_PR22 EXTI_PR_PIF22
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
+#define FLASH_ACR_PRFTEN_Pos (1U)
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_SLEEP_PD_Pos (3U)
+#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD_Pos (4U)
+#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
+#define FLASH_ACR_DISAB_BUF_Pos (5U)
+#define FLASH_ACR_DISAB_BUF_Msk (0x1UL << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
+#define FLASH_ACR_PRE_READ_Pos (6U)
+#define FLASH_ACR_PRE_READ_Msk (0x1UL << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
+#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
+
+/******************* Bit definition for FLASH_PECR register ******************/
+#define FLASH_PECR_PELOCK_Pos (0U)
+#define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
+#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK_Pos (1U)
+#define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
+#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK_Pos (2U)
+#define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
+#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG_Pos (3U)
+#define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
+#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
+#define FLASH_PECR_DATA_Pos (4U)
+#define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
+#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
+#define FLASH_PECR_FIX_Pos (8U)
+#define FLASH_PECR_FIX_Msk (0x1UL << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
+#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE_Pos (9U)
+#define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
+#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
+#define FLASH_PECR_FPRG_Pos (10U)
+#define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
+#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_EOPIE_Pos (16U)
+#define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
+#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
+#define FLASH_PECR_ERRIE_Pos (17U)
+#define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
+#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
+#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
+#define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
+#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
+#define FLASH_PECR_HALF_ARRAY_Pos (19U)
+#define FLASH_PECR_HALF_ARRAY_Msk (0x1UL << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
+#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
+
+/****************** Bit definition for FLASH_PDKEYR register ******************/
+#define FLASH_PDKEYR_PDKEYR_Pos (0U)
+#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PEKEYR register ******************/
+#define FLASH_PEKEYR_PEKEYR_Pos (0U)
+#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PRGKEYR register ******************/
+#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
+#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
+
+/****************** Bit definition for FLASH_OPTKEYR register ******************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_EOP_Pos (1U)
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
+#define FLASH_SR_HVOFF_Pos (2U)
+#define FLASH_SR_HVOFF_Msk (0x1UL << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
+#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
+#define FLASH_SR_READY_Pos (3U)
+#define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */
+#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR_Pos (8U)
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
+#define FLASH_SR_PGAERR_Pos (9U)
+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR_Pos (10U)
+#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
+#define FLASH_SR_OPTVERR_Pos (11U)
+#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
+#define FLASH_SR_RDERR_Pos (13U)
+#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
+#define FLASH_SR_NOTZEROERR_Pos (16U)
+#define FLASH_SR_NOTZEROERR_Msk (0x1UL << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
+#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
+#define FLASH_SR_FWWERR_Pos (17U)
+#define FLASH_SR_FWWERR_Msk (0x1UL << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
+#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
+
+/* Legacy defines */
+#define FLASH_SR_FWWER FLASH_SR_FWWERR
+#define FLASH_SR_ENHV FLASH_SR_HVOFF
+#define FLASH_SR_ENDHV FLASH_SR_HVOFF
+
+/****************** Bit definition for FLASH_OPTR register *******************/
+#define FLASH_OPTR_RDPROT_Pos (0U)
+#define FLASH_OPTR_RDPROT_Msk (0xFFUL << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
+#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
+#define FLASH_OPTR_WPRMOD_Pos (8U)
+#define FLASH_OPTR_WPRMOD_Msk (0x1UL << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
+#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
+#define FLASH_OPTR_BOR_LEV_Pos (16U)
+#define FLASH_OPTR_BOR_LEV_Msk (0xFUL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
+#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OPTR_IWDG_SW_Pos (20U)
+#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
+#define FLASH_OPTR_nRST_STOP_Pos (21U)
+#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OPTR_nRST_STDBY_Pos (22U)
+#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OPTR_USER_Pos (20U)
+#define FLASH_OPTR_USER_Msk (0x7UL << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
+#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OPTR_BOOT1_Pos (31U)
+#define FLASH_OPTR_BOOT1_Msk (0x1UL << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
+#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 (0x00000001U)
+#define GPIO_OTYPER_OT_1 (0x00000002U)
+#define GPIO_OTYPER_OT_2 (0x00000004U)
+#define GPIO_OTYPER_OT_3 (0x00000008U)
+#define GPIO_OTYPER_OT_4 (0x00000010U)
+#define GPIO_OTYPER_OT_5 (0x00000020U)
+#define GPIO_OTYPER_OT_6 (0x00000040U)
+#define GPIO_OTYPER_OT_7 (0x00000080U)
+#define GPIO_OTYPER_OT_8 (0x00000100U)
+#define GPIO_OTYPER_OT_9 (0x00000200U)
+#define GPIO_OTYPER_OT_10 (0x00000400U)
+#define GPIO_OTYPER_OT_11 (0x00000800U)
+#define GPIO_OTYPER_OT_12 (0x00001000U)
+#define GPIO_OTYPER_OT_13 (0x00002000U)
+#define GPIO_OTYPER_OT_14 (0x00004000U)
+#define GPIO_OTYPER_OT_15 (0x00008000U)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDER_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
+#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDER_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
+#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDER_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
+#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDER_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
+#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDER_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
+#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDER_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
+#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDER_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
+#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDER_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
+#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDER_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
+#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDER_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
+#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDER_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
+#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDER_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
+#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDER_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
+#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDER_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
+#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDER_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
+#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDER_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
+#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 (0x00000001U)
+#define GPIO_BSRR_BS_1 (0x00000002U)
+#define GPIO_BSRR_BS_2 (0x00000004U)
+#define GPIO_BSRR_BS_3 (0x00000008U)
+#define GPIO_BSRR_BS_4 (0x00000010U)
+#define GPIO_BSRR_BS_5 (0x00000020U)
+#define GPIO_BSRR_BS_6 (0x00000040U)
+#define GPIO_BSRR_BS_7 (0x00000080U)
+#define GPIO_BSRR_BS_8 (0x00000100U)
+#define GPIO_BSRR_BS_9 (0x00000200U)
+#define GPIO_BSRR_BS_10 (0x00000400U)
+#define GPIO_BSRR_BS_11 (0x00000800U)
+#define GPIO_BSRR_BS_12 (0x00001000U)
+#define GPIO_BSRR_BS_13 (0x00002000U)
+#define GPIO_BSRR_BS_14 (0x00004000U)
+#define GPIO_BSRR_BS_15 (0x00008000U)
+#define GPIO_BSRR_BR_0 (0x00010000U)
+#define GPIO_BSRR_BR_1 (0x00020000U)
+#define GPIO_BSRR_BR_2 (0x00040000U)
+#define GPIO_BSRR_BR_3 (0x00080000U)
+#define GPIO_BSRR_BR_4 (0x00100000U)
+#define GPIO_BSRR_BR_5 (0x00200000U)
+#define GPIO_BSRR_BR_6 (0x00400000U)
+#define GPIO_BSRR_BR_7 (0x00800000U)
+#define GPIO_BSRR_BR_8 (0x01000000U)
+#define GPIO_BSRR_BR_9 (0x02000000U)
+#define GPIO_BSRR_BR_10 (0x04000000U)
+#define GPIO_BSRR_BR_11 (0x08000000U)
+#define GPIO_BSRR_BR_12 (0x10000000U)
+#define GPIO_BSRR_BR_13 (0x20000000U)
+#define GPIO_BSRR_BR_14 (0x40000000U)
+#define GPIO_BSRR_BR_15 (0x80000000U)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 (0x00000001U)
+#define GPIO_BRR_BR_1 (0x00000002U)
+#define GPIO_BRR_BR_2 (0x00000004U)
+#define GPIO_BRR_BR_3 (0x00000008U)
+#define GPIO_BRR_BR_4 (0x00000010U)
+#define GPIO_BRR_BR_5 (0x00000020U)
+#define GPIO_BRR_BR_6 (0x00000040U)
+#define GPIO_BRR_BR_7 (0x00000080U)
+#define GPIO_BRR_BR_8 (0x00000100U)
+#define GPIO_BRR_BR_9 (0x00000200U)
+#define GPIO_BRR_BR_10 (0x00000400U)
+#define GPIO_BRR_BR_11 (0x00000800U)
+#define GPIO_BRR_BR_12 (0x00001000U)
+#define GPIO_BRR_BR_13 (0x00002000U)
+#define GPIO_BRR_BR_14 (0x00004000U)
+#define GPIO_BRR_BR_15 (0x00008000U)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos (1U)
+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos (2U)
+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos (3U)
+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos (4U)
+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos (5U)
+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos (6U)
+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos (7U)
+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos (8U)
+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos (12U)
+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos (14U)
+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos (15U)
+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos (16U)
+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos (17U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos (18U)
+#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos (19U)
+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos (20U)
+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos (21U)
+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos (22U)
+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos (23U)
+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD_Pos (0U)
+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos (10U)
+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos (11U)
+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos (12U)
+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos (13U)
+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
+#define I2C_CR2_STOP_Pos (14U)
+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos (15U)
+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos (16U)
+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos (24U)
+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos (25U)
+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos (26U)
+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1_Pos (0U)
+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos (10U)
+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos (15U)
+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2_Pos (1U)
+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos (8U)
+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos (8U)
+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos (9U)
+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos (8U)
+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos (10U)
+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos (8U)
+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos (9U)
+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos (8U)
+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos (15U)
+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos (0U)
+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos (8U)
+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos (16U)
+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos (20U)
+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos (28U)
+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE_Pos (0U)
+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos (1U)
+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos (2U)
+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos (3U)
+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos (4U)
+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos (5U)
+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos (6U)
+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos (7U)
+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos (8U)
+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
+#define I2C_ISR_ARLO_Pos (9U)
+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos (10U)
+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos (11U)
+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos (12U)
+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos (13U)
+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos (15U)
+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
+#define I2C_ISR_DIR_Pos (16U)
+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos (17U)
+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF_Pos (3U)
+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos (4U)
+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos (5U)
+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos (8U)
+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos (9U)
+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos (10U)
+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos (11U)
+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos (12U)
+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos (13U)
+#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define I2C_PECR_PEC_Pos (0U)
+#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA_Pos (0U)
+#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA_Pos (0U)
+#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos (2U)
+#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN_Pos (0U)
+#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM_Pos (0U)
+#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos (1U)
+#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos (2U)
+#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos (3U)
+#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos (4U)
+#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos (5U)
+#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos (6U)
+#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF_Pos (0U)
+#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos (1U)
+#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos (3U)
+#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos (4U)
+#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos (5U)
+#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos (6U)
+#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos (0U)
+#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos (1U)
+#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos (3U)
+#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos (4U)
+#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos (5U)
+#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos (6U)
+#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos (0U)
+#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos (1U)
+#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos (3U)
+#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos (6U)
+#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos (9U)
+#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos (17U)
+#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos (19U)
+#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos (20U)
+#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos (21U)
+#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos (22U)
+#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos (24U)
+#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE_Pos (0U)
+#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos (1U)
+#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos (2U)
+#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP_Pos (0U)
+#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR_Pos (0U)
+#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT_Pos (0U)
+#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
+
+/******************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/******************************************************************************/
+
+#define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPSDSR_Pos (0U)
+#define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP_Pos (9U)
+#define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /*!< 0x00000200 */
+#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
+#define PWR_CR_FWU_Pos (10U)
+#define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /*!< 0x00000400 */
+#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
+
+#define PWR_CR_VOS_Pos (11U)
+#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x00001800 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /*!< 0x00000800 */
+#define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /*!< 0x00001000 */
+#define PWR_CR_DSEEKOFF_Pos (13U)
+#define PWR_CR_DSEEKOFF_Msk (0x1UL << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */
+#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */
+#define PWR_CR_LPRUN_Pos (14U)
+#define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
+#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
+#define PWR_CR_LPDS_Pos (16U)
+#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00010000 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< regulator in low power deepsleep mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF_Pos (3U)
+#define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
+#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF_Pos (4U)
+#define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
+#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF_Pos (5U)
+#define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
+#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1_Pos (8U)
+#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP3_Pos (10U)
+#define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
+#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos (1U)
+#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos (2U)
+#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIVEN_Pos (3U)
+#define RCC_CR_HSIDIVEN_Msk (0x1UL << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */
+#define RCC_CR_HSIDIVF_Pos (4U)
+#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */
+#define RCC_CR_HSIOUTEN_Pos (5U)
+#define RCC_CR_HSIOUTEN_Msk (0x1UL << RCC_CR_HSIOUTEN_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_Msk /*!< Internal High Speed clock out enable */
+#define RCC_CR_MSION_Pos (8U)
+#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000100 */
+#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY_Pos (9U)
+#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
+#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_RTCPRE_Pos (20U)
+#define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
+#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */
+#define RCC_CR_RTCPRE_0 (0x1UL << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */
+#define RCC_CR_RTCPRE_1 (0x2UL << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+/* Reference defines */
+
+/******************** Bit definition for RCC_ICSCR register *****************/
+#define RCC_ICSCR_HSICAL_Pos (0U)
+#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
+#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM_Pos (8U)
+#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
+#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE_Pos (13U)
+#define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
+#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
+#define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
+#define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
+#define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
+#define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
+#define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
+#define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
+#define RCC_ICSCR_MSICAL_Pos (16U)
+#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
+#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM_Pos (24U)
+#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
+#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos (15U)
+#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */
+
+/*!< PLL entry clock source*/
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
+
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL_Pos (18U)
+#define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV_Pos (22U)
+#define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
+
+#define RCC_CFGR_PLLDIV2_Pos (22U)
+#define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3_Pos (23U)
+#define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4_Pos (22U)
+#define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCOSEL_Pos (24U)
+#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
+#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
+
+#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
+#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCOSEL_HSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_MSI_Pos (24U)
+#define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
+#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_HSE_Pos (26U)
+#define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCOSEL_PLL_Pos (24U)
+#define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
+#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
+#define RCC_CFGR_MCOSEL_LSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
+#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
+#define RCC_CFGR_MCOSEL_LSE_Pos (24U)
+#define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
+
+#define RCC_CFGR_MCOPRE_Pos (28U)
+#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
+
+#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
+
+/* Legacy defines */
+#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
+#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
+#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
+#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
+#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
+#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
+#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
+#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
+#ifdef RCC_CFGR_MCOSEL_HSI48
+#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48
+#endif
+
+#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
+#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
+
+/*!<****************** Bit definition for RCC_CIER register ********************/
+#define RCC_CIER_LSIRDYIE_Pos (0U)
+#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIER_LSERDYIE_Pos (1U)
+#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIER_HSIRDYIE_Pos (2U)
+#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIER_HSERDYIE_Pos (3U)
+#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIER_PLLRDYIE_Pos (4U)
+#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIER_MSIRDYIE_Pos (5U)
+#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
+#define RCC_CIER_CSSLSE_Pos (7U)
+#define RCC_CIER_CSSLSE_Msk (0x1UL << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */
+
+/* Reference defines */
+#define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
+
+/*!<****************** Bit definition for RCC_CIFR register ********************/
+#define RCC_CIFR_LSIRDYF_Pos (0U)
+#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIFR_LSERDYF_Pos (1U)
+#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIFR_HSIRDYF_Pos (2U)
+#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIFR_HSERDYF_Pos (3U)
+#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIFR_PLLRDYF_Pos (4U)
+#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIFR_MSIRDYF_Pos (5U)
+#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
+#define RCC_CIFR_CSSLSEF_Pos (7U)
+#define RCC_CIFR_CSSLSEF_Msk (0x1UL << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */
+
+/* Reference defines */
+#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
+
+/*!<****************** Bit definition for RCC_CICR register ********************/
+#define RCC_CICR_LSIRDYC_Pos (0U)
+#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CICR_LSERDYC_Pos (1U)
+#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CICR_HSIRDYC_Pos (2U)
+#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CICR_HSERDYC_Pos (3U)
+#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CICR_PLLRDYC_Pos (4U)
+#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CICR_MSIRDYC_Pos (5U)
+#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
+#define RCC_CICR_CSSLSEC_Pos (7U)
+#define RCC_CICR_CSSLSEC_Msk (0x1UL << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */
+
+/* Reference defines */
+#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
+/***************** Bit definition for RCC_IOPRSTR register ******************/
+#define RCC_IOPRSTR_IOPARST_Pos (0U)
+#define RCC_IOPRSTR_IOPARST_Msk (0x1UL << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */
+#define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */
+#define RCC_IOPRSTR_IOPBRST_Pos (1U)
+#define RCC_IOPRSTR_IOPBRST_Msk (0x1UL << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */
+#define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */
+#define RCC_IOPRSTR_IOPCRST_Pos (2U)
+#define RCC_IOPRSTR_IOPCRST_Msk (0x1UL << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */
+#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */
+
+/* Reference defines */
+#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
+#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
+#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
+
+
+/****************** Bit definition for RCC_AHBRST register ******************/
+#define RCC_AHBRSTR_DMARST_Pos (0U)
+#define RCC_AHBRSTR_DMARST_Msk (0x1UL << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */
+#define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */
+#define RCC_AHBRSTR_MIFRST_Pos (8U)
+#define RCC_AHBRSTR_MIFRST_Msk (0x1UL << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */
+#define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset */
+#define RCC_AHBRSTR_CRCRST_Pos (12U)
+#define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */
+
+/* Reference defines */
+#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
+#define RCC_APB2RSTR_TIM21RST_Pos (2U)
+#define RCC_APB2RSTR_TIM21RST_Msk (0x1UL << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 reset */
+#define RCC_APB2RSTR_ADCRST_Pos (9U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
+#define RCC_APB2RSTR_DBGRST_Pos (22U)
+#define RCC_APB2RSTR_DBGRST_Msk (0x1UL << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU reset */
+
+/* Reference defines */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 reset */
+#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU reset */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_LPUART1RST_Pos (18U)
+#define RCC_APB1RSTR_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
+#define RCC_APB1RSTR_LPTIM1RST_Pos (31U)
+#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 reset */
+
+/***************** Bit definition for RCC_IOPENR register ******************/
+#define RCC_IOPENR_IOPAEN_Pos (0U)
+#define RCC_IOPENR_IOPAEN_Msk (0x1UL << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */
+#define RCC_IOPENR_IOPBEN_Pos (1U)
+#define RCC_IOPENR_IOPBEN_Msk (0x1UL << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */
+#define RCC_IOPENR_IOPCEN_Pos (2U)
+#define RCC_IOPENR_IOPCEN_Msk (0x1UL << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */
+
+/* Reference defines */
+#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
+#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
+#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
+
+/***************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMAEN_Pos (0U)
+#define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_MIFEN_Pos (8U)
+#define RCC_AHBENR_MIFEN_Msk (0x1UL << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */
+#define RCC_AHBENR_CRCEN_Pos (12U)
+#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+
+/* Reference defines */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register ******************/
+#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM21EN_Pos (2U)
+#define RCC_APB2ENR_TIM21EN_Msk (0x1UL << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */
+#define RCC_APB2ENR_FWEN_Pos (7U)
+#define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADCEN_Pos (9U)
+#define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
+#define RCC_APB2ENR_DBGEN_Pos (22U)
+#define RCC_APB2ENR_DBGEN_Msk (0x1UL << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */
+
+/* Reference defines */
+
+#define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
+#define RCC_APB1ENR_LPUART1EN_Pos (18U)
+#define RCC_APB1ENR_LPUART1EN_Msk (0x1UL << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
+#define RCC_APB1ENR_LPTIM1EN_Pos (31U)
+#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */
+
+/****************** Bit definition for RCC_IOPSMENR register ****************/
+#define RCC_IOPSMENR_IOPASMEN_Pos (0U)
+#define RCC_IOPSMENR_IOPASMEN_Msk (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPBSMEN_Pos (1U)
+#define RCC_IOPSMENR_IOPBSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPCSMEN_Pos (2U)
+#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_AHBSMENR register ******************/
+#define RCC_AHBSMENR_DMASMEN_Pos (0U)
+#define RCC_AHBSMENR_DMASMEN_Msk (0x1UL << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */
+#define RCC_AHBSMENR_MIFSMEN_Pos (8U)
+#define RCC_AHBSMENR_MIFSMEN_Msk (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */
+#define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
+#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRCSMEN_Pos (12U)
+#define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB2SMENR register ******************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM21SMEN_Pos (2U)
+#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */
+#define RCC_APB2SMENR_ADCSMEN_Pos (9U)
+#define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
+#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGSMEN_Pos (22U)
+#define RCC_APB2SMENR_DBGSMEN_Msk (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB1SMENR register ******************/
+#define RCC_APB1SMENR_TIM2SMEN_Pos (0U)
+#define RCC_APB1SMENR_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_WWDGSMEN_Pos (11U)
+#define RCC_APB1SMENR_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART2SMEN_Pos (17U)
+#define RCC_APB1SMENR_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPUART1SMEN_Pos (18U)
+#define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C1SMEN_Pos (21U)
+#define RCC_APB1SMENR_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_PWRSMEN_Pos (28U)
+#define RCC_APB1SMENR_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U)
+#define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */
+
+/*!< USART2 Clock source selection */
+#define RCC_CCIPR_USART2SEL_Pos (2U)
+#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */
+#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+/*!< LPUART1 Clock source selection */
+#define RCC_CCIPR_LPUART1SEL_Pos (10U)
+#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */
+#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */
+#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CCIPR_I2C1SEL_Pos (12U)
+#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */
+#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
+
+
+/*!< LPTIM1 Clock source selection */
+#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
+#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */
+#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+/******************* Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSEON_Pos (8U)
+#define RCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */
+#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_CSR_LSERDY_Pos (9U)
+#define RCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */
+#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP_Pos (10U)
+#define RCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */
+#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_CSR_LSEDRV_Pos (11U)
+#define RCC_CSR_LSEDRV_Msk (0x3UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */
+#define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_CSR_LSEDRV_0 (0x1UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */
+#define RCC_CSR_LSEDRV_1 (0x2UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */
+
+#define RCC_CSR_LSECSSON_Pos (13U)
+#define RCC_CSR_LSECSSON_Msk (0x1UL << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */
+#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */
+#define RCC_CSR_LSECSSD_Pos (14U)
+#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
+#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
+
+/*!< RTC congiguration */
+#define RCC_CSR_RTCSEL_Pos (16U)
+#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
+
+#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CSR_RTCSEL_LSE_Pos (16U)
+#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_LSI_Pos (17U)
+#define RCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */
+#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_HSE_Pos (16U)
+#define RCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */
+
+#define RCC_CSR_RTCEN_Pos (18U)
+#define RCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */
+#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_CSR_RTCRST_Pos (19U)
+#define RCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */
+#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */
+
+#define RCC_CSR_RMVF_Pos (23U)
+#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_OBLRSTF_Pos (25U)
+#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+/* Reference defines */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER2_SUPPORT
+#define RTC_TAMPER3_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk /*!< */
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk /*!< */
+#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk /*!< */
+#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */
+#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */
+#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk /*!< */
+#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk /*!< */
+#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk /*!< */
+#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk /*!< */
+#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */
+#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk /*!< */
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk /*!< */
+#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk /*!< */
+#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk /*!< */
+#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk /*!< */
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */
+#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk /*!< */
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< */
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */
+#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */
+#define RTC_ISR_TAMP3F_Pos (15U)
+#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk /*!< */
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */
+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */
+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */
+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */
+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */
+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */
+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */
+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */
+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */
+#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */
+#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */
+#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */
+#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */
+#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */
+#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */
+#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */
+#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */
+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */
+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */
+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */
+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */
+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */
+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */
+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */
+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */
+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */
+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CALR register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */
+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define RTC_CAL_CALP RTC_CALR_CALP
+#define RTC_CAL_CALW8 RTC_CALR_CALW8
+#define RTC_CAL_CALW16 RTC_CALR_CALW16
+#define RTC_CAL_CALM RTC_CALR_CALM
+#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
+
+/******************** Bits definition for RTC_TAMPCR register ****************/
+#define RTC_TAMPCR_TAMP3MF_Pos (24U)
+#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
+#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
+#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
+#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP3IE_Pos (22U)
+#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
+#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2MF_Pos (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2IE_Pos (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */
+#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */
+#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */
+#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos (7U)
+#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */
+#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
+#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
+#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP3E_Pos (5U)
+#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
+#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk /*!< */
+#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP2E_Pos (3U)
+#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */
+#define RTC_TAMPCR_TAMPIE_Pos (2U)
+#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_OR register ****************/
+#define RTC_OR_OUT_RMP_Pos (1U)
+#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */
+#define RTC_OR_ALARMOUTTYPE_Pos (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */
+
+/* Legacy defines */
+#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk /*!< */
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER (0x00000005U) /*!< */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/******************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
+#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR1_BOOT_MODE_Pos (8U)
+#define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
+#define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */
+#define SYSCFG_CFGR1_BOOT_MODE_0 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOT_MODE_1 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_FWDISEN_Pos (0U)
+#define SYSCFG_CFGR2_FWDISEN_Msk (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos (8U)
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR2_I2C_PB6_FMP SYSCFG_CFGR2_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos (9U)
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR2_I2C_PB7_FMP SYSCFG_CFGR2_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos (10U)
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
+#define SYSCFG_CFGR2_I2C_PB8_FMP SYSCFG_CFGR2_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos (11U)
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
+#define SYSCFG_CFGR2_I2C_PB9_FMP SYSCFG_CFGR2_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR2_I2C1_FMP_Pos (12U)
+#define SYSCFG_CFGR2_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR2_I2C1_FMP SYSCFG_CFGR2_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
+
+
+/***************** Bit definition for SYSCFG_CFGR3 register ****************/
+#define SYSCFG_CFGR3_EN_VREFINT_Pos (0U)
+#define SYSCFG_CFGR3_EN_VREFINT_Msk (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_EN_VREFINT SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
+#define SYSCFG_CFGR3_VREF_OUT_Pos (4U)
+#define SYSCFG_CFGR3_VREF_OUT_Msk (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
+#define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */
+#define SYSCFG_CFGR3_VREF_OUT_0 (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
+#define SYSCFG_CFGR3_VREF_OUT_1 (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U)
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U)
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U)
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
+#define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U)
+#define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
+#define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
+#define SYSCFG_CFGR3_REF_LOCK_Pos (31U)
+#define SYSCFG_CFGR3_REF_LOCK_Msk (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
+#define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */
+
+/* Legacy defines */
+
+#define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
+#define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
+#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
+#define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+
+/******************************************************************************/
+/* */
+/* Timers (TIM)*/
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
+#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
+ || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#else
+#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
+#endif
+
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFUL << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFUL << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM2_OR_ETR_RMP_Pos (0U)
+#define TIM2_OR_ETR_RMP_Msk (0x7UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000007 */
+#define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
+#define TIM2_OR_ETR_RMP_0 (0x1UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM2_OR_ETR_RMP_1 (0x2UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM2_OR_ETR_RMP_2 (0x4UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000004 */
+#define TIM2_OR_TI4_RMP_Pos (3U)
+#define TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000018 */
+#define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
+#define TIM2_OR_TI4_RMP_0 (0x1UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */
+#define TIM2_OR_TI4_RMP_1 (0x2UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000010 */
+
+#define TIM21_OR_ETR_RMP_Pos (0U)
+#define TIM21_OR_ETR_RMP_Msk (0x3UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
+#define TIM21_OR_ETR_RMP_0 (0x1UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM21_OR_ETR_RMP_1 (0x2UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM21_OR_TI1_RMP_Pos (2U)
+#define TIM21_OR_TI1_RMP_Msk (0x7UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x0000001C */
+#define TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
+#define TIM21_OR_TI1_RMP_0 (0x1UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM21_OR_TI1_RMP_1 (0x2UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+#define TIM21_OR_TI1_RMP_2 (0x4UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000010 */
+#define TIM21_OR_TI2_RMP_Pos (5U)
+#define TIM21_OR_TI2_RMP_Msk (0x1UL << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */
+#define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+#define USART_TCBGT_SUPPORT /*!< Transmission completed before guard time interrupt support */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE_Pos (0U)
+#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+#define USART_CR1_UESM_Pos (1U)
+#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
+#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_M0_Pos (12U)
+#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
+#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos (13U)
+#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos (14U)
+#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos (16U)
+#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
+#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
+#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
+#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
+#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos (21U)
+#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
+#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
+#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
+#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
+#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos (26U)
+#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos (27U)
+#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos (28U)
+#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
+#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7_Pos (4U)
+#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos (15U)
+#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos (16U)
+#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos (17U)
+#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos (18U)
+#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos (19U)
+#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos (20U)
+#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos (21U)
+#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos (23U)
+#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos (24U)
+#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos (12U)
+#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos (13U)
+#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos (14U)
+#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos (15U)
+#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos (17U)
+#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos (20U)
+#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
+#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
+#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos (22U)
+#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
+#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
+#define USART_CR3_UCESM_Pos (23U)
+#define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
+#define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
+#define USART_CR3_TCBGTIE_Pos (24U)
+#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
+#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION_Pos (0U)
+#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos (4U)
+#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO_Pos (0U)
+#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos (24U)
+#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ_Pos (0U)
+#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
+#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos (1U)
+#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
+#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos (2U)
+#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
+#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos (3U)
+#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
+#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos (4U)
+#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
+#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE_Pos (0U)
+#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
+#define USART_ISR_FE_Pos (1U)
+#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
+#define USART_ISR_NE_Pos (2U)
+#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos (3U)
+#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos (4U)
+#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos (5U)
+#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos (6U)
+#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos (7U)
+#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
+#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos (8U)
+#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos (9U)
+#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos (10U)
+#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
+#define USART_ISR_RTOF_Pos (11U)
+#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos (12U)
+#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos (14U)
+#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos (15U)
+#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos (16U)
+#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
+#define USART_ISR_CMF_Pos (17U)
+#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos (18U)
+#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos (19U)
+#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos (20U)
+#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
+#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos (21U)
+#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos (22U)
+#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
+#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
+#define USART_ISR_TCBGT_Pos (25U)
+#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
+#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time Completion Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF_Pos (0U)
+#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos (1U)
+#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos (2U)
+#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */
+#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos (3U)
+#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos (4U)
+#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos (6U)
+#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
+#define USART_ICR_TCBGTCF_Pos (7U)
+#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
+#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
+#define USART_ICR_LBDCF_Pos (8U)
+#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos (9U)
+#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos (11U)
+#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos (12U)
+#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos (17U)
+#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos (20U)
+#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
+#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
+
+/* Compatibility defines with other series */
+#define USART_ICR_NECF USART_ICR_NCF
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR_Pos (0U)
+#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR_Pos (0U)
+#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+/******************************* COMP Instances *******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+ ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
+
+
+
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SMBUS Instances *****************************/
+#define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/************* LPTIM instances supporting the encoder mode feature ************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM21) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/******************* TIM Instances : output(s) OCXEC register *****************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (1 == 0)
+
+/****************** USART Instances : Auto Baud Rate detection ****************/
+
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (1 == 0)
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (1==0)
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32L0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32L0 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+
+#define RNG_LPUART1_IRQn LPUART1_IRQn
+#define AES_LPUART1_IRQn LPUART1_IRQn
+#define AES_RNG_LPUART1_IRQn LPUART1_IRQn
+#define RCC_CRS_IRQn RCC_IRQn
+#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
+#define ADC1_IRQn ADC1_COMP_IRQn
+
+/* Aliases for __IRQHandler */
+#define RNG_LPUART1_IRQHandler LPUART1_IRQHandler
+#define AES_LPUART1_IRQHandler LPUART1_IRQHandler
+#define AES_RNG_LPUART1_IRQHandler LPUART1_IRQHandler
+#define RCC_CRS_IRQHandler RCC_IRQHandler
+#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
+#define ADC1_IRQHandler ADC1_COMP_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L011xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/CMSIS/device/stm32l021xx.h b/CMSIS/device/stm32l021xx.h
new file mode 100644
index 0000000..046fda3
--- /dev/null
+++ b/CMSIS/device/stm32l021xx.h
@@ -0,0 +1,6085 @@
+/**
+ ******************************************************************************
+ * @file stm32l021xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for stm32l021xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright(c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l021xx
+ * @{
+ */
+
+#ifndef __STM32L021xx_H
+#define __STM32L021xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 0U /*!< STM32L0xx provides no MPU */
+#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
+#define __NVIC_PRIO_BITS 2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief stm32l021xx Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+/*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
+
+/****** STM32L-0 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */
+ RCC_IRQn = 4, /*!< RCC Interrupt */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
+ ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
+ LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 Interrupt */
+ TIM21_IRQn = 20, /*!< TIM21 Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ USART2_IRQn = 28, /*!< USART2 Interrupt */
+ AES_LPUART1_IRQn = 29, /*!< AES and LPUART1 Interrupts */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0plus.h"
+#include "system_stm32l0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+ uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+} ADC_Common_TypeDef;
+
+/**
+ * @brief AES hardware accelerator
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
+ __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
+ __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
+ __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
+ __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
+ __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
+ __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
+ __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
+ __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
+ __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
+ __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
+} AES_TypeDef;
+
+/**
+ * @brief Comparator
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
+} COMP_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+
+/**
+* @brief CRC calculation unit
+*/
+
+typedef struct
+{
+__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+uint8_t RESERVED0; /*!< Reserved, 0x05 */
+uint16_t RESERVED1; /*!< Reserved, 0x06 */
+__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+uint32_t RESERVED2; /*!< Reserved, 0x0C */
+__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
+} DMA_Request_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
+ __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
+ __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
+ __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
+ __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
+ __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
+ __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
+ __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
+ __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
+ __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
+} OB_TypeDef;
+
+
+/**
+ * @brief General Purpose IO
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief LPTIMIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+} LPTIM_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+ * @brief Independent WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
+ __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
+ __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
+ __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
+ __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
+ __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
+ __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
+ __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
+ __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
+ __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
+ __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */
+
+#define DATA_EEPROM_BASE (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
+#define DATA_EEPROM_END (0x080801FFUL) /*!< DATA EEPROM end address in the alias region */
+#define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */
+#define SRAM_SIZE_MAX (0x00000800UL) /*!< maximum SRAM size (up to 2KBytes) */
+
+#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000UL)
+
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
+#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800UL)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
+#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL)
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
+#define COMP1_BASE (APBPERIPH_BASE + 0x00010018UL)
+#define COMP2_BASE (APBPERIPH_BASE + 0x0001001CUL)
+#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL)
+#define TIM21_BASE (APBPERIPH_BASE + 0x00010800UL)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708UL)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
+#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL)
+
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
+#define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */
+#define FLASHSIZE_BASE (0x1FF8007CUL) /*!< FLASH Size register base address */
+#define UID_BASE (0x1FF80050UL) /*!< Unique device ID register base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
+#define AES_BASE (AHBPERIPH_BASE + 0x00006000UL)
+
+#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL)
+#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL)
+#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
+/* Legacy defines */
+#define ADC ADC1_COMMON
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define AES ((AES_TypeDef *) AES_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_EOCAL_Pos (11U)
+#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
+#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
+#define ADC_ISR_AWD_Pos (7U)
+#define ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
+#define ADC_ISR_EOSEQ_Pos (3U)
+#define ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_EOCALIE_Pos (11U)
+#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
+#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
+#define ADC_IER_AWDIE_Pos (7U)
+#define ADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE_Pos (3U)
+#define ADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH_Pos (26U)
+#define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
+#define ADC_CFGR1_AWDEN_Pos (23U)
+#define ADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL_Pos (22U)
+#define ADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN_Pos (16U)
+#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF_Pos (15U)
+#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
+#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT_Pos (14U)
+#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
+#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT_Pos (13U)
+#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD_Pos (12U)
+#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN_Pos (10U)
+#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
+#define ADC_CFGR1_EXTSEL_Pos (6U)
+#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
+#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
+#define ADC_CFGR1_ALIGN_Pos (5U)
+#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
+#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
+#define ADC_CFGR1_RES_Pos (3U)
+#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
+#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
+#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
+#define ADC_CFGR1_SCANDIR_Pos (2U)
+#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG_Pos (1U)
+#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
+#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN_Pos (0U)
+#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
+#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_TOVS_Pos (9U)
+#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
+#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+#define ADC_CFGR2_OVSR_Pos (2U)
+#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
+#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+#define ADC_CFGR2_OVSE_Pos (0U)
+#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
+#define ADC_CFGR2_CKMODE_Pos (30U)
+#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
+#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
+#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
+#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
+
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP_Pos (0U)
+#define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
+#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
+#define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
+#define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define ADC_SMPR_SMPR ADC_SMPR_SMP
+#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
+#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
+#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT_Pos (16U)
+#define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
+#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
+#define ADC_TR_LT_Pos (0U)
+#define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL_Pos (0U)
+#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
+#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
+#define ADC_CHSELR_CHSEL18_Pos (18U)
+#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17_Pos (17U)
+#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
+#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL15_Pos (15U)
+#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
+#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14_Pos (14U)
+#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
+#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13_Pos (13U)
+#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
+#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12_Pos (12U)
+#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
+#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11_Pos (11U)
+#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
+#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10_Pos (10U)
+#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
+#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9_Pos (9U)
+#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
+#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8_Pos (8U)
+#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
+#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7_Pos (7U)
+#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
+#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6_Pos (6U)
+#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
+#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5_Pos (5U)
+#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
+#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4_Pos (4U)
+#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
+#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3_Pos (3U)
+#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
+#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2_Pos (2U)
+#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
+#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1_Pos (1U)
+#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
+#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0_Pos (0U)
+#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
+#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_CALFACT_Pos (0U)
+#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_LFMEN_Pos (25U)
+#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
+#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
+#define ADC_CCR_TSEN_Pos (23U)
+#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+/******************************************************************************/
+/* */
+/* Advanced Encryption Standard (AES) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for AES_CR register *********************/
+#define AES_CR_EN_Pos (0U)
+#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */
+#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */
+#define AES_CR_DATATYPE_Pos (1U)
+#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */
+#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */
+#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */
+#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */
+
+#define AES_CR_MODE_Pos (3U)
+#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */
+#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */
+#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */
+#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */
+
+#define AES_CR_CHMOD_Pos (5U)
+#define AES_CR_CHMOD_Msk (0x3UL << AES_CR_CHMOD_Pos) /*!< 0x00000060 */
+#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */
+#define AES_CR_CHMOD_0 (0x1UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */
+#define AES_CR_CHMOD_1 (0x2UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */
+
+#define AES_CR_CCFC_Pos (7U)
+#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */
+#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */
+#define AES_CR_ERRC_Pos (8U)
+#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */
+#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */
+#define AES_CR_CCIE_Pos (9U)
+#define AES_CR_CCIE_Msk (0x1UL << AES_CR_CCIE_Pos) /*!< 0x00000200 */
+#define AES_CR_CCIE AES_CR_CCIE_Msk /*!< Computation Complete Interrupt Enable */
+#define AES_CR_ERRIE_Pos (10U)
+#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */
+#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */
+#define AES_CR_DMAINEN_Pos (11U)
+#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */
+#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< DMA ENable managing the data input phase */
+#define AES_CR_DMAOUTEN_Pos (12U)
+#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */
+#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< DMA Enable managing the data output phase */
+
+/******************* Bit definition for AES_SR register *********************/
+#define AES_SR_CCF_Pos (0U)
+#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */
+#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */
+#define AES_SR_RDERR_Pos (1U)
+#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */
+#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */
+#define AES_SR_WRERR_Pos (2U)
+#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */
+#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */
+
+/******************* Bit definition for AES_DINR register *******************/
+#define AES_DINR_Pos (0U)
+#define AES_DINR_Msk (0xFFFFUL << AES_DINR_Pos) /*!< 0x0000FFFF */
+#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */
+
+/******************* Bit definition for AES_DOUTR register ******************/
+#define AES_DOUTR_Pos (0U)
+#define AES_DOUTR_Msk (0xFFFFUL << AES_DOUTR_Pos) /*!< 0x0000FFFF */
+#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */
+
+/******************* Bit definition for AES_KEYR0 register ******************/
+#define AES_KEYR0_Pos (0U)
+#define AES_KEYR0_Msk (0xFFFFUL << AES_KEYR0_Pos) /*!< 0x0000FFFF */
+#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */
+
+/******************* Bit definition for AES_KEYR1 register ******************/
+#define AES_KEYR1_Pos (0U)
+#define AES_KEYR1_Msk (0xFFFFUL << AES_KEYR1_Pos) /*!< 0x0000FFFF */
+#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */
+
+/******************* Bit definition for AES_KEYR2 register ******************/
+#define AES_KEYR2_Pos (0U)
+#define AES_KEYR2_Msk (0xFFFFUL << AES_KEYR2_Pos) /*!< 0x0000FFFF */
+#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */
+
+/******************* Bit definition for AES_KEYR3 register ******************/
+#define AES_KEYR3_Pos (0U)
+#define AES_KEYR3_Msk (0xFFFFUL << AES_KEYR3_Pos) /*!< 0x0000FFFF */
+#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */
+
+/******************* Bit definition for AES_IVR0 register *******************/
+#define AES_IVR0_Pos (0U)
+#define AES_IVR0_Msk (0xFFFFUL << AES_IVR0_Pos) /*!< 0x0000FFFF */
+#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */
+
+/******************* Bit definition for AES_IVR1 register *******************/
+#define AES_IVR1_Pos (0U)
+#define AES_IVR1_Msk (0xFFFFUL << AES_IVR1_Pos) /*!< 0x0000FFFF */
+#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */
+
+/******************* Bit definition for AES_IVR2 register *******************/
+#define AES_IVR2_Pos (0U)
+#define AES_IVR2_Msk (0xFFFFUL << AES_IVR2_Pos) /*!< 0x0000FFFF */
+#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */
+
+/******************* Bit definition for AES_IVR3 register *******************/
+#define AES_IVR3_Pos (0U)
+#define AES_IVR3_Msk (0xFFFFUL << AES_IVR3_Pos) /*!< 0x0000FFFF */
+#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+/************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN_Pos (0U)
+#define COMP_CSR_COMP1EN_Msk (0x1UL << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
+#define COMP_CSR_COMP1INNSEL_Pos (4U)
+#define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
+#define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP1WM_Pos (8U)
+#define COMP_CSR_COMP1WM_Msk (0x1UL << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */
+#define COMP_CSR_COMP1LPTIM1IN1_Pos (12U)
+#define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP1POLARITY_Pos (15U)
+#define COMP_CSR_COMP1POLARITY_Msk (0x1UL << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1VALUE_Pos (30U)
+#define COMP_CSR_COMP1VALUE_Msk (0x1UL << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK_Pos (31U)
+#define COMP_CSR_COMP1LOCK_Msk (0x1UL << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN_Pos (0U)
+#define COMP_CSR_COMP2EN_Msk (0x1UL << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
+#define COMP_CSR_COMP2SPEED_Pos (3U)
+#define COMP_CSR_COMP2SPEED_Msk (0x1UL << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */
+#define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */
+#define COMP_CSR_COMP2INNSEL_Pos (4U)
+#define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */
+#define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
+#define COMP_CSR_COMP2INPSEL_Pos (8U)
+#define COMP_CSR_COMP2INPSEL_Msk (0x7UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */
+#define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2INPSEL_0 (0x1UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP2INPSEL_1 (0x2UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */
+#define COMP_CSR_COMP2INPSEL_2 (0x4UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */
+#define COMP_CSR_COMP2LPTIM1IN2_Pos (12U)
+#define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */
+#define COMP_CSR_COMP2LPTIM1IN1_Pos (13U)
+#define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */
+#define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP2POLARITY_Pos (15U)
+#define COMP_CSR_COMP2POLARITY_Msk (0x1UL << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2VALUE_Pos (30U)
+#define COMP_CSR_COMP2VALUE_Msk (0x1UL << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK_Pos (31U)
+#define COMP_CSR_COMP2LOCK_Msk (0x1UL << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
+
+/********************** Bit definition for COMP_CSR register common ****************/
+#define COMP_CSR_COMPxEN_Pos (0U)
+#define COMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
+#define COMP_CSR_COMPxPOLARITY_Pos (15U)
+#define COMP_CSR_COMPxPOLARITY_Msk (0x1UL << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */
+#define COMP_CSR_COMPxOUTVALUE_Pos (30U)
+#define COMP_CSR_COMPxOUTVALUE_Msk (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK_Pos (31U)
+#define COMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
+
+/* Reference defines */
+#define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR (0xFFU) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos (3U)
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos (5U)
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos (7U)
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT_Pos (0U)
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL_Pos (0U)
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_Pos (0U)
+#define DBGMCU_CR_DBG_Msk (0x7UL << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
+#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+
+/******************* Bit definition for DMA_CSELR register *******************/
+#define DMA_CSELR_C1S_Pos (0U)
+#define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
+#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos (4U)
+#define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
+#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos (8U)
+#define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
+#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos (12U)
+#define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
+#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos (16U)
+#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
+#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_IM0_Pos (0U)
+#define EXTI_IMR_IM0_Msk (0x1UL << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_IM1_Pos (1U)
+#define EXTI_IMR_IM1_Msk (0x1UL << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_IM2_Pos (2U)
+#define EXTI_IMR_IM2_Msk (0x1UL << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_IM3_Pos (3U)
+#define EXTI_IMR_IM3_Msk (0x1UL << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_IM4_Pos (4U)
+#define EXTI_IMR_IM4_Msk (0x1UL << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_IM5_Pos (5U)
+#define EXTI_IMR_IM5_Msk (0x1UL << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_IM6_Pos (6U)
+#define EXTI_IMR_IM6_Msk (0x1UL << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_IM7_Pos (7U)
+#define EXTI_IMR_IM7_Msk (0x1UL << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_IM8_Pos (8U)
+#define EXTI_IMR_IM8_Msk (0x1UL << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_IM9_Pos (9U)
+#define EXTI_IMR_IM9_Msk (0x1UL << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_IM10_Pos (10U)
+#define EXTI_IMR_IM10_Msk (0x1UL << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_IM11_Pos (11U)
+#define EXTI_IMR_IM11_Msk (0x1UL << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_IM12_Pos (12U)
+#define EXTI_IMR_IM12_Msk (0x1UL << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_IM13_Pos (13U)
+#define EXTI_IMR_IM13_Msk (0x1UL << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_IM14_Pos (14U)
+#define EXTI_IMR_IM14_Msk (0x1UL << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_IM15_Pos (15U)
+#define EXTI_IMR_IM15_Msk (0x1UL << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_IM16_Pos (16U)
+#define EXTI_IMR_IM16_Msk (0x1UL << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_IM17_Pos (17U)
+#define EXTI_IMR_IM17_Msk (0x1UL << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_IM18_Pos (18U)
+#define EXTI_IMR_IM18_Msk (0x1UL << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_IM19_Pos (19U)
+#define EXTI_IMR_IM19_Msk (0x1UL << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_IM20_Pos (20U)
+#define EXTI_IMR_IM20_Msk (0x1UL << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_IM21_Pos (21U)
+#define EXTI_IMR_IM21_Msk (0x1UL << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_IM22_Pos (22U)
+#define EXTI_IMR_IM22_Msk (0x1UL << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_IM23_Pos (23U)
+#define EXTI_IMR_IM23_Msk (0x1UL << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
+#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_IM25_Pos (25U)
+#define EXTI_IMR_IM25_Msk (0x1UL << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */
+#define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_IM26_Pos (26U)
+#define EXTI_IMR_IM26_Msk (0x1UL << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
+#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_IM28_Pos (28U)
+#define EXTI_IMR_IM28_Msk (0x1UL << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
+#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_IM29_Pos (29U)
+#define EXTI_IMR_IM29_Msk (0x1UL << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
+#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
+
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x36FFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x36FFFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_EM0_Pos (0U)
+#define EXTI_EMR_EM0_Msk (0x1UL << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_EM1_Pos (1U)
+#define EXTI_EMR_EM1_Msk (0x1UL << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_EM2_Pos (2U)
+#define EXTI_EMR_EM2_Msk (0x1UL << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_EM3_Pos (3U)
+#define EXTI_EMR_EM3_Msk (0x1UL << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_EM4_Pos (4U)
+#define EXTI_EMR_EM4_Msk (0x1UL << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_EM5_Pos (5U)
+#define EXTI_EMR_EM5_Msk (0x1UL << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_EM6_Pos (6U)
+#define EXTI_EMR_EM6_Msk (0x1UL << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_EM7_Pos (7U)
+#define EXTI_EMR_EM7_Msk (0x1UL << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_EM8_Pos (8U)
+#define EXTI_EMR_EM8_Msk (0x1UL << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_EM9_Pos (9U)
+#define EXTI_EMR_EM9_Msk (0x1UL << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_EM10_Pos (10U)
+#define EXTI_EMR_EM10_Msk (0x1UL << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_EM11_Pos (11U)
+#define EXTI_EMR_EM11_Msk (0x1UL << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_EM12_Pos (12U)
+#define EXTI_EMR_EM12_Msk (0x1UL << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_EM13_Pos (13U)
+#define EXTI_EMR_EM13_Msk (0x1UL << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_EM14_Pos (14U)
+#define EXTI_EMR_EM14_Msk (0x1UL << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_EM15_Pos (15U)
+#define EXTI_EMR_EM15_Msk (0x1UL << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_EM16_Pos (16U)
+#define EXTI_EMR_EM16_Msk (0x1UL << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_EM17_Pos (17U)
+#define EXTI_EMR_EM17_Msk (0x1UL << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_EM18_Pos (18U)
+#define EXTI_EMR_EM18_Msk (0x1UL << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_EM19_Pos (19U)
+#define EXTI_EMR_EM19_Msk (0x1UL << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_EM20_Pos (20U)
+#define EXTI_EMR_EM20_Msk (0x1UL << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_EM21_Pos (21U)
+#define EXTI_EMR_EM21_Msk (0x1UL << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_EM22_Pos (22U)
+#define EXTI_EMR_EM22_Msk (0x1UL << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */
+#define EXTI_EMR_EM23_Pos (23U)
+#define EXTI_EMR_EM23_Msk (0x1UL << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
+#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
+#define EXTI_EMR_EM25_Pos (25U)
+#define EXTI_EMR_EM25_Msk (0x1UL << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */
+#define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */
+#define EXTI_EMR_EM26_Pos (26U)
+#define EXTI_EMR_EM26_Msk (0x1UL << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
+#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
+#define EXTI_EMR_EM28_Pos (28U)
+#define EXTI_EMR_EM28_Msk (0x1UL << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
+#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
+#define EXTI_EMR_EM29_Pos (29U)
+#define EXTI_EMR_EM29_Msk (0x1UL << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
+#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_RT0_Pos (0U)
+#define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_RT1_Pos (1U)
+#define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_RT2_Pos (2U)
+#define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_RT3_Pos (3U)
+#define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_RT4_Pos (4U)
+#define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_RT5_Pos (5U)
+#define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_RT6_Pos (6U)
+#define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_RT7_Pos (7U)
+#define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_RT8_Pos (8U)
+#define EXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_RT9_Pos (9U)
+#define EXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_RT10_Pos (10U)
+#define EXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_RT11_Pos (11U)
+#define EXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_RT12_Pos (12U)
+#define EXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_RT13_Pos (13U)
+#define EXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_RT14_Pos (14U)
+#define EXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_RT15_Pos (15U)
+#define EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_RT16_Pos (16U)
+#define EXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_RT17_Pos (17U)
+#define EXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_RT19_Pos (19U)
+#define EXTI_RTSR_RT19_Msk (0x1UL << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_RT20_Pos (20U)
+#define EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_RT21_Pos (21U)
+#define EXTI_RTSR_RT21_Msk (0x1UL << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_RT22_Pos (22U)
+#define EXTI_RTSR_RT22_Msk (0x1UL << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
+#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
+#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
+#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
+#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
+#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
+#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
+#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
+#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
+#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
+#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
+#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
+#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
+#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
+#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
+#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
+#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
+#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
+#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
+#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
+#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
+#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_FT0_Pos (0U)
+#define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_FT1_Pos (1U)
+#define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_FT2_Pos (2U)
+#define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_FT3_Pos (3U)
+#define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_FT4_Pos (4U)
+#define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_FT5_Pos (5U)
+#define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_FT6_Pos (6U)
+#define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_FT7_Pos (7U)
+#define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_FT8_Pos (8U)
+#define EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_FT9_Pos (9U)
+#define EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_FT10_Pos (10U)
+#define EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_FT11_Pos (11U)
+#define EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_FT12_Pos (12U)
+#define EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_FT13_Pos (13U)
+#define EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_FT14_Pos (14U)
+#define EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_FT15_Pos (15U)
+#define EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_FT16_Pos (16U)
+#define EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_FT17_Pos (17U)
+#define EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_FT19_Pos (19U)
+#define EXTI_FTSR_FT19_Msk (0x1UL << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_FT20_Pos (20U)
+#define EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_FT21_Pos (21U)
+#define EXTI_FTSR_FT21_Msk (0x1UL << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_FT22_Pos (22U)
+#define EXTI_FTSR_FT22_Msk (0x1UL << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
+#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
+#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
+#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
+#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
+#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
+#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
+#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
+#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
+#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
+#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
+#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
+#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
+#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
+#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
+#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
+#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
+#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
+#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
+#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
+#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
+#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWI0_Pos (0U)
+#define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWI1_Pos (1U)
+#define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWI2_Pos (2U)
+#define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWI3_Pos (3U)
+#define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWI4_Pos (4U)
+#define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWI5_Pos (5U)
+#define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWI6_Pos (6U)
+#define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWI7_Pos (7U)
+#define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWI8_Pos (8U)
+#define EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWI9_Pos (9U)
+#define EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWI10_Pos (10U)
+#define EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWI11_Pos (11U)
+#define EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWI12_Pos (12U)
+#define EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWI13_Pos (13U)
+#define EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWI14_Pos (14U)
+#define EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWI15_Pos (15U)
+#define EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWI16_Pos (16U)
+#define EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWI17_Pos (17U)
+#define EXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWI19_Pos (19U)
+#define EXTI_SWIER_SWI19_Msk (0x1UL << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWI20_Pos (20U)
+#define EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWI21_Pos (21U)
+#define EXTI_SWIER_SWI21_Msk (0x1UL << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWI22_Pos (22U)
+#define EXTI_SWIER_SWI22_Msk (0x1UL << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
+
+/* Legacy defines */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PIF0_Pos (0U)
+#define EXTI_PR_PIF0_Msk (0x1UL << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
+#define EXTI_PR_PIF1_Pos (1U)
+#define EXTI_PR_PIF1_Msk (0x1UL << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
+#define EXTI_PR_PIF2_Pos (2U)
+#define EXTI_PR_PIF2_Msk (0x1UL << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
+#define EXTI_PR_PIF3_Pos (3U)
+#define EXTI_PR_PIF3_Msk (0x1UL << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
+#define EXTI_PR_PIF4_Pos (4U)
+#define EXTI_PR_PIF4_Msk (0x1UL << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
+#define EXTI_PR_PIF5_Pos (5U)
+#define EXTI_PR_PIF5_Msk (0x1UL << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
+#define EXTI_PR_PIF6_Pos (6U)
+#define EXTI_PR_PIF6_Msk (0x1UL << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
+#define EXTI_PR_PIF7_Pos (7U)
+#define EXTI_PR_PIF7_Msk (0x1UL << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
+#define EXTI_PR_PIF8_Pos (8U)
+#define EXTI_PR_PIF8_Msk (0x1UL << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
+#define EXTI_PR_PIF9_Pos (9U)
+#define EXTI_PR_PIF9_Msk (0x1UL << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
+#define EXTI_PR_PIF10_Pos (10U)
+#define EXTI_PR_PIF10_Msk (0x1UL << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
+#define EXTI_PR_PIF11_Pos (11U)
+#define EXTI_PR_PIF11_Msk (0x1UL << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
+#define EXTI_PR_PIF12_Pos (12U)
+#define EXTI_PR_PIF12_Msk (0x1UL << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
+#define EXTI_PR_PIF13_Pos (13U)
+#define EXTI_PR_PIF13_Msk (0x1UL << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
+#define EXTI_PR_PIF14_Pos (14U)
+#define EXTI_PR_PIF14_Msk (0x1UL << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
+#define EXTI_PR_PIF15_Pos (15U)
+#define EXTI_PR_PIF15_Msk (0x1UL << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
+#define EXTI_PR_PIF16_Pos (16U)
+#define EXTI_PR_PIF16_Msk (0x1UL << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
+#define EXTI_PR_PIF17_Pos (17U)
+#define EXTI_PR_PIF17_Msk (0x1UL << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
+#define EXTI_PR_PIF19_Pos (19U)
+#define EXTI_PR_PIF19_Msk (0x1UL << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
+#define EXTI_PR_PIF20_Pos (20U)
+#define EXTI_PR_PIF20_Msk (0x1UL << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
+#define EXTI_PR_PIF21_Pos (21U)
+#define EXTI_PR_PIF21_Msk (0x1UL << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
+#define EXTI_PR_PIF22_Pos (22U)
+#define EXTI_PR_PIF22_Msk (0x1UL << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
+
+/* Legacy defines */
+#define EXTI_PR_PR0 EXTI_PR_PIF0
+#define EXTI_PR_PR1 EXTI_PR_PIF1
+#define EXTI_PR_PR2 EXTI_PR_PIF2
+#define EXTI_PR_PR3 EXTI_PR_PIF3
+#define EXTI_PR_PR4 EXTI_PR_PIF4
+#define EXTI_PR_PR5 EXTI_PR_PIF5
+#define EXTI_PR_PR6 EXTI_PR_PIF6
+#define EXTI_PR_PR7 EXTI_PR_PIF7
+#define EXTI_PR_PR8 EXTI_PR_PIF8
+#define EXTI_PR_PR9 EXTI_PR_PIF9
+#define EXTI_PR_PR10 EXTI_PR_PIF10
+#define EXTI_PR_PR11 EXTI_PR_PIF11
+#define EXTI_PR_PR12 EXTI_PR_PIF12
+#define EXTI_PR_PR13 EXTI_PR_PIF13
+#define EXTI_PR_PR14 EXTI_PR_PIF14
+#define EXTI_PR_PR15 EXTI_PR_PIF15
+#define EXTI_PR_PR16 EXTI_PR_PIF16
+#define EXTI_PR_PR17 EXTI_PR_PIF17
+#define EXTI_PR_PR19 EXTI_PR_PIF19
+#define EXTI_PR_PR20 EXTI_PR_PIF20
+#define EXTI_PR_PR21 EXTI_PR_PIF21
+#define EXTI_PR_PR22 EXTI_PR_PIF22
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
+#define FLASH_ACR_PRFTEN_Pos (1U)
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_SLEEP_PD_Pos (3U)
+#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD_Pos (4U)
+#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
+#define FLASH_ACR_DISAB_BUF_Pos (5U)
+#define FLASH_ACR_DISAB_BUF_Msk (0x1UL << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
+#define FLASH_ACR_PRE_READ_Pos (6U)
+#define FLASH_ACR_PRE_READ_Msk (0x1UL << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
+#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
+
+/******************* Bit definition for FLASH_PECR register ******************/
+#define FLASH_PECR_PELOCK_Pos (0U)
+#define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
+#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK_Pos (1U)
+#define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
+#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK_Pos (2U)
+#define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
+#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG_Pos (3U)
+#define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
+#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
+#define FLASH_PECR_DATA_Pos (4U)
+#define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
+#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
+#define FLASH_PECR_FIX_Pos (8U)
+#define FLASH_PECR_FIX_Msk (0x1UL << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
+#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE_Pos (9U)
+#define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
+#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
+#define FLASH_PECR_FPRG_Pos (10U)
+#define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
+#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_EOPIE_Pos (16U)
+#define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
+#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
+#define FLASH_PECR_ERRIE_Pos (17U)
+#define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
+#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
+#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
+#define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
+#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
+#define FLASH_PECR_HALF_ARRAY_Pos (19U)
+#define FLASH_PECR_HALF_ARRAY_Msk (0x1UL << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
+#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
+
+/****************** Bit definition for FLASH_PDKEYR register ******************/
+#define FLASH_PDKEYR_PDKEYR_Pos (0U)
+#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PEKEYR register ******************/
+#define FLASH_PEKEYR_PEKEYR_Pos (0U)
+#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PRGKEYR register ******************/
+#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
+#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
+
+/****************** Bit definition for FLASH_OPTKEYR register ******************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_EOP_Pos (1U)
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
+#define FLASH_SR_HVOFF_Pos (2U)
+#define FLASH_SR_HVOFF_Msk (0x1UL << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
+#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
+#define FLASH_SR_READY_Pos (3U)
+#define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */
+#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR_Pos (8U)
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
+#define FLASH_SR_PGAERR_Pos (9U)
+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR_Pos (10U)
+#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
+#define FLASH_SR_OPTVERR_Pos (11U)
+#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
+#define FLASH_SR_RDERR_Pos (13U)
+#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
+#define FLASH_SR_NOTZEROERR_Pos (16U)
+#define FLASH_SR_NOTZEROERR_Msk (0x1UL << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
+#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
+#define FLASH_SR_FWWERR_Pos (17U)
+#define FLASH_SR_FWWERR_Msk (0x1UL << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
+#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
+
+/* Legacy defines */
+#define FLASH_SR_FWWER FLASH_SR_FWWERR
+#define FLASH_SR_ENHV FLASH_SR_HVOFF
+#define FLASH_SR_ENDHV FLASH_SR_HVOFF
+
+/****************** Bit definition for FLASH_OPTR register *******************/
+#define FLASH_OPTR_RDPROT_Pos (0U)
+#define FLASH_OPTR_RDPROT_Msk (0xFFUL << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
+#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
+#define FLASH_OPTR_WPRMOD_Pos (8U)
+#define FLASH_OPTR_WPRMOD_Msk (0x1UL << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
+#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
+#define FLASH_OPTR_BOR_LEV_Pos (16U)
+#define FLASH_OPTR_BOR_LEV_Msk (0xFUL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
+#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OPTR_IWDG_SW_Pos (20U)
+#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
+#define FLASH_OPTR_nRST_STOP_Pos (21U)
+#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OPTR_nRST_STDBY_Pos (22U)
+#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OPTR_USER_Pos (20U)
+#define FLASH_OPTR_USER_Msk (0x7UL << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
+#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OPTR_BOOT1_Pos (31U)
+#define FLASH_OPTR_BOOT1_Msk (0x1UL << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
+#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 (0x00000001U)
+#define GPIO_OTYPER_OT_1 (0x00000002U)
+#define GPIO_OTYPER_OT_2 (0x00000004U)
+#define GPIO_OTYPER_OT_3 (0x00000008U)
+#define GPIO_OTYPER_OT_4 (0x00000010U)
+#define GPIO_OTYPER_OT_5 (0x00000020U)
+#define GPIO_OTYPER_OT_6 (0x00000040U)
+#define GPIO_OTYPER_OT_7 (0x00000080U)
+#define GPIO_OTYPER_OT_8 (0x00000100U)
+#define GPIO_OTYPER_OT_9 (0x00000200U)
+#define GPIO_OTYPER_OT_10 (0x00000400U)
+#define GPIO_OTYPER_OT_11 (0x00000800U)
+#define GPIO_OTYPER_OT_12 (0x00001000U)
+#define GPIO_OTYPER_OT_13 (0x00002000U)
+#define GPIO_OTYPER_OT_14 (0x00004000U)
+#define GPIO_OTYPER_OT_15 (0x00008000U)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDER_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
+#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDER_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
+#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDER_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
+#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDER_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
+#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDER_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
+#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDER_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
+#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDER_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
+#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDER_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
+#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDER_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
+#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDER_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
+#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDER_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
+#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDER_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
+#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDER_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
+#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDER_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
+#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDER_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
+#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDER_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
+#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 (0x00000001U)
+#define GPIO_BSRR_BS_1 (0x00000002U)
+#define GPIO_BSRR_BS_2 (0x00000004U)
+#define GPIO_BSRR_BS_3 (0x00000008U)
+#define GPIO_BSRR_BS_4 (0x00000010U)
+#define GPIO_BSRR_BS_5 (0x00000020U)
+#define GPIO_BSRR_BS_6 (0x00000040U)
+#define GPIO_BSRR_BS_7 (0x00000080U)
+#define GPIO_BSRR_BS_8 (0x00000100U)
+#define GPIO_BSRR_BS_9 (0x00000200U)
+#define GPIO_BSRR_BS_10 (0x00000400U)
+#define GPIO_BSRR_BS_11 (0x00000800U)
+#define GPIO_BSRR_BS_12 (0x00001000U)
+#define GPIO_BSRR_BS_13 (0x00002000U)
+#define GPIO_BSRR_BS_14 (0x00004000U)
+#define GPIO_BSRR_BS_15 (0x00008000U)
+#define GPIO_BSRR_BR_0 (0x00010000U)
+#define GPIO_BSRR_BR_1 (0x00020000U)
+#define GPIO_BSRR_BR_2 (0x00040000U)
+#define GPIO_BSRR_BR_3 (0x00080000U)
+#define GPIO_BSRR_BR_4 (0x00100000U)
+#define GPIO_BSRR_BR_5 (0x00200000U)
+#define GPIO_BSRR_BR_6 (0x00400000U)
+#define GPIO_BSRR_BR_7 (0x00800000U)
+#define GPIO_BSRR_BR_8 (0x01000000U)
+#define GPIO_BSRR_BR_9 (0x02000000U)
+#define GPIO_BSRR_BR_10 (0x04000000U)
+#define GPIO_BSRR_BR_11 (0x08000000U)
+#define GPIO_BSRR_BR_12 (0x10000000U)
+#define GPIO_BSRR_BR_13 (0x20000000U)
+#define GPIO_BSRR_BR_14 (0x40000000U)
+#define GPIO_BSRR_BR_15 (0x80000000U)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 (0x00000001U)
+#define GPIO_BRR_BR_1 (0x00000002U)
+#define GPIO_BRR_BR_2 (0x00000004U)
+#define GPIO_BRR_BR_3 (0x00000008U)
+#define GPIO_BRR_BR_4 (0x00000010U)
+#define GPIO_BRR_BR_5 (0x00000020U)
+#define GPIO_BRR_BR_6 (0x00000040U)
+#define GPIO_BRR_BR_7 (0x00000080U)
+#define GPIO_BRR_BR_8 (0x00000100U)
+#define GPIO_BRR_BR_9 (0x00000200U)
+#define GPIO_BRR_BR_10 (0x00000400U)
+#define GPIO_BRR_BR_11 (0x00000800U)
+#define GPIO_BRR_BR_12 (0x00001000U)
+#define GPIO_BRR_BR_13 (0x00002000U)
+#define GPIO_BRR_BR_14 (0x00004000U)
+#define GPIO_BRR_BR_15 (0x00008000U)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos (1U)
+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos (2U)
+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos (3U)
+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos (4U)
+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos (5U)
+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos (6U)
+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos (7U)
+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos (8U)
+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos (12U)
+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos (14U)
+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos (15U)
+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos (16U)
+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos (17U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos (18U)
+#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos (19U)
+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos (20U)
+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos (21U)
+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos (22U)
+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos (23U)
+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD_Pos (0U)
+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos (10U)
+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos (11U)
+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos (12U)
+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos (13U)
+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
+#define I2C_CR2_STOP_Pos (14U)
+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos (15U)
+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos (16U)
+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos (24U)
+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos (25U)
+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos (26U)
+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1_Pos (0U)
+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos (10U)
+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos (15U)
+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2_Pos (1U)
+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos (8U)
+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos (8U)
+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos (9U)
+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos (8U)
+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos (10U)
+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos (8U)
+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos (9U)
+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos (8U)
+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos (15U)
+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos (0U)
+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos (8U)
+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos (16U)
+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos (20U)
+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos (28U)
+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE_Pos (0U)
+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos (1U)
+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos (2U)
+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos (3U)
+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos (4U)
+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos (5U)
+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos (6U)
+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos (7U)
+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos (8U)
+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
+#define I2C_ISR_ARLO_Pos (9U)
+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos (10U)
+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos (11U)
+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos (12U)
+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos (13U)
+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos (15U)
+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
+#define I2C_ISR_DIR_Pos (16U)
+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos (17U)
+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF_Pos (3U)
+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos (4U)
+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos (5U)
+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos (8U)
+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos (9U)
+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos (10U)
+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos (11U)
+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos (12U)
+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos (13U)
+#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define I2C_PECR_PEC_Pos (0U)
+#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA_Pos (0U)
+#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA_Pos (0U)
+#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos (2U)
+#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN_Pos (0U)
+#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM_Pos (0U)
+#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos (1U)
+#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos (2U)
+#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos (3U)
+#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos (4U)
+#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos (5U)
+#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos (6U)
+#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF_Pos (0U)
+#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos (1U)
+#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos (3U)
+#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos (4U)
+#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos (5U)
+#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos (6U)
+#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos (0U)
+#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos (1U)
+#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos (3U)
+#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos (4U)
+#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos (5U)
+#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos (6U)
+#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos (0U)
+#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos (1U)
+#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos (3U)
+#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos (6U)
+#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos (9U)
+#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos (17U)
+#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos (19U)
+#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos (20U)
+#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos (21U)
+#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos (22U)
+#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos (24U)
+#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE_Pos (0U)
+#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos (1U)
+#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos (2U)
+#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP_Pos (0U)
+#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR_Pos (0U)
+#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT_Pos (0U)
+#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
+
+/******************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/******************************************************************************/
+
+#define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPSDSR_Pos (0U)
+#define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP_Pos (9U)
+#define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /*!< 0x00000200 */
+#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
+#define PWR_CR_FWU_Pos (10U)
+#define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /*!< 0x00000400 */
+#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
+
+#define PWR_CR_VOS_Pos (11U)
+#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x00001800 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /*!< 0x00000800 */
+#define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /*!< 0x00001000 */
+#define PWR_CR_DSEEKOFF_Pos (13U)
+#define PWR_CR_DSEEKOFF_Msk (0x1UL << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */
+#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */
+#define PWR_CR_LPRUN_Pos (14U)
+#define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
+#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
+#define PWR_CR_LPDS_Pos (16U)
+#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00010000 */
+#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< regulator in low power deepsleep mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF_Pos (3U)
+#define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
+#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF_Pos (4U)
+#define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
+#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF_Pos (5U)
+#define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
+#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1_Pos (8U)
+#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP3_Pos (10U)
+#define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
+#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos (1U)
+#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos (2U)
+#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIVEN_Pos (3U)
+#define RCC_CR_HSIDIVEN_Msk (0x1UL << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */
+#define RCC_CR_HSIDIVF_Pos (4U)
+#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */
+#define RCC_CR_HSIOUTEN_Pos (5U)
+#define RCC_CR_HSIOUTEN_Msk (0x1UL << RCC_CR_HSIOUTEN_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_Msk /*!< Internal High Speed clock out enable */
+#define RCC_CR_MSION_Pos (8U)
+#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000100 */
+#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY_Pos (9U)
+#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
+#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_RTCPRE_Pos (20U)
+#define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
+#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */
+#define RCC_CR_RTCPRE_0 (0x1UL << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */
+#define RCC_CR_RTCPRE_1 (0x2UL << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+/* Reference defines */
+
+/******************** Bit definition for RCC_ICSCR register *****************/
+#define RCC_ICSCR_HSICAL_Pos (0U)
+#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
+#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM_Pos (8U)
+#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
+#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE_Pos (13U)
+#define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
+#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
+#define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
+#define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
+#define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
+#define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
+#define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
+#define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
+#define RCC_ICSCR_MSICAL_Pos (16U)
+#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
+#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM_Pos (24U)
+#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
+#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos (15U)
+#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */
+
+/*!< PLL entry clock source*/
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
+
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL_Pos (18U)
+#define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV_Pos (22U)
+#define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
+
+#define RCC_CFGR_PLLDIV2_Pos (22U)
+#define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3_Pos (23U)
+#define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4_Pos (22U)
+#define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCOSEL_Pos (24U)
+#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
+#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
+
+#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
+#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCOSEL_HSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_MSI_Pos (24U)
+#define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
+#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_HSE_Pos (26U)
+#define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCOSEL_PLL_Pos (24U)
+#define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
+#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
+#define RCC_CFGR_MCOSEL_LSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
+#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
+#define RCC_CFGR_MCOSEL_LSE_Pos (24U)
+#define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
+
+#define RCC_CFGR_MCOPRE_Pos (28U)
+#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
+
+#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
+
+/* Legacy defines */
+#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
+#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
+#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
+#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
+#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
+#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
+#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
+#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
+#ifdef RCC_CFGR_MCOSEL_HSI48
+#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48
+#endif
+
+#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
+#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
+
+/*!<****************** Bit definition for RCC_CIER register ********************/
+#define RCC_CIER_LSIRDYIE_Pos (0U)
+#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIER_LSERDYIE_Pos (1U)
+#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIER_HSIRDYIE_Pos (2U)
+#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIER_HSERDYIE_Pos (3U)
+#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIER_PLLRDYIE_Pos (4U)
+#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIER_MSIRDYIE_Pos (5U)
+#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
+#define RCC_CIER_CSSLSE_Pos (7U)
+#define RCC_CIER_CSSLSE_Msk (0x1UL << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */
+
+/* Reference defines */
+#define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
+
+/*!<****************** Bit definition for RCC_CIFR register ********************/
+#define RCC_CIFR_LSIRDYF_Pos (0U)
+#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIFR_LSERDYF_Pos (1U)
+#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIFR_HSIRDYF_Pos (2U)
+#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIFR_HSERDYF_Pos (3U)
+#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIFR_PLLRDYF_Pos (4U)
+#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIFR_MSIRDYF_Pos (5U)
+#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
+#define RCC_CIFR_CSSLSEF_Pos (7U)
+#define RCC_CIFR_CSSLSEF_Msk (0x1UL << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */
+
+/* Reference defines */
+#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
+
+/*!<****************** Bit definition for RCC_CICR register ********************/
+#define RCC_CICR_LSIRDYC_Pos (0U)
+#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CICR_LSERDYC_Pos (1U)
+#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CICR_HSIRDYC_Pos (2U)
+#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CICR_HSERDYC_Pos (3U)
+#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CICR_PLLRDYC_Pos (4U)
+#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CICR_MSIRDYC_Pos (5U)
+#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
+#define RCC_CICR_CSSLSEC_Pos (7U)
+#define RCC_CICR_CSSLSEC_Msk (0x1UL << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */
+
+/* Reference defines */
+#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
+/***************** Bit definition for RCC_IOPRSTR register ******************/
+#define RCC_IOPRSTR_IOPARST_Pos (0U)
+#define RCC_IOPRSTR_IOPARST_Msk (0x1UL << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */
+#define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */
+#define RCC_IOPRSTR_IOPBRST_Pos (1U)
+#define RCC_IOPRSTR_IOPBRST_Msk (0x1UL << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */
+#define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */
+#define RCC_IOPRSTR_IOPCRST_Pos (2U)
+#define RCC_IOPRSTR_IOPCRST_Msk (0x1UL << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */
+#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */
+
+/* Reference defines */
+#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
+#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
+#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
+
+
+/****************** Bit definition for RCC_AHBRST register ******************/
+#define RCC_AHBRSTR_DMARST_Pos (0U)
+#define RCC_AHBRSTR_DMARST_Msk (0x1UL << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */
+#define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */
+#define RCC_AHBRSTR_MIFRST_Pos (8U)
+#define RCC_AHBRSTR_MIFRST_Msk (0x1UL << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */
+#define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset */
+#define RCC_AHBRSTR_CRCRST_Pos (12U)
+#define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */
+#define RCC_AHBRSTR_CRYPRST_Pos (24U)
+#define RCC_AHBRSTR_CRYPRST_Msk (0x1UL << RCC_AHBRSTR_CRYPRST_Pos) /*!< 0x01000000 */
+#define RCC_AHBRSTR_CRYPRST RCC_AHBRSTR_CRYPRST_Msk /*!< Crypto reset */
+
+/* Reference defines */
+#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
+#define RCC_APB2RSTR_TIM21RST_Pos (2U)
+#define RCC_APB2RSTR_TIM21RST_Msk (0x1UL << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 reset */
+#define RCC_APB2RSTR_ADCRST_Pos (9U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
+#define RCC_APB2RSTR_DBGRST_Pos (22U)
+#define RCC_APB2RSTR_DBGRST_Msk (0x1UL << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU reset */
+
+/* Reference defines */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 reset */
+#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU reset */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_LPUART1RST_Pos (18U)
+#define RCC_APB1RSTR_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
+#define RCC_APB1RSTR_LPTIM1RST_Pos (31U)
+#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 reset */
+
+/***************** Bit definition for RCC_IOPENR register ******************/
+#define RCC_IOPENR_IOPAEN_Pos (0U)
+#define RCC_IOPENR_IOPAEN_Msk (0x1UL << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */
+#define RCC_IOPENR_IOPBEN_Pos (1U)
+#define RCC_IOPENR_IOPBEN_Msk (0x1UL << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */
+#define RCC_IOPENR_IOPCEN_Pos (2U)
+#define RCC_IOPENR_IOPCEN_Msk (0x1UL << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */
+
+/* Reference defines */
+#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
+#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
+#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
+
+/***************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMAEN_Pos (0U)
+#define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_MIFEN_Pos (8U)
+#define RCC_AHBENR_MIFEN_Msk (0x1UL << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */
+#define RCC_AHBENR_CRCEN_Pos (12U)
+#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+#define RCC_AHBENR_CRYPEN_Pos (24U)
+#define RCC_AHBENR_CRYPEN_Msk (0x1UL << RCC_AHBENR_CRYPEN_Pos) /*!< 0x01000000 */
+#define RCC_AHBENR_CRYPEN RCC_AHBENR_CRYPEN_Msk /*!< Crypto clock enable*/
+
+/* Reference defines */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register ******************/
+#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM21EN_Pos (2U)
+#define RCC_APB2ENR_TIM21EN_Msk (0x1UL << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */
+#define RCC_APB2ENR_FWEN_Pos (7U)
+#define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADCEN_Pos (9U)
+#define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
+#define RCC_APB2ENR_DBGEN_Pos (22U)
+#define RCC_APB2ENR_DBGEN_Msk (0x1UL << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */
+
+/* Reference defines */
+
+#define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
+#define RCC_APB1ENR_LPUART1EN_Pos (18U)
+#define RCC_APB1ENR_LPUART1EN_Msk (0x1UL << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
+#define RCC_APB1ENR_LPTIM1EN_Pos (31U)
+#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */
+
+/****************** Bit definition for RCC_IOPSMENR register ****************/
+#define RCC_IOPSMENR_IOPASMEN_Pos (0U)
+#define RCC_IOPSMENR_IOPASMEN_Msk (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPBSMEN_Pos (1U)
+#define RCC_IOPSMENR_IOPBSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPCSMEN_Pos (2U)
+#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_AHBSMENR register ******************/
+#define RCC_AHBSMENR_DMASMEN_Pos (0U)
+#define RCC_AHBSMENR_DMASMEN_Msk (0x1UL << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */
+#define RCC_AHBSMENR_MIFSMEN_Pos (8U)
+#define RCC_AHBSMENR_MIFSMEN_Msk (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */
+#define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
+#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRCSMEN_Pos (12U)
+#define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRYPSMEN_Pos (24U)
+#define RCC_AHBSMENR_CRYPSMEN_Msk (0x1UL << RCC_AHBSMENR_CRYPSMEN_Pos) /*!< 0x01000000 */
+#define RCC_AHBSMENR_CRYPSMEN RCC_AHBSMENR_CRYPSMEN_Msk /*!< Crypto clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB2SMENR register ******************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM21SMEN_Pos (2U)
+#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */
+#define RCC_APB2SMENR_ADCSMEN_Pos (9U)
+#define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
+#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGSMEN_Pos (22U)
+#define RCC_APB2SMENR_DBGSMEN_Msk (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB1SMENR register ******************/
+#define RCC_APB1SMENR_TIM2SMEN_Pos (0U)
+#define RCC_APB1SMENR_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_WWDGSMEN_Pos (11U)
+#define RCC_APB1SMENR_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART2SMEN_Pos (17U)
+#define RCC_APB1SMENR_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPUART1SMEN_Pos (18U)
+#define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C1SMEN_Pos (21U)
+#define RCC_APB1SMENR_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_PWRSMEN_Pos (28U)
+#define RCC_APB1SMENR_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U)
+#define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */
+
+/*!< USART2 Clock source selection */
+#define RCC_CCIPR_USART2SEL_Pos (2U)
+#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */
+#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+/*!< LPUART1 Clock source selection */
+#define RCC_CCIPR_LPUART1SEL_Pos (10U)
+#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */
+#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */
+#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CCIPR_I2C1SEL_Pos (12U)
+#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */
+#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
+
+
+/*!< LPTIM1 Clock source selection */
+#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
+#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */
+#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+/******************* Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSEON_Pos (8U)
+#define RCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */
+#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_CSR_LSERDY_Pos (9U)
+#define RCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */
+#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP_Pos (10U)
+#define RCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */
+#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_CSR_LSEDRV_Pos (11U)
+#define RCC_CSR_LSEDRV_Msk (0x3UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */
+#define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_CSR_LSEDRV_0 (0x1UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */
+#define RCC_CSR_LSEDRV_1 (0x2UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */
+
+#define RCC_CSR_LSECSSON_Pos (13U)
+#define RCC_CSR_LSECSSON_Msk (0x1UL << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */
+#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */
+#define RCC_CSR_LSECSSD_Pos (14U)
+#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
+#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
+
+/*!< RTC congiguration */
+#define RCC_CSR_RTCSEL_Pos (16U)
+#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
+
+#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CSR_RTCSEL_LSE_Pos (16U)
+#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_LSI_Pos (17U)
+#define RCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */
+#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_HSE_Pos (16U)
+#define RCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */
+
+#define RCC_CSR_RTCEN_Pos (18U)
+#define RCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */
+#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_CSR_RTCRST_Pos (19U)
+#define RCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */
+#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */
+
+#define RCC_CSR_RMVF_Pos (23U)
+#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_OBLRSTF_Pos (25U)
+#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+/* Reference defines */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER2_SUPPORT
+#define RTC_TAMPER3_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk /*!< */
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk /*!< */
+#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk /*!< */
+#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */
+#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */
+#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk /*!< */
+#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk /*!< */
+#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk /*!< */
+#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk /*!< */
+#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */
+#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk /*!< */
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk /*!< */
+#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk /*!< */
+#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk /*!< */
+#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk /*!< */
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */
+#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk /*!< */
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< */
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */
+#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */
+#define RTC_ISR_TAMP3F_Pos (15U)
+#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk /*!< */
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */
+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */
+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */
+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */
+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */
+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */
+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */
+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */
+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */
+#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */
+#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */
+#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */
+#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */
+#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */
+#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */
+#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */
+#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */
+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */
+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */
+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */
+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */
+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */
+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */
+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */
+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */
+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */
+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CALR register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */
+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define RTC_CAL_CALP RTC_CALR_CALP
+#define RTC_CAL_CALW8 RTC_CALR_CALW8
+#define RTC_CAL_CALW16 RTC_CALR_CALW16
+#define RTC_CAL_CALM RTC_CALR_CALM
+#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
+
+/******************** Bits definition for RTC_TAMPCR register ****************/
+#define RTC_TAMPCR_TAMP3MF_Pos (24U)
+#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
+#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
+#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
+#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP3IE_Pos (22U)
+#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
+#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2MF_Pos (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2IE_Pos (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */
+#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */
+#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */
+#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos (7U)
+#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */
+#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
+#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
+#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP3E_Pos (5U)
+#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
+#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk /*!< */
+#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP2E_Pos (3U)
+#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */
+#define RTC_TAMPCR_TAMPIE_Pos (2U)
+#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_OR register ****************/
+#define RTC_OR_OUT_RMP_Pos (1U)
+#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */
+#define RTC_OR_ALARMOUTTYPE_Pos (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */
+
+/* Legacy defines */
+#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk /*!< */
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER (0x00000005U) /*!< */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/******************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
+#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR1_BOOT_MODE_Pos (8U)
+#define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
+#define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */
+#define SYSCFG_CFGR1_BOOT_MODE_0 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOT_MODE_1 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_FWDISEN_Pos (0U)
+#define SYSCFG_CFGR2_FWDISEN_Msk (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos (8U)
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR2_I2C_PB6_FMP SYSCFG_CFGR2_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos (9U)
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR2_I2C_PB7_FMP SYSCFG_CFGR2_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos (10U)
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
+#define SYSCFG_CFGR2_I2C_PB8_FMP SYSCFG_CFGR2_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos (11U)
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
+#define SYSCFG_CFGR2_I2C_PB9_FMP SYSCFG_CFGR2_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR2_I2C1_FMP_Pos (12U)
+#define SYSCFG_CFGR2_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR2_I2C1_FMP SYSCFG_CFGR2_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
+
+
+/***************** Bit definition for SYSCFG_CFGR3 register ****************/
+#define SYSCFG_CFGR3_EN_VREFINT_Pos (0U)
+#define SYSCFG_CFGR3_EN_VREFINT_Msk (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_EN_VREFINT SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
+#define SYSCFG_CFGR3_VREF_OUT_Pos (4U)
+#define SYSCFG_CFGR3_VREF_OUT_Msk (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
+#define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */
+#define SYSCFG_CFGR3_VREF_OUT_0 (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
+#define SYSCFG_CFGR3_VREF_OUT_1 (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U)
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U)
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U)
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
+#define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U)
+#define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
+#define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
+#define SYSCFG_CFGR3_REF_LOCK_Pos (31U)
+#define SYSCFG_CFGR3_REF_LOCK_Msk (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
+#define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */
+
+/* Legacy defines */
+
+#define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
+#define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
+#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
+#define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+
+/******************************************************************************/
+/* */
+/* Timers (TIM)*/
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
+#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
+ || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#else
+#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
+#endif
+
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFUL << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFUL << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM2_OR_ETR_RMP_Pos (0U)
+#define TIM2_OR_ETR_RMP_Msk (0x7UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000007 */
+#define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
+#define TIM2_OR_ETR_RMP_0 (0x1UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM2_OR_ETR_RMP_1 (0x2UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM2_OR_ETR_RMP_2 (0x4UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000004 */
+#define TIM2_OR_TI4_RMP_Pos (3U)
+#define TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000018 */
+#define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
+#define TIM2_OR_TI4_RMP_0 (0x1UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */
+#define TIM2_OR_TI4_RMP_1 (0x2UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000010 */
+
+#define TIM21_OR_ETR_RMP_Pos (0U)
+#define TIM21_OR_ETR_RMP_Msk (0x3UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
+#define TIM21_OR_ETR_RMP_0 (0x1UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM21_OR_ETR_RMP_1 (0x2UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM21_OR_TI1_RMP_Pos (2U)
+#define TIM21_OR_TI1_RMP_Msk (0x7UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x0000001C */
+#define TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
+#define TIM21_OR_TI1_RMP_0 (0x1UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM21_OR_TI1_RMP_1 (0x2UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+#define TIM21_OR_TI1_RMP_2 (0x4UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000010 */
+#define TIM21_OR_TI2_RMP_Pos (5U)
+#define TIM21_OR_TI2_RMP_Msk (0x1UL << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */
+#define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+#define USART_TCBGT_SUPPORT /*!< Transmission completed before guard time interrupt support */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE_Pos (0U)
+#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+#define USART_CR1_UESM_Pos (1U)
+#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
+#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_M0_Pos (12U)
+#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
+#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos (13U)
+#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos (14U)
+#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos (16U)
+#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
+#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
+#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
+#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
+#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos (21U)
+#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
+#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
+#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
+#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
+#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos (26U)
+#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos (27U)
+#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos (28U)
+#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
+#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7_Pos (4U)
+#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos (15U)
+#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos (16U)
+#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos (17U)
+#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos (18U)
+#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos (19U)
+#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos (20U)
+#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos (21U)
+#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos (23U)
+#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos (24U)
+#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos (12U)
+#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos (13U)
+#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos (14U)
+#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos (15U)
+#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos (17U)
+#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos (20U)
+#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
+#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
+#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos (22U)
+#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
+#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
+#define USART_CR3_UCESM_Pos (23U)
+#define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
+#define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
+#define USART_CR3_TCBGTIE_Pos (24U)
+#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
+#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION_Pos (0U)
+#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos (4U)
+#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO_Pos (0U)
+#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos (24U)
+#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ_Pos (0U)
+#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
+#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos (1U)
+#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
+#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos (2U)
+#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
+#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos (3U)
+#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
+#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos (4U)
+#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
+#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE_Pos (0U)
+#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
+#define USART_ISR_FE_Pos (1U)
+#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
+#define USART_ISR_NE_Pos (2U)
+#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos (3U)
+#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos (4U)
+#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos (5U)
+#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos (6U)
+#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos (7U)
+#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
+#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos (8U)
+#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos (9U)
+#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos (10U)
+#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
+#define USART_ISR_RTOF_Pos (11U)
+#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos (12U)
+#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos (14U)
+#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos (15U)
+#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos (16U)
+#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
+#define USART_ISR_CMF_Pos (17U)
+#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos (18U)
+#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos (19U)
+#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos (20U)
+#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
+#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos (21U)
+#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos (22U)
+#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
+#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
+#define USART_ISR_TCBGT_Pos (25U)
+#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
+#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time Completion Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF_Pos (0U)
+#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos (1U)
+#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos (2U)
+#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */
+#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos (3U)
+#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos (4U)
+#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos (6U)
+#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
+#define USART_ICR_TCBGTCF_Pos (7U)
+#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
+#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
+#define USART_ICR_LBDCF_Pos (8U)
+#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos (9U)
+#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos (11U)
+#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos (12U)
+#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos (17U)
+#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos (20U)
+#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
+#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
+
+/* Compatibility defines with other series */
+#define USART_ICR_NECF USART_ICR_NCF
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR_Pos (0U)
+#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR_Pos (0U)
+#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+/******************************* AES Instances ********************************/
+#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
+
+/******************************* COMP Instances *******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+ ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
+
+
+
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SMBUS Instances *****************************/
+#define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/************* LPTIM instances supporting the encoder mode feature ************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM21) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/******************* TIM Instances : output(s) OCXEC register *****************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (1 == 0)
+
+/****************** USART Instances : Auto Baud Rate detection ****************/
+
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (1 == 0)
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (1==0)
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32L0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32L0 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+
+#define RNG_LPUART1_IRQn AES_LPUART1_IRQn
+#define LPUART1_IRQn AES_LPUART1_IRQn
+#define AES_RNG_LPUART1_IRQn AES_LPUART1_IRQn
+#define RCC_CRS_IRQn RCC_IRQn
+#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
+#define ADC1_IRQn ADC1_COMP_IRQn
+
+/* Aliases for __IRQHandler */
+#define LPUART1_IRQHandler AES_LPUART1_IRQHandler
+#define RNG_LPUART1_IRQHandler AES_LPUART1_IRQHandler
+#define AES_RNG_LPUART1_IRQHandler AES_LPUART1_IRQHandler
+#define RCC_CRS_IRQHandler RCC_IRQHandler
+#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
+#define ADC1_IRQHandler ADC1_COMP_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L021xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/CMSIS/device/stm32l031xx.h b/CMSIS/device/stm32l031xx.h
new file mode 100644
index 0000000..2f1c9e6
--- /dev/null
+++ b/CMSIS/device/stm32l031xx.h
@@ -0,0 +1,6090 @@
+/**
+ ******************************************************************************
+ * @file stm32l031xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for stm32l031xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright(c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l031xx
+ * @{
+ */
+
+#ifndef __STM32L031xx_H
+#define __STM32L031xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 0U /*!< STM32L0xx provides no MPU */
+#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
+#define __NVIC_PRIO_BITS 2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief stm32l031xx Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+/*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
+
+/****** STM32L-0 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */
+ RCC_IRQn = 4, /*!< RCC Interrupt */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
+ ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
+ LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 Interrupt */
+ TIM21_IRQn = 20, /*!< TIM21 Interrupt */
+ TIM22_IRQn = 22, /*!< TIM22 Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ USART2_IRQn = 28, /*!< USART2 Interrupt */
+ LPUART1_IRQn = 29, /*!< LPUART1 Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0plus.h"
+#include "system_stm32l0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+ uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Comparator
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
+} COMP_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+
+/**
+* @brief CRC calculation unit
+*/
+
+typedef struct
+{
+__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+uint8_t RESERVED0; /*!< Reserved, 0x05 */
+uint16_t RESERVED1; /*!< Reserved, 0x06 */
+__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+uint32_t RESERVED2; /*!< Reserved, 0x0C */
+__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
+} DMA_Request_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
+ __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
+ __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
+ __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
+ __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
+ __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
+ __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
+ __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
+ __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
+ __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
+} OB_TypeDef;
+
+
+/**
+ * @brief General Purpose IO
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief LPTIMIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+} LPTIM_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+ * @brief Independent WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
+ __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
+ __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
+ __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
+ __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
+ __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
+ __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
+ __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
+ __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
+ __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
+ __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */
+
+#define DATA_EEPROM_BASE (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
+#define DATA_EEPROM_END (0x080803FFUL) /*!< DATA EEPROM end address in the alias region */
+#define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */
+#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8KBytes) */
+
+#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000UL)
+
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
+#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800UL)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
+#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL)
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
+#define COMP1_BASE (APBPERIPH_BASE + 0x00010018UL)
+#define COMP2_BASE (APBPERIPH_BASE + 0x0001001CUL)
+#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL)
+#define TIM21_BASE (APBPERIPH_BASE + 0x00010800UL)
+#define TIM22_BASE (APBPERIPH_BASE + 0x00011400UL)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708UL)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
+#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL)
+
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
+#define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */
+#define FLASHSIZE_BASE (0x1FF8007CUL) /*!< FLASH Size register base address */
+#define UID_BASE (0x1FF80050UL) /*!< Unique device ID register base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
+
+#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL)
+#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL)
+#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL)
+#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00UL)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
+#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
+/* Legacy defines */
+#define ADC ADC1_COMMON
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_EOCAL_Pos (11U)
+#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
+#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
+#define ADC_ISR_AWD_Pos (7U)
+#define ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
+#define ADC_ISR_EOSEQ_Pos (3U)
+#define ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_EOCALIE_Pos (11U)
+#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
+#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
+#define ADC_IER_AWDIE_Pos (7U)
+#define ADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE_Pos (3U)
+#define ADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH_Pos (26U)
+#define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
+#define ADC_CFGR1_AWDEN_Pos (23U)
+#define ADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL_Pos (22U)
+#define ADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN_Pos (16U)
+#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF_Pos (15U)
+#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
+#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT_Pos (14U)
+#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
+#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT_Pos (13U)
+#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD_Pos (12U)
+#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN_Pos (10U)
+#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
+#define ADC_CFGR1_EXTSEL_Pos (6U)
+#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
+#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
+#define ADC_CFGR1_ALIGN_Pos (5U)
+#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
+#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
+#define ADC_CFGR1_RES_Pos (3U)
+#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
+#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
+#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
+#define ADC_CFGR1_SCANDIR_Pos (2U)
+#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG_Pos (1U)
+#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
+#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN_Pos (0U)
+#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
+#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_TOVS_Pos (9U)
+#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
+#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+#define ADC_CFGR2_OVSR_Pos (2U)
+#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
+#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+#define ADC_CFGR2_OVSE_Pos (0U)
+#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
+#define ADC_CFGR2_CKMODE_Pos (30U)
+#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
+#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
+#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
+#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
+
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP_Pos (0U)
+#define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
+#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
+#define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
+#define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define ADC_SMPR_SMPR ADC_SMPR_SMP
+#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
+#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
+#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT_Pos (16U)
+#define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
+#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
+#define ADC_TR_LT_Pos (0U)
+#define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL_Pos (0U)
+#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
+#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
+#define ADC_CHSELR_CHSEL18_Pos (18U)
+#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17_Pos (17U)
+#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
+#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL15_Pos (15U)
+#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
+#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14_Pos (14U)
+#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
+#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13_Pos (13U)
+#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
+#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12_Pos (12U)
+#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
+#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11_Pos (11U)
+#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
+#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10_Pos (10U)
+#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
+#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9_Pos (9U)
+#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
+#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8_Pos (8U)
+#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
+#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7_Pos (7U)
+#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
+#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6_Pos (6U)
+#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
+#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5_Pos (5U)
+#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
+#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4_Pos (4U)
+#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
+#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3_Pos (3U)
+#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
+#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2_Pos (2U)
+#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
+#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1_Pos (1U)
+#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
+#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0_Pos (0U)
+#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
+#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_CALFACT_Pos (0U)
+#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_LFMEN_Pos (25U)
+#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
+#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
+#define ADC_CCR_TSEN_Pos (23U)
+#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+/************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN_Pos (0U)
+#define COMP_CSR_COMP1EN_Msk (0x1UL << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
+#define COMP_CSR_COMP1INNSEL_Pos (4U)
+#define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
+#define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP1WM_Pos (8U)
+#define COMP_CSR_COMP1WM_Msk (0x1UL << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */
+#define COMP_CSR_COMP1LPTIM1IN1_Pos (12U)
+#define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP1POLARITY_Pos (15U)
+#define COMP_CSR_COMP1POLARITY_Msk (0x1UL << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1VALUE_Pos (30U)
+#define COMP_CSR_COMP1VALUE_Msk (0x1UL << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK_Pos (31U)
+#define COMP_CSR_COMP1LOCK_Msk (0x1UL << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN_Pos (0U)
+#define COMP_CSR_COMP2EN_Msk (0x1UL << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
+#define COMP_CSR_COMP2SPEED_Pos (3U)
+#define COMP_CSR_COMP2SPEED_Msk (0x1UL << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */
+#define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */
+#define COMP_CSR_COMP2INNSEL_Pos (4U)
+#define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */
+#define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
+#define COMP_CSR_COMP2INPSEL_Pos (8U)
+#define COMP_CSR_COMP2INPSEL_Msk (0x7UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */
+#define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2INPSEL_0 (0x1UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP2INPSEL_1 (0x2UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */
+#define COMP_CSR_COMP2INPSEL_2 (0x4UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */
+#define COMP_CSR_COMP2LPTIM1IN2_Pos (12U)
+#define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */
+#define COMP_CSR_COMP2LPTIM1IN1_Pos (13U)
+#define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */
+#define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP2POLARITY_Pos (15U)
+#define COMP_CSR_COMP2POLARITY_Msk (0x1UL << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2VALUE_Pos (30U)
+#define COMP_CSR_COMP2VALUE_Msk (0x1UL << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK_Pos (31U)
+#define COMP_CSR_COMP2LOCK_Msk (0x1UL << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
+
+/********************** Bit definition for COMP_CSR register common ****************/
+#define COMP_CSR_COMPxEN_Pos (0U)
+#define COMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
+#define COMP_CSR_COMPxPOLARITY_Pos (15U)
+#define COMP_CSR_COMPxPOLARITY_Msk (0x1UL << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */
+#define COMP_CSR_COMPxOUTVALUE_Pos (30U)
+#define COMP_CSR_COMPxOUTVALUE_Msk (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK_Pos (31U)
+#define COMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
+
+/* Reference defines */
+#define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR (0xFFU) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos (3U)
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos (5U)
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos (7U)
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT_Pos (0U)
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL_Pos (0U)
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_Pos (0U)
+#define DBGMCU_CR_DBG_Msk (0x7UL << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
+#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+
+/******************* Bit definition for DMA_CSELR register *******************/
+#define DMA_CSELR_C1S_Pos (0U)
+#define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
+#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos (4U)
+#define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
+#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos (8U)
+#define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
+#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos (12U)
+#define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
+#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos (16U)
+#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
+#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S_Pos (20U)
+#define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
+#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S_Pos (24U)
+#define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
+#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_IM0_Pos (0U)
+#define EXTI_IMR_IM0_Msk (0x1UL << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_IM1_Pos (1U)
+#define EXTI_IMR_IM1_Msk (0x1UL << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_IM2_Pos (2U)
+#define EXTI_IMR_IM2_Msk (0x1UL << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_IM3_Pos (3U)
+#define EXTI_IMR_IM3_Msk (0x1UL << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_IM4_Pos (4U)
+#define EXTI_IMR_IM4_Msk (0x1UL << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_IM5_Pos (5U)
+#define EXTI_IMR_IM5_Msk (0x1UL << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_IM6_Pos (6U)
+#define EXTI_IMR_IM6_Msk (0x1UL << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_IM7_Pos (7U)
+#define EXTI_IMR_IM7_Msk (0x1UL << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_IM8_Pos (8U)
+#define EXTI_IMR_IM8_Msk (0x1UL << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_IM9_Pos (9U)
+#define EXTI_IMR_IM9_Msk (0x1UL << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_IM10_Pos (10U)
+#define EXTI_IMR_IM10_Msk (0x1UL << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_IM11_Pos (11U)
+#define EXTI_IMR_IM11_Msk (0x1UL << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_IM12_Pos (12U)
+#define EXTI_IMR_IM12_Msk (0x1UL << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_IM13_Pos (13U)
+#define EXTI_IMR_IM13_Msk (0x1UL << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_IM14_Pos (14U)
+#define EXTI_IMR_IM14_Msk (0x1UL << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_IM15_Pos (15U)
+#define EXTI_IMR_IM15_Msk (0x1UL << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_IM16_Pos (16U)
+#define EXTI_IMR_IM16_Msk (0x1UL << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_IM17_Pos (17U)
+#define EXTI_IMR_IM17_Msk (0x1UL << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_IM18_Pos (18U)
+#define EXTI_IMR_IM18_Msk (0x1UL << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_IM19_Pos (19U)
+#define EXTI_IMR_IM19_Msk (0x1UL << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_IM20_Pos (20U)
+#define EXTI_IMR_IM20_Msk (0x1UL << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_IM21_Pos (21U)
+#define EXTI_IMR_IM21_Msk (0x1UL << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_IM22_Pos (22U)
+#define EXTI_IMR_IM22_Msk (0x1UL << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_IM23_Pos (23U)
+#define EXTI_IMR_IM23_Msk (0x1UL << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
+#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_IM25_Pos (25U)
+#define EXTI_IMR_IM25_Msk (0x1UL << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */
+#define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_IM26_Pos (26U)
+#define EXTI_IMR_IM26_Msk (0x1UL << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
+#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_IM28_Pos (28U)
+#define EXTI_IMR_IM28_Msk (0x1UL << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
+#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_IM29_Pos (29U)
+#define EXTI_IMR_IM29_Msk (0x1UL << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
+#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
+
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x36FFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x36FFFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_EM0_Pos (0U)
+#define EXTI_EMR_EM0_Msk (0x1UL << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_EM1_Pos (1U)
+#define EXTI_EMR_EM1_Msk (0x1UL << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_EM2_Pos (2U)
+#define EXTI_EMR_EM2_Msk (0x1UL << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_EM3_Pos (3U)
+#define EXTI_EMR_EM3_Msk (0x1UL << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_EM4_Pos (4U)
+#define EXTI_EMR_EM4_Msk (0x1UL << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_EM5_Pos (5U)
+#define EXTI_EMR_EM5_Msk (0x1UL << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_EM6_Pos (6U)
+#define EXTI_EMR_EM6_Msk (0x1UL << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_EM7_Pos (7U)
+#define EXTI_EMR_EM7_Msk (0x1UL << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_EM8_Pos (8U)
+#define EXTI_EMR_EM8_Msk (0x1UL << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_EM9_Pos (9U)
+#define EXTI_EMR_EM9_Msk (0x1UL << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_EM10_Pos (10U)
+#define EXTI_EMR_EM10_Msk (0x1UL << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_EM11_Pos (11U)
+#define EXTI_EMR_EM11_Msk (0x1UL << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_EM12_Pos (12U)
+#define EXTI_EMR_EM12_Msk (0x1UL << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_EM13_Pos (13U)
+#define EXTI_EMR_EM13_Msk (0x1UL << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_EM14_Pos (14U)
+#define EXTI_EMR_EM14_Msk (0x1UL << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_EM15_Pos (15U)
+#define EXTI_EMR_EM15_Msk (0x1UL << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_EM16_Pos (16U)
+#define EXTI_EMR_EM16_Msk (0x1UL << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_EM17_Pos (17U)
+#define EXTI_EMR_EM17_Msk (0x1UL << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_EM18_Pos (18U)
+#define EXTI_EMR_EM18_Msk (0x1UL << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_EM19_Pos (19U)
+#define EXTI_EMR_EM19_Msk (0x1UL << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_EM20_Pos (20U)
+#define EXTI_EMR_EM20_Msk (0x1UL << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_EM21_Pos (21U)
+#define EXTI_EMR_EM21_Msk (0x1UL << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_EM22_Pos (22U)
+#define EXTI_EMR_EM22_Msk (0x1UL << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */
+#define EXTI_EMR_EM23_Pos (23U)
+#define EXTI_EMR_EM23_Msk (0x1UL << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
+#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
+#define EXTI_EMR_EM25_Pos (25U)
+#define EXTI_EMR_EM25_Msk (0x1UL << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */
+#define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */
+#define EXTI_EMR_EM26_Pos (26U)
+#define EXTI_EMR_EM26_Msk (0x1UL << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
+#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
+#define EXTI_EMR_EM28_Pos (28U)
+#define EXTI_EMR_EM28_Msk (0x1UL << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
+#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
+#define EXTI_EMR_EM29_Pos (29U)
+#define EXTI_EMR_EM29_Msk (0x1UL << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
+#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_RT0_Pos (0U)
+#define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_RT1_Pos (1U)
+#define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_RT2_Pos (2U)
+#define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_RT3_Pos (3U)
+#define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_RT4_Pos (4U)
+#define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_RT5_Pos (5U)
+#define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_RT6_Pos (6U)
+#define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_RT7_Pos (7U)
+#define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_RT8_Pos (8U)
+#define EXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_RT9_Pos (9U)
+#define EXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_RT10_Pos (10U)
+#define EXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_RT11_Pos (11U)
+#define EXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_RT12_Pos (12U)
+#define EXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_RT13_Pos (13U)
+#define EXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_RT14_Pos (14U)
+#define EXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_RT15_Pos (15U)
+#define EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_RT16_Pos (16U)
+#define EXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_RT17_Pos (17U)
+#define EXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_RT19_Pos (19U)
+#define EXTI_RTSR_RT19_Msk (0x1UL << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_RT20_Pos (20U)
+#define EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_RT21_Pos (21U)
+#define EXTI_RTSR_RT21_Msk (0x1UL << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_RT22_Pos (22U)
+#define EXTI_RTSR_RT22_Msk (0x1UL << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
+#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
+#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
+#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
+#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
+#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
+#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
+#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
+#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
+#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
+#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
+#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
+#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
+#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
+#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
+#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
+#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
+#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
+#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
+#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
+#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
+#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_FT0_Pos (0U)
+#define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_FT1_Pos (1U)
+#define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_FT2_Pos (2U)
+#define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_FT3_Pos (3U)
+#define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_FT4_Pos (4U)
+#define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_FT5_Pos (5U)
+#define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_FT6_Pos (6U)
+#define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_FT7_Pos (7U)
+#define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_FT8_Pos (8U)
+#define EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_FT9_Pos (9U)
+#define EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_FT10_Pos (10U)
+#define EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_FT11_Pos (11U)
+#define EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_FT12_Pos (12U)
+#define EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_FT13_Pos (13U)
+#define EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_FT14_Pos (14U)
+#define EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_FT15_Pos (15U)
+#define EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_FT16_Pos (16U)
+#define EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_FT17_Pos (17U)
+#define EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_FT19_Pos (19U)
+#define EXTI_FTSR_FT19_Msk (0x1UL << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_FT20_Pos (20U)
+#define EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_FT21_Pos (21U)
+#define EXTI_FTSR_FT21_Msk (0x1UL << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_FT22_Pos (22U)
+#define EXTI_FTSR_FT22_Msk (0x1UL << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
+#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
+#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
+#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
+#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
+#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
+#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
+#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
+#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
+#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
+#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
+#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
+#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
+#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
+#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
+#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
+#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
+#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
+#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
+#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
+#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
+#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWI0_Pos (0U)
+#define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWI1_Pos (1U)
+#define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWI2_Pos (2U)
+#define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWI3_Pos (3U)
+#define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWI4_Pos (4U)
+#define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWI5_Pos (5U)
+#define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWI6_Pos (6U)
+#define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWI7_Pos (7U)
+#define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWI8_Pos (8U)
+#define EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWI9_Pos (9U)
+#define EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWI10_Pos (10U)
+#define EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWI11_Pos (11U)
+#define EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWI12_Pos (12U)
+#define EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWI13_Pos (13U)
+#define EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWI14_Pos (14U)
+#define EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWI15_Pos (15U)
+#define EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWI16_Pos (16U)
+#define EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWI17_Pos (17U)
+#define EXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWI19_Pos (19U)
+#define EXTI_SWIER_SWI19_Msk (0x1UL << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWI20_Pos (20U)
+#define EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWI21_Pos (21U)
+#define EXTI_SWIER_SWI21_Msk (0x1UL << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWI22_Pos (22U)
+#define EXTI_SWIER_SWI22_Msk (0x1UL << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
+
+/* Legacy defines */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PIF0_Pos (0U)
+#define EXTI_PR_PIF0_Msk (0x1UL << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
+#define EXTI_PR_PIF1_Pos (1U)
+#define EXTI_PR_PIF1_Msk (0x1UL << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
+#define EXTI_PR_PIF2_Pos (2U)
+#define EXTI_PR_PIF2_Msk (0x1UL << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
+#define EXTI_PR_PIF3_Pos (3U)
+#define EXTI_PR_PIF3_Msk (0x1UL << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
+#define EXTI_PR_PIF4_Pos (4U)
+#define EXTI_PR_PIF4_Msk (0x1UL << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
+#define EXTI_PR_PIF5_Pos (5U)
+#define EXTI_PR_PIF5_Msk (0x1UL << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
+#define EXTI_PR_PIF6_Pos (6U)
+#define EXTI_PR_PIF6_Msk (0x1UL << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
+#define EXTI_PR_PIF7_Pos (7U)
+#define EXTI_PR_PIF7_Msk (0x1UL << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
+#define EXTI_PR_PIF8_Pos (8U)
+#define EXTI_PR_PIF8_Msk (0x1UL << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
+#define EXTI_PR_PIF9_Pos (9U)
+#define EXTI_PR_PIF9_Msk (0x1UL << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
+#define EXTI_PR_PIF10_Pos (10U)
+#define EXTI_PR_PIF10_Msk (0x1UL << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
+#define EXTI_PR_PIF11_Pos (11U)
+#define EXTI_PR_PIF11_Msk (0x1UL << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
+#define EXTI_PR_PIF12_Pos (12U)
+#define EXTI_PR_PIF12_Msk (0x1UL << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
+#define EXTI_PR_PIF13_Pos (13U)
+#define EXTI_PR_PIF13_Msk (0x1UL << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
+#define EXTI_PR_PIF14_Pos (14U)
+#define EXTI_PR_PIF14_Msk (0x1UL << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
+#define EXTI_PR_PIF15_Pos (15U)
+#define EXTI_PR_PIF15_Msk (0x1UL << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
+#define EXTI_PR_PIF16_Pos (16U)
+#define EXTI_PR_PIF16_Msk (0x1UL << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
+#define EXTI_PR_PIF17_Pos (17U)
+#define EXTI_PR_PIF17_Msk (0x1UL << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
+#define EXTI_PR_PIF19_Pos (19U)
+#define EXTI_PR_PIF19_Msk (0x1UL << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
+#define EXTI_PR_PIF20_Pos (20U)
+#define EXTI_PR_PIF20_Msk (0x1UL << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
+#define EXTI_PR_PIF21_Pos (21U)
+#define EXTI_PR_PIF21_Msk (0x1UL << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
+#define EXTI_PR_PIF22_Pos (22U)
+#define EXTI_PR_PIF22_Msk (0x1UL << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
+
+/* Legacy defines */
+#define EXTI_PR_PR0 EXTI_PR_PIF0
+#define EXTI_PR_PR1 EXTI_PR_PIF1
+#define EXTI_PR_PR2 EXTI_PR_PIF2
+#define EXTI_PR_PR3 EXTI_PR_PIF3
+#define EXTI_PR_PR4 EXTI_PR_PIF4
+#define EXTI_PR_PR5 EXTI_PR_PIF5
+#define EXTI_PR_PR6 EXTI_PR_PIF6
+#define EXTI_PR_PR7 EXTI_PR_PIF7
+#define EXTI_PR_PR8 EXTI_PR_PIF8
+#define EXTI_PR_PR9 EXTI_PR_PIF9
+#define EXTI_PR_PR10 EXTI_PR_PIF10
+#define EXTI_PR_PR11 EXTI_PR_PIF11
+#define EXTI_PR_PR12 EXTI_PR_PIF12
+#define EXTI_PR_PR13 EXTI_PR_PIF13
+#define EXTI_PR_PR14 EXTI_PR_PIF14
+#define EXTI_PR_PR15 EXTI_PR_PIF15
+#define EXTI_PR_PR16 EXTI_PR_PIF16
+#define EXTI_PR_PR17 EXTI_PR_PIF17
+#define EXTI_PR_PR19 EXTI_PR_PIF19
+#define EXTI_PR_PR20 EXTI_PR_PIF20
+#define EXTI_PR_PR21 EXTI_PR_PIF21
+#define EXTI_PR_PR22 EXTI_PR_PIF22
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
+#define FLASH_ACR_PRFTEN_Pos (1U)
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_SLEEP_PD_Pos (3U)
+#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD_Pos (4U)
+#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
+#define FLASH_ACR_DISAB_BUF_Pos (5U)
+#define FLASH_ACR_DISAB_BUF_Msk (0x1UL << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
+#define FLASH_ACR_PRE_READ_Pos (6U)
+#define FLASH_ACR_PRE_READ_Msk (0x1UL << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
+#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
+
+/******************* Bit definition for FLASH_PECR register ******************/
+#define FLASH_PECR_PELOCK_Pos (0U)
+#define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
+#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK_Pos (1U)
+#define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
+#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK_Pos (2U)
+#define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
+#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG_Pos (3U)
+#define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
+#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
+#define FLASH_PECR_DATA_Pos (4U)
+#define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
+#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
+#define FLASH_PECR_FIX_Pos (8U)
+#define FLASH_PECR_FIX_Msk (0x1UL << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
+#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE_Pos (9U)
+#define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
+#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
+#define FLASH_PECR_FPRG_Pos (10U)
+#define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
+#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_EOPIE_Pos (16U)
+#define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
+#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
+#define FLASH_PECR_ERRIE_Pos (17U)
+#define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
+#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
+#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
+#define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
+#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
+#define FLASH_PECR_HALF_ARRAY_Pos (19U)
+#define FLASH_PECR_HALF_ARRAY_Msk (0x1UL << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
+#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
+
+/****************** Bit definition for FLASH_PDKEYR register ******************/
+#define FLASH_PDKEYR_PDKEYR_Pos (0U)
+#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PEKEYR register ******************/
+#define FLASH_PEKEYR_PEKEYR_Pos (0U)
+#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PRGKEYR register ******************/
+#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
+#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
+
+/****************** Bit definition for FLASH_OPTKEYR register ******************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_EOP_Pos (1U)
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
+#define FLASH_SR_HVOFF_Pos (2U)
+#define FLASH_SR_HVOFF_Msk (0x1UL << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
+#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
+#define FLASH_SR_READY_Pos (3U)
+#define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */
+#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR_Pos (8U)
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
+#define FLASH_SR_PGAERR_Pos (9U)
+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR_Pos (10U)
+#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
+#define FLASH_SR_OPTVERR_Pos (11U)
+#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
+#define FLASH_SR_RDERR_Pos (13U)
+#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
+#define FLASH_SR_NOTZEROERR_Pos (16U)
+#define FLASH_SR_NOTZEROERR_Msk (0x1UL << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
+#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
+#define FLASH_SR_FWWERR_Pos (17U)
+#define FLASH_SR_FWWERR_Msk (0x1UL << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
+#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
+
+/* Legacy defines */
+#define FLASH_SR_FWWER FLASH_SR_FWWERR
+#define FLASH_SR_ENHV FLASH_SR_HVOFF
+#define FLASH_SR_ENDHV FLASH_SR_HVOFF
+
+/****************** Bit definition for FLASH_OPTR register *******************/
+#define FLASH_OPTR_RDPROT_Pos (0U)
+#define FLASH_OPTR_RDPROT_Msk (0xFFUL << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
+#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
+#define FLASH_OPTR_WPRMOD_Pos (8U)
+#define FLASH_OPTR_WPRMOD_Msk (0x1UL << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
+#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
+#define FLASH_OPTR_BOR_LEV_Pos (16U)
+#define FLASH_OPTR_BOR_LEV_Msk (0xFUL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
+#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OPTR_IWDG_SW_Pos (20U)
+#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
+#define FLASH_OPTR_nRST_STOP_Pos (21U)
+#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OPTR_nRST_STDBY_Pos (22U)
+#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OPTR_USER_Pos (20U)
+#define FLASH_OPTR_USER_Msk (0x7UL << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
+#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OPTR_BOOT1_Pos (31U)
+#define FLASH_OPTR_BOOT1_Msk (0x1UL << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
+#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 (0x00000001U)
+#define GPIO_OTYPER_OT_1 (0x00000002U)
+#define GPIO_OTYPER_OT_2 (0x00000004U)
+#define GPIO_OTYPER_OT_3 (0x00000008U)
+#define GPIO_OTYPER_OT_4 (0x00000010U)
+#define GPIO_OTYPER_OT_5 (0x00000020U)
+#define GPIO_OTYPER_OT_6 (0x00000040U)
+#define GPIO_OTYPER_OT_7 (0x00000080U)
+#define GPIO_OTYPER_OT_8 (0x00000100U)
+#define GPIO_OTYPER_OT_9 (0x00000200U)
+#define GPIO_OTYPER_OT_10 (0x00000400U)
+#define GPIO_OTYPER_OT_11 (0x00000800U)
+#define GPIO_OTYPER_OT_12 (0x00001000U)
+#define GPIO_OTYPER_OT_13 (0x00002000U)
+#define GPIO_OTYPER_OT_14 (0x00004000U)
+#define GPIO_OTYPER_OT_15 (0x00008000U)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDER_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
+#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDER_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
+#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDER_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
+#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDER_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
+#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDER_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
+#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDER_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
+#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDER_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
+#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDER_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
+#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDER_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
+#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDER_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
+#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDER_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
+#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDER_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
+#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDER_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
+#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDER_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
+#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDER_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
+#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDER_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
+#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 (0x00000001U)
+#define GPIO_BSRR_BS_1 (0x00000002U)
+#define GPIO_BSRR_BS_2 (0x00000004U)
+#define GPIO_BSRR_BS_3 (0x00000008U)
+#define GPIO_BSRR_BS_4 (0x00000010U)
+#define GPIO_BSRR_BS_5 (0x00000020U)
+#define GPIO_BSRR_BS_6 (0x00000040U)
+#define GPIO_BSRR_BS_7 (0x00000080U)
+#define GPIO_BSRR_BS_8 (0x00000100U)
+#define GPIO_BSRR_BS_9 (0x00000200U)
+#define GPIO_BSRR_BS_10 (0x00000400U)
+#define GPIO_BSRR_BS_11 (0x00000800U)
+#define GPIO_BSRR_BS_12 (0x00001000U)
+#define GPIO_BSRR_BS_13 (0x00002000U)
+#define GPIO_BSRR_BS_14 (0x00004000U)
+#define GPIO_BSRR_BS_15 (0x00008000U)
+#define GPIO_BSRR_BR_0 (0x00010000U)
+#define GPIO_BSRR_BR_1 (0x00020000U)
+#define GPIO_BSRR_BR_2 (0x00040000U)
+#define GPIO_BSRR_BR_3 (0x00080000U)
+#define GPIO_BSRR_BR_4 (0x00100000U)
+#define GPIO_BSRR_BR_5 (0x00200000U)
+#define GPIO_BSRR_BR_6 (0x00400000U)
+#define GPIO_BSRR_BR_7 (0x00800000U)
+#define GPIO_BSRR_BR_8 (0x01000000U)
+#define GPIO_BSRR_BR_9 (0x02000000U)
+#define GPIO_BSRR_BR_10 (0x04000000U)
+#define GPIO_BSRR_BR_11 (0x08000000U)
+#define GPIO_BSRR_BR_12 (0x10000000U)
+#define GPIO_BSRR_BR_13 (0x20000000U)
+#define GPIO_BSRR_BR_14 (0x40000000U)
+#define GPIO_BSRR_BR_15 (0x80000000U)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 (0x00000001U)
+#define GPIO_BRR_BR_1 (0x00000002U)
+#define GPIO_BRR_BR_2 (0x00000004U)
+#define GPIO_BRR_BR_3 (0x00000008U)
+#define GPIO_BRR_BR_4 (0x00000010U)
+#define GPIO_BRR_BR_5 (0x00000020U)
+#define GPIO_BRR_BR_6 (0x00000040U)
+#define GPIO_BRR_BR_7 (0x00000080U)
+#define GPIO_BRR_BR_8 (0x00000100U)
+#define GPIO_BRR_BR_9 (0x00000200U)
+#define GPIO_BRR_BR_10 (0x00000400U)
+#define GPIO_BRR_BR_11 (0x00000800U)
+#define GPIO_BRR_BR_12 (0x00001000U)
+#define GPIO_BRR_BR_13 (0x00002000U)
+#define GPIO_BRR_BR_14 (0x00004000U)
+#define GPIO_BRR_BR_15 (0x00008000U)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos (1U)
+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos (2U)
+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos (3U)
+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos (4U)
+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos (5U)
+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos (6U)
+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos (7U)
+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos (8U)
+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos (12U)
+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos (14U)
+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos (15U)
+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos (16U)
+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos (17U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos (18U)
+#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos (19U)
+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos (20U)
+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos (21U)
+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos (22U)
+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos (23U)
+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD_Pos (0U)
+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos (10U)
+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos (11U)
+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos (12U)
+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos (13U)
+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
+#define I2C_CR2_STOP_Pos (14U)
+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos (15U)
+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos (16U)
+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos (24U)
+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos (25U)
+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos (26U)
+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1_Pos (0U)
+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos (10U)
+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos (15U)
+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2_Pos (1U)
+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos (8U)
+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos (8U)
+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos (9U)
+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos (8U)
+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos (10U)
+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos (8U)
+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos (9U)
+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos (8U)
+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos (15U)
+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos (0U)
+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos (8U)
+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos (16U)
+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos (20U)
+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos (28U)
+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE_Pos (0U)
+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos (1U)
+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos (2U)
+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos (3U)
+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos (4U)
+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos (5U)
+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos (6U)
+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos (7U)
+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos (8U)
+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
+#define I2C_ISR_ARLO_Pos (9U)
+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos (10U)
+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos (11U)
+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos (12U)
+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos (13U)
+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos (15U)
+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
+#define I2C_ISR_DIR_Pos (16U)
+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos (17U)
+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF_Pos (3U)
+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos (4U)
+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos (5U)
+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos (8U)
+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos (9U)
+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos (10U)
+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos (11U)
+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos (12U)
+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos (13U)
+#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define I2C_PECR_PEC_Pos (0U)
+#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA_Pos (0U)
+#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA_Pos (0U)
+#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos (2U)
+#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN_Pos (0U)
+#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM_Pos (0U)
+#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos (1U)
+#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos (2U)
+#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos (3U)
+#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos (4U)
+#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos (5U)
+#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos (6U)
+#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF_Pos (0U)
+#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos (1U)
+#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos (3U)
+#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos (4U)
+#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos (5U)
+#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos (6U)
+#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos (0U)
+#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos (1U)
+#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos (3U)
+#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos (4U)
+#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos (5U)
+#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos (6U)
+#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos (0U)
+#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos (1U)
+#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos (3U)
+#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos (6U)
+#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos (9U)
+#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos (17U)
+#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos (19U)
+#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos (20U)
+#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos (21U)
+#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos (22U)
+#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos (24U)
+#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE_Pos (0U)
+#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos (1U)
+#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos (2U)
+#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP_Pos (0U)
+#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR_Pos (0U)
+#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT_Pos (0U)
+#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
+
+/******************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/******************************************************************************/
+
+#define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPSDSR_Pos (0U)
+#define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP_Pos (9U)
+#define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /*!< 0x00000200 */
+#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
+#define PWR_CR_FWU_Pos (10U)
+#define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /*!< 0x00000400 */
+#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
+
+#define PWR_CR_VOS_Pos (11U)
+#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x00001800 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /*!< 0x00000800 */
+#define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /*!< 0x00001000 */
+#define PWR_CR_DSEEKOFF_Pos (13U)
+#define PWR_CR_DSEEKOFF_Msk (0x1UL << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */
+#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */
+#define PWR_CR_LPRUN_Pos (14U)
+#define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
+#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF_Pos (3U)
+#define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
+#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF_Pos (4U)
+#define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
+#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF_Pos (5U)
+#define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
+#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1_Pos (8U)
+#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2_Pos (9U)
+#define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
+#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP3_Pos (10U)
+#define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
+#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos (1U)
+#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos (2U)
+#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIVEN_Pos (3U)
+#define RCC_CR_HSIDIVEN_Msk (0x1UL << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */
+#define RCC_CR_HSIDIVF_Pos (4U)
+#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */
+#define RCC_CR_HSIOUTEN_Pos (5U)
+#define RCC_CR_HSIOUTEN_Msk (0x1UL << RCC_CR_HSIOUTEN_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_Msk /*!< Internal High Speed clock out enable */
+#define RCC_CR_MSION_Pos (8U)
+#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000100 */
+#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY_Pos (9U)
+#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
+#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON_Pos (19U)
+#define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */
+#define RCC_CR_RTCPRE_Pos (20U)
+#define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
+#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */
+#define RCC_CR_RTCPRE_0 (0x1UL << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */
+#define RCC_CR_RTCPRE_1 (0x2UL << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+/* Reference defines */
+#define RCC_CR_CSSON RCC_CR_CSSHSEON
+
+/******************** Bit definition for RCC_ICSCR register *****************/
+#define RCC_ICSCR_HSICAL_Pos (0U)
+#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
+#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM_Pos (8U)
+#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
+#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE_Pos (13U)
+#define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
+#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
+#define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
+#define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
+#define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
+#define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
+#define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
+#define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
+#define RCC_ICSCR_MSICAL_Pos (16U)
+#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
+#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM_Pos (24U)
+#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
+#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos (15U)
+#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */
+
+/*!< PLL entry clock source*/
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
+
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL_Pos (18U)
+#define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV_Pos (22U)
+#define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
+
+#define RCC_CFGR_PLLDIV2_Pos (22U)
+#define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3_Pos (23U)
+#define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4_Pos (22U)
+#define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCOSEL_Pos (24U)
+#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
+#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
+
+#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
+#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCOSEL_HSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_MSI_Pos (24U)
+#define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
+#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_HSE_Pos (26U)
+#define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCOSEL_PLL_Pos (24U)
+#define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
+#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
+#define RCC_CFGR_MCOSEL_LSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
+#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
+#define RCC_CFGR_MCOSEL_LSE_Pos (24U)
+#define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
+
+#define RCC_CFGR_MCOPRE_Pos (28U)
+#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
+
+#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
+
+/* Legacy defines */
+#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
+#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
+#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
+#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
+#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
+#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
+#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
+#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
+#ifdef RCC_CFGR_MCOSEL_HSI48
+#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48
+#endif
+
+#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
+#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
+
+/*!<****************** Bit definition for RCC_CIER register ********************/
+#define RCC_CIER_LSIRDYIE_Pos (0U)
+#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIER_LSERDYIE_Pos (1U)
+#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIER_HSIRDYIE_Pos (2U)
+#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIER_HSERDYIE_Pos (3U)
+#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIER_PLLRDYIE_Pos (4U)
+#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIER_MSIRDYIE_Pos (5U)
+#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
+#define RCC_CIER_CSSLSE_Pos (7U)
+#define RCC_CIER_CSSLSE_Msk (0x1UL << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */
+
+/* Reference defines */
+#define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
+
+/*!<****************** Bit definition for RCC_CIFR register ********************/
+#define RCC_CIFR_LSIRDYF_Pos (0U)
+#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIFR_LSERDYF_Pos (1U)
+#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIFR_HSIRDYF_Pos (2U)
+#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIFR_HSERDYF_Pos (3U)
+#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIFR_PLLRDYF_Pos (4U)
+#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIFR_MSIRDYF_Pos (5U)
+#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
+#define RCC_CIFR_CSSLSEF_Pos (7U)
+#define RCC_CIFR_CSSLSEF_Msk (0x1UL << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */
+#define RCC_CIFR_CSSHSEF_Pos (8U)
+#define RCC_CIFR_CSSHSEF_Msk (0x1UL << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */
+#define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */
+
+/* Reference defines */
+#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
+#define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
+
+/*!<****************** Bit definition for RCC_CICR register ********************/
+#define RCC_CICR_LSIRDYC_Pos (0U)
+#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CICR_LSERDYC_Pos (1U)
+#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CICR_HSIRDYC_Pos (2U)
+#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CICR_HSERDYC_Pos (3U)
+#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CICR_PLLRDYC_Pos (4U)
+#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CICR_MSIRDYC_Pos (5U)
+#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
+#define RCC_CICR_CSSLSEC_Pos (7U)
+#define RCC_CICR_CSSLSEC_Msk (0x1UL << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */
+#define RCC_CICR_CSSHSEC_Pos (8U)
+#define RCC_CICR_CSSHSEC_Msk (0x1UL << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */
+#define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */
+
+/* Reference defines */
+#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
+#define RCC_CICR_CSSC RCC_CICR_CSSHSEC
+/***************** Bit definition for RCC_IOPRSTR register ******************/
+#define RCC_IOPRSTR_IOPARST_Pos (0U)
+#define RCC_IOPRSTR_IOPARST_Msk (0x1UL << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */
+#define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */
+#define RCC_IOPRSTR_IOPBRST_Pos (1U)
+#define RCC_IOPRSTR_IOPBRST_Msk (0x1UL << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */
+#define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */
+#define RCC_IOPRSTR_IOPCRST_Pos (2U)
+#define RCC_IOPRSTR_IOPCRST_Msk (0x1UL << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */
+#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */
+#define RCC_IOPRSTR_IOPHRST_Pos (7U)
+#define RCC_IOPRSTR_IOPHRST_Msk (0x1UL << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */
+#define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */
+
+/* Reference defines */
+#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
+#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
+#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
+#define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
+
+
+/****************** Bit definition for RCC_AHBRST register ******************/
+#define RCC_AHBRSTR_DMARST_Pos (0U)
+#define RCC_AHBRSTR_DMARST_Msk (0x1UL << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */
+#define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */
+#define RCC_AHBRSTR_MIFRST_Pos (8U)
+#define RCC_AHBRSTR_MIFRST_Msk (0x1UL << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */
+#define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset */
+#define RCC_AHBRSTR_CRCRST_Pos (12U)
+#define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */
+
+/* Reference defines */
+#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
+#define RCC_APB2RSTR_TIM21RST_Pos (2U)
+#define RCC_APB2RSTR_TIM21RST_Msk (0x1UL << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 reset */
+#define RCC_APB2RSTR_TIM22RST_Pos (5U)
+#define RCC_APB2RSTR_TIM22RST_Msk (0x1UL << RCC_APB2RSTR_TIM22RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk /*!< TIM22 reset */
+#define RCC_APB2RSTR_ADCRST_Pos (9U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
+#define RCC_APB2RSTR_DBGRST_Pos (22U)
+#define RCC_APB2RSTR_DBGRST_Msk (0x1UL << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU reset */
+
+/* Reference defines */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 reset */
+#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU reset */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_LPUART1RST_Pos (18U)
+#define RCC_APB1RSTR_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
+#define RCC_APB1RSTR_LPTIM1RST_Pos (31U)
+#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 reset */
+
+/***************** Bit definition for RCC_IOPENR register ******************/
+#define RCC_IOPENR_IOPAEN_Pos (0U)
+#define RCC_IOPENR_IOPAEN_Msk (0x1UL << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */
+#define RCC_IOPENR_IOPBEN_Pos (1U)
+#define RCC_IOPENR_IOPBEN_Msk (0x1UL << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */
+#define RCC_IOPENR_IOPCEN_Pos (2U)
+#define RCC_IOPENR_IOPCEN_Msk (0x1UL << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */
+#define RCC_IOPENR_IOPHEN_Pos (7U)
+#define RCC_IOPENR_IOPHEN_Msk (0x1UL << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */
+
+/* Reference defines */
+#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
+#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
+#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
+#define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
+
+/***************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMAEN_Pos (0U)
+#define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_MIFEN_Pos (8U)
+#define RCC_AHBENR_MIFEN_Msk (0x1UL << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */
+#define RCC_AHBENR_CRCEN_Pos (12U)
+#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+
+/* Reference defines */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register ******************/
+#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM21EN_Pos (2U)
+#define RCC_APB2ENR_TIM21EN_Msk (0x1UL << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */
+#define RCC_APB2ENR_TIM22EN_Pos (5U)
+#define RCC_APB2ENR_TIM22EN_Msk (0x1UL << RCC_APB2ENR_TIM22EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk /*!< TIM22 clock enable */
+#define RCC_APB2ENR_FWEN_Pos (7U)
+#define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADCEN_Pos (9U)
+#define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
+#define RCC_APB2ENR_DBGEN_Pos (22U)
+#define RCC_APB2ENR_DBGEN_Msk (0x1UL << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */
+
+/* Reference defines */
+
+#define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
+#define RCC_APB1ENR_LPUART1EN_Pos (18U)
+#define RCC_APB1ENR_LPUART1EN_Msk (0x1UL << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
+#define RCC_APB1ENR_LPTIM1EN_Pos (31U)
+#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */
+
+/****************** Bit definition for RCC_IOPSMENR register ****************/
+#define RCC_IOPSMENR_IOPASMEN_Pos (0U)
+#define RCC_IOPSMENR_IOPASMEN_Msk (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPBSMEN_Pos (1U)
+#define RCC_IOPSMENR_IOPBSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPCSMEN_Pos (2U)
+#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPHSMEN_Pos (7U)
+#define RCC_IOPSMENR_IOPHSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_AHBSMENR register ******************/
+#define RCC_AHBSMENR_DMASMEN_Pos (0U)
+#define RCC_AHBSMENR_DMASMEN_Msk (0x1UL << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */
+#define RCC_AHBSMENR_MIFSMEN_Pos (8U)
+#define RCC_AHBSMENR_MIFSMEN_Msk (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */
+#define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
+#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRCSMEN_Pos (12U)
+#define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB2SMENR register ******************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM21SMEN_Pos (2U)
+#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM22SMEN_Pos (5U)
+#define RCC_APB2SMENR_TIM22SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk /*!< TIM22 clock enabled in sleep mode */
+#define RCC_APB2SMENR_ADCSMEN_Pos (9U)
+#define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
+#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGSMEN_Pos (22U)
+#define RCC_APB2SMENR_DBGSMEN_Msk (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB1SMENR register ******************/
+#define RCC_APB1SMENR_TIM2SMEN_Pos (0U)
+#define RCC_APB1SMENR_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_WWDGSMEN_Pos (11U)
+#define RCC_APB1SMENR_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART2SMEN_Pos (17U)
+#define RCC_APB1SMENR_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPUART1SMEN_Pos (18U)
+#define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C1SMEN_Pos (21U)
+#define RCC_APB1SMENR_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_PWRSMEN_Pos (28U)
+#define RCC_APB1SMENR_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U)
+#define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */
+
+/*!< USART2 Clock source selection */
+#define RCC_CCIPR_USART2SEL_Pos (2U)
+#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */
+#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+/*!< LPUART1 Clock source selection */
+#define RCC_CCIPR_LPUART1SEL_Pos (10U)
+#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */
+#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */
+#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CCIPR_I2C1SEL_Pos (12U)
+#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */
+#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
+
+
+/*!< LPTIM1 Clock source selection */
+#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
+#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */
+#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+/******************* Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSEON_Pos (8U)
+#define RCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */
+#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_CSR_LSERDY_Pos (9U)
+#define RCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */
+#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP_Pos (10U)
+#define RCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */
+#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_CSR_LSEDRV_Pos (11U)
+#define RCC_CSR_LSEDRV_Msk (0x3UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */
+#define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_CSR_LSEDRV_0 (0x1UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */
+#define RCC_CSR_LSEDRV_1 (0x2UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */
+
+#define RCC_CSR_LSECSSON_Pos (13U)
+#define RCC_CSR_LSECSSON_Msk (0x1UL << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */
+#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */
+#define RCC_CSR_LSECSSD_Pos (14U)
+#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
+#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
+
+/*!< RTC congiguration */
+#define RCC_CSR_RTCSEL_Pos (16U)
+#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
+
+#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CSR_RTCSEL_LSE_Pos (16U)
+#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_LSI_Pos (17U)
+#define RCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */
+#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_HSE_Pos (16U)
+#define RCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */
+
+#define RCC_CSR_RTCEN_Pos (18U)
+#define RCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */
+#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_CSR_RTCRST_Pos (19U)
+#define RCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */
+#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */
+
+#define RCC_CSR_RMVF_Pos (23U)
+#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_FWRSTF_Pos (24U)
+#define RCC_CSR_FWRSTF_Msk (0x1UL << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk /*!< Mifare Firewall reset flag */
+#define RCC_CSR_OBLRSTF_Pos (25U)
+#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+/* Reference defines */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER1_SUPPORT
+#define RTC_TAMPER2_SUPPORT
+#define RTC_TAMPER3_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk /*!< */
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk /*!< */
+#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk /*!< */
+#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */
+#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */
+#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk /*!< */
+#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk /*!< */
+#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk /*!< */
+#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk /*!< */
+#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */
+#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk /*!< */
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk /*!< */
+#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk /*!< */
+#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk /*!< */
+#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk /*!< */
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */
+#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk /*!< */
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< */
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */
+#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */
+#define RTC_ISR_TAMP3F_Pos (15U)
+#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk /*!< */
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */
+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */
+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */
+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */
+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */
+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */
+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */
+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */
+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */
+#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */
+#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */
+#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */
+#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */
+#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */
+#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */
+#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */
+#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */
+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */
+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */
+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */
+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */
+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */
+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */
+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */
+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */
+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */
+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CALR register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */
+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define RTC_CAL_CALP RTC_CALR_CALP
+#define RTC_CAL_CALW8 RTC_CALR_CALW8
+#define RTC_CAL_CALW16 RTC_CALR_CALW16
+#define RTC_CAL_CALM RTC_CALR_CALM
+#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
+
+/******************** Bits definition for RTC_TAMPCR register ****************/
+#define RTC_TAMPCR_TAMP3MF_Pos (24U)
+#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
+#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
+#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
+#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP3IE_Pos (22U)
+#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
+#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2MF_Pos (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2IE_Pos (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1MF_Pos (18U)
+#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
+#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1IE_Pos (16U)
+#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */
+#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */
+#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */
+#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos (7U)
+#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */
+#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
+#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
+#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP3E_Pos (5U)
+#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
+#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk /*!< */
+#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP2E_Pos (3U)
+#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */
+#define RTC_TAMPCR_TAMPIE_Pos (2U)
+#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
+#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP1E_Pos (0U)
+#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_OR register ****************/
+#define RTC_OR_OUT_RMP_Pos (1U)
+#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */
+#define RTC_OR_ALARMOUTTYPE_Pos (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */
+
+/* Legacy defines */
+#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk /*!< */
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER (0x00000005U) /*!< */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/******************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
+#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR1_BOOT_MODE_Pos (8U)
+#define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
+#define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */
+#define SYSCFG_CFGR1_BOOT_MODE_0 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOT_MODE_1 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_FWDISEN_Pos (0U)
+#define SYSCFG_CFGR2_FWDISEN_Msk (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos (8U)
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR2_I2C_PB6_FMP SYSCFG_CFGR2_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos (9U)
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR2_I2C_PB7_FMP SYSCFG_CFGR2_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos (10U)
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
+#define SYSCFG_CFGR2_I2C_PB8_FMP SYSCFG_CFGR2_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos (11U)
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
+#define SYSCFG_CFGR2_I2C_PB9_FMP SYSCFG_CFGR2_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR2_I2C1_FMP_Pos (12U)
+#define SYSCFG_CFGR2_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR2_I2C1_FMP SYSCFG_CFGR2_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
+
+
+/***************** Bit definition for SYSCFG_CFGR3 register ****************/
+#define SYSCFG_CFGR3_EN_VREFINT_Pos (0U)
+#define SYSCFG_CFGR3_EN_VREFINT_Msk (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_EN_VREFINT SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
+#define SYSCFG_CFGR3_VREF_OUT_Pos (4U)
+#define SYSCFG_CFGR3_VREF_OUT_Msk (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
+#define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */
+#define SYSCFG_CFGR3_VREF_OUT_0 (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
+#define SYSCFG_CFGR3_VREF_OUT_1 (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U)
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U)
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U)
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
+#define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U)
+#define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
+#define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
+#define SYSCFG_CFGR3_REF_LOCK_Pos (31U)
+#define SYSCFG_CFGR3_REF_LOCK_Msk (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
+#define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */
+
+/* Legacy defines */
+
+#define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
+#define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
+#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
+#define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+
+/******************************************************************************/
+/* */
+/* Timers (TIM)*/
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
+#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
+ || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#else
+#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
+#endif
+
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFUL << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFUL << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM2_OR_ETR_RMP_Pos (0U)
+#define TIM2_OR_ETR_RMP_Msk (0x7UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000007 */
+#define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
+#define TIM2_OR_ETR_RMP_0 (0x1UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM2_OR_ETR_RMP_1 (0x2UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM2_OR_ETR_RMP_2 (0x4UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000004 */
+#define TIM2_OR_TI4_RMP_Pos (3U)
+#define TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000018 */
+#define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
+#define TIM2_OR_TI4_RMP_0 (0x1UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */
+#define TIM2_OR_TI4_RMP_1 (0x2UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000010 */
+
+#define TIM21_OR_ETR_RMP_Pos (0U)
+#define TIM21_OR_ETR_RMP_Msk (0x3UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
+#define TIM21_OR_ETR_RMP_0 (0x1UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM21_OR_ETR_RMP_1 (0x2UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM21_OR_TI1_RMP_Pos (2U)
+#define TIM21_OR_TI1_RMP_Msk (0x7UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x0000001C */
+#define TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
+#define TIM21_OR_TI1_RMP_0 (0x1UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM21_OR_TI1_RMP_1 (0x2UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+#define TIM21_OR_TI1_RMP_2 (0x4UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000010 */
+#define TIM21_OR_TI2_RMP_Pos (5U)
+#define TIM21_OR_TI2_RMP_Msk (0x1UL << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */
+#define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */
+
+#define TIM22_OR_ETR_RMP_Pos (0U)
+#define TIM22_OR_ETR_RMP_Msk (0x3UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM22_OR_ETR_RMP TIM22_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
+#define TIM22_OR_ETR_RMP_0 (0x1UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM22_OR_ETR_RMP_1 (0x2UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM22_OR_TI1_RMP_Pos (2U)
+#define TIM22_OR_TI1_RMP_Msk (0x3UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x0000000C */
+#define TIM22_OR_TI1_RMP TIM22_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
+#define TIM22_OR_TI1_RMP_0 (0x1UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM22_OR_TI1_RMP_1 (0x2UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE_Pos (0U)
+#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+#define USART_CR1_UESM_Pos (1U)
+#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
+#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_M0_Pos (12U)
+#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
+#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos (13U)
+#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos (14U)
+#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos (16U)
+#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
+#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
+#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
+#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
+#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos (21U)
+#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
+#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
+#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
+#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
+#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos (26U)
+#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos (27U)
+#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos (28U)
+#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
+#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7_Pos (4U)
+#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos (15U)
+#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos (16U)
+#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos (17U)
+#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos (18U)
+#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos (19U)
+#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos (20U)
+#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos (21U)
+#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos (23U)
+#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos (24U)
+#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos (12U)
+#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos (13U)
+#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos (14U)
+#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos (15U)
+#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos (17U)
+#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos (20U)
+#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
+#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
+#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos (22U)
+#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
+#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
+#define USART_CR3_UCESM_Pos (23U)
+#define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
+#define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION_Pos (0U)
+#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos (4U)
+#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO_Pos (0U)
+#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos (24U)
+#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ_Pos (0U)
+#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
+#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos (1U)
+#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
+#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos (2U)
+#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
+#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos (3U)
+#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
+#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos (4U)
+#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
+#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE_Pos (0U)
+#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
+#define USART_ISR_FE_Pos (1U)
+#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
+#define USART_ISR_NE_Pos (2U)
+#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos (3U)
+#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos (4U)
+#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos (5U)
+#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos (6U)
+#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos (7U)
+#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
+#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos (8U)
+#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos (9U)
+#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos (10U)
+#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
+#define USART_ISR_RTOF_Pos (11U)
+#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos (12U)
+#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos (14U)
+#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos (15U)
+#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos (16U)
+#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
+#define USART_ISR_CMF_Pos (17U)
+#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos (18U)
+#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos (19U)
+#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos (20U)
+#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
+#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos (21U)
+#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos (22U)
+#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
+#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF_Pos (0U)
+#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos (1U)
+#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos (2U)
+#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */
+#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos (3U)
+#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos (4U)
+#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos (6U)
+#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF_Pos (8U)
+#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos (9U)
+#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos (11U)
+#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos (12U)
+#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos (17U)
+#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos (20U)
+#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
+#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
+
+/* Compatibility defines with other series */
+#define USART_ICR_NECF USART_ICR_NCF
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR_Pos (0U)
+#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR_Pos (0U)
+#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+/******************************* COMP Instances *******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+ ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOH))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
+
+
+
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SMBUS Instances *****************************/
+#define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/************* LPTIM instances supporting the encoder mode feature ************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM21) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM22) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/******************* TIM Instances : output(s) OCXEC register *****************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/****************** USART Instances : Auto Baud Rate detection ****************/
+
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32L0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32L0 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+
+#define RNG_LPUART1_IRQn LPUART1_IRQn
+#define AES_LPUART1_IRQn LPUART1_IRQn
+#define AES_RNG_LPUART1_IRQn LPUART1_IRQn
+#define RCC_CRS_IRQn RCC_IRQn
+#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
+#define ADC1_IRQn ADC1_COMP_IRQn
+
+/* Aliases for __IRQHandler */
+#define RNG_LPUART1_IRQHandler LPUART1_IRQHandler
+#define AES_LPUART1_IRQHandler LPUART1_IRQHandler
+#define AES_RNG_LPUART1_IRQHandler LPUART1_IRQHandler
+#define RCC_CRS_IRQHandler RCC_IRQHandler
+#define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
+#define ADC1_IRQHandler ADC1_COMP_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L031xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/CMSIS/device/stm32l041xx.h b/CMSIS/device/stm32l041xx.h
new file mode 100644
index 0000000..f945ba6
--- /dev/null
+++ b/CMSIS/device/stm32l041xx.h
@@ -0,0 +1,6230 @@
+/**
+ ******************************************************************************
+ * @file stm32l041xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for stm32l041xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright(c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l041xx
+ * @{
+ */
+
+#ifndef __STM32L041xx_H
+#define __STM32L041xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 0U /*!< STM32L0xx provides no MPU */
+#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
+#define __NVIC_PRIO_BITS 2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief stm32l041xx Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+/*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
+
+/****** STM32L-0 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */
+ RCC_IRQn = 4, /*!< RCC Interrupt */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
+ ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
+ LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 Interrupt */
+ TIM21_IRQn = 20, /*!< TIM21 Interrupt */
+ TIM22_IRQn = 22, /*!< TIM22 Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ USART2_IRQn = 28, /*!< USART2 Interrupt */
+ AES_LPUART1_IRQn = 29, /*!< AES and LPUART1 Interrupts */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0plus.h"
+#include "system_stm32l0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+ uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+} ADC_Common_TypeDef;
+
+/**
+ * @brief AES hardware accelerator
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
+ __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
+ __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
+ __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
+ __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
+ __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
+ __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
+ __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
+ __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
+ __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
+ __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
+} AES_TypeDef;
+
+/**
+ * @brief Comparator
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
+} COMP_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+
+/**
+* @brief CRC calculation unit
+*/
+
+typedef struct
+{
+__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+uint8_t RESERVED0; /*!< Reserved, 0x05 */
+uint16_t RESERVED1; /*!< Reserved, 0x06 */
+__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+uint32_t RESERVED2; /*!< Reserved, 0x0C */
+__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
+} DMA_Request_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
+ __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
+ __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
+ __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
+ __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
+ __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
+ __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
+ __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
+ __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
+ __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
+} OB_TypeDef;
+
+
+/**
+ * @brief General Purpose IO
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief LPTIMIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+} LPTIM_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+ * @brief Independent WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
+ __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
+ __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
+ __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
+ __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
+ __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
+ __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
+ __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
+ __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
+ __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
+ __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */
+
+#define DATA_EEPROM_BASE (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
+#define DATA_EEPROM_END (0x080803FFUL) /*!< DATA EEPROM end address in the alias region */
+#define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */
+#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8KBytes) */
+
+#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000UL)
+
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
+#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800UL)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
+#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL)
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
+#define COMP1_BASE (APBPERIPH_BASE + 0x00010018UL)
+#define COMP2_BASE (APBPERIPH_BASE + 0x0001001CUL)
+#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL)
+#define TIM21_BASE (APBPERIPH_BASE + 0x00010800UL)
+#define TIM22_BASE (APBPERIPH_BASE + 0x00011400UL)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708UL)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
+#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL)
+
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
+#define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */
+#define FLASHSIZE_BASE (0x1FF8007CUL) /*!< FLASH Size register base address */
+#define UID_BASE (0x1FF80050UL) /*!< Unique device ID register base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
+#define AES_BASE (AHBPERIPH_BASE + 0x00006000UL)
+
+#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL)
+#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL)
+#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL)
+#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00UL)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
+#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
+/* Legacy defines */
+#define ADC ADC1_COMMON
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define AES ((AES_TypeDef *) AES_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_EOCAL_Pos (11U)
+#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
+#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
+#define ADC_ISR_AWD_Pos (7U)
+#define ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
+#define ADC_ISR_EOSEQ_Pos (3U)
+#define ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_EOCALIE_Pos (11U)
+#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
+#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
+#define ADC_IER_AWDIE_Pos (7U)
+#define ADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE_Pos (3U)
+#define ADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH_Pos (26U)
+#define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
+#define ADC_CFGR1_AWDEN_Pos (23U)
+#define ADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL_Pos (22U)
+#define ADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN_Pos (16U)
+#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF_Pos (15U)
+#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
+#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT_Pos (14U)
+#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
+#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT_Pos (13U)
+#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD_Pos (12U)
+#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN_Pos (10U)
+#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
+#define ADC_CFGR1_EXTSEL_Pos (6U)
+#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
+#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
+#define ADC_CFGR1_ALIGN_Pos (5U)
+#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
+#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
+#define ADC_CFGR1_RES_Pos (3U)
+#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
+#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
+#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
+#define ADC_CFGR1_SCANDIR_Pos (2U)
+#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG_Pos (1U)
+#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
+#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN_Pos (0U)
+#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
+#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_TOVS_Pos (9U)
+#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
+#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+#define ADC_CFGR2_OVSR_Pos (2U)
+#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
+#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+#define ADC_CFGR2_OVSE_Pos (0U)
+#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
+#define ADC_CFGR2_CKMODE_Pos (30U)
+#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
+#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
+#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
+#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
+
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP_Pos (0U)
+#define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
+#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
+#define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
+#define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define ADC_SMPR_SMPR ADC_SMPR_SMP
+#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
+#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
+#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT_Pos (16U)
+#define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
+#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
+#define ADC_TR_LT_Pos (0U)
+#define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL_Pos (0U)
+#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
+#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
+#define ADC_CHSELR_CHSEL18_Pos (18U)
+#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17_Pos (17U)
+#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
+#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL15_Pos (15U)
+#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
+#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14_Pos (14U)
+#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
+#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13_Pos (13U)
+#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
+#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12_Pos (12U)
+#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
+#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11_Pos (11U)
+#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
+#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10_Pos (10U)
+#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
+#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9_Pos (9U)
+#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
+#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8_Pos (8U)
+#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
+#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7_Pos (7U)
+#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
+#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6_Pos (6U)
+#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
+#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5_Pos (5U)
+#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
+#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4_Pos (4U)
+#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
+#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3_Pos (3U)
+#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
+#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2_Pos (2U)
+#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
+#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1_Pos (1U)
+#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
+#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0_Pos (0U)
+#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
+#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_CALFACT_Pos (0U)
+#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_LFMEN_Pos (25U)
+#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
+#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
+#define ADC_CCR_TSEN_Pos (23U)
+#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+/******************************************************************************/
+/* */
+/* Advanced Encryption Standard (AES) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for AES_CR register *********************/
+#define AES_CR_EN_Pos (0U)
+#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */
+#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */
+#define AES_CR_DATATYPE_Pos (1U)
+#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */
+#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */
+#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */
+#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */
+
+#define AES_CR_MODE_Pos (3U)
+#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */
+#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */
+#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */
+#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */
+
+#define AES_CR_CHMOD_Pos (5U)
+#define AES_CR_CHMOD_Msk (0x3UL << AES_CR_CHMOD_Pos) /*!< 0x00000060 */
+#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */
+#define AES_CR_CHMOD_0 (0x1UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */
+#define AES_CR_CHMOD_1 (0x2UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */
+
+#define AES_CR_CCFC_Pos (7U)
+#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */
+#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */
+#define AES_CR_ERRC_Pos (8U)
+#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */
+#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */
+#define AES_CR_CCIE_Pos (9U)
+#define AES_CR_CCIE_Msk (0x1UL << AES_CR_CCIE_Pos) /*!< 0x00000200 */
+#define AES_CR_CCIE AES_CR_CCIE_Msk /*!< Computation Complete Interrupt Enable */
+#define AES_CR_ERRIE_Pos (10U)
+#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */
+#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */
+#define AES_CR_DMAINEN_Pos (11U)
+#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */
+#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< DMA ENable managing the data input phase */
+#define AES_CR_DMAOUTEN_Pos (12U)
+#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */
+#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< DMA Enable managing the data output phase */
+
+/******************* Bit definition for AES_SR register *********************/
+#define AES_SR_CCF_Pos (0U)
+#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */
+#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */
+#define AES_SR_RDERR_Pos (1U)
+#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */
+#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */
+#define AES_SR_WRERR_Pos (2U)
+#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */
+#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */
+
+/******************* Bit definition for AES_DINR register *******************/
+#define AES_DINR_Pos (0U)
+#define AES_DINR_Msk (0xFFFFUL << AES_DINR_Pos) /*!< 0x0000FFFF */
+#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */
+
+/******************* Bit definition for AES_DOUTR register ******************/
+#define AES_DOUTR_Pos (0U)
+#define AES_DOUTR_Msk (0xFFFFUL << AES_DOUTR_Pos) /*!< 0x0000FFFF */
+#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */
+
+/******************* Bit definition for AES_KEYR0 register ******************/
+#define AES_KEYR0_Pos (0U)
+#define AES_KEYR0_Msk (0xFFFFUL << AES_KEYR0_Pos) /*!< 0x0000FFFF */
+#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */
+
+/******************* Bit definition for AES_KEYR1 register ******************/
+#define AES_KEYR1_Pos (0U)
+#define AES_KEYR1_Msk (0xFFFFUL << AES_KEYR1_Pos) /*!< 0x0000FFFF */
+#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */
+
+/******************* Bit definition for AES_KEYR2 register ******************/
+#define AES_KEYR2_Pos (0U)
+#define AES_KEYR2_Msk (0xFFFFUL << AES_KEYR2_Pos) /*!< 0x0000FFFF */
+#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */
+
+/******************* Bit definition for AES_KEYR3 register ******************/
+#define AES_KEYR3_Pos (0U)
+#define AES_KEYR3_Msk (0xFFFFUL << AES_KEYR3_Pos) /*!< 0x0000FFFF */
+#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */
+
+/******************* Bit definition for AES_IVR0 register *******************/
+#define AES_IVR0_Pos (0U)
+#define AES_IVR0_Msk (0xFFFFUL << AES_IVR0_Pos) /*!< 0x0000FFFF */
+#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */
+
+/******************* Bit definition for AES_IVR1 register *******************/
+#define AES_IVR1_Pos (0U)
+#define AES_IVR1_Msk (0xFFFFUL << AES_IVR1_Pos) /*!< 0x0000FFFF */
+#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */
+
+/******************* Bit definition for AES_IVR2 register *******************/
+#define AES_IVR2_Pos (0U)
+#define AES_IVR2_Msk (0xFFFFUL << AES_IVR2_Pos) /*!< 0x0000FFFF */
+#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */
+
+/******************* Bit definition for AES_IVR3 register *******************/
+#define AES_IVR3_Pos (0U)
+#define AES_IVR3_Msk (0xFFFFUL << AES_IVR3_Pos) /*!< 0x0000FFFF */
+#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+/************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN_Pos (0U)
+#define COMP_CSR_COMP1EN_Msk (0x1UL << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
+#define COMP_CSR_COMP1INNSEL_Pos (4U)
+#define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
+#define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP1WM_Pos (8U)
+#define COMP_CSR_COMP1WM_Msk (0x1UL << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */
+#define COMP_CSR_COMP1LPTIM1IN1_Pos (12U)
+#define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP1POLARITY_Pos (15U)
+#define COMP_CSR_COMP1POLARITY_Msk (0x1UL << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1VALUE_Pos (30U)
+#define COMP_CSR_COMP1VALUE_Msk (0x1UL << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK_Pos (31U)
+#define COMP_CSR_COMP1LOCK_Msk (0x1UL << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN_Pos (0U)
+#define COMP_CSR_COMP2EN_Msk (0x1UL << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
+#define COMP_CSR_COMP2SPEED_Pos (3U)
+#define COMP_CSR_COMP2SPEED_Msk (0x1UL << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */
+#define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */
+#define COMP_CSR_COMP2INNSEL_Pos (4U)
+#define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */
+#define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
+#define COMP_CSR_COMP2INPSEL_Pos (8U)
+#define COMP_CSR_COMP2INPSEL_Msk (0x7UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */
+#define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2INPSEL_0 (0x1UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP2INPSEL_1 (0x2UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */
+#define COMP_CSR_COMP2INPSEL_2 (0x4UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */
+#define COMP_CSR_COMP2LPTIM1IN2_Pos (12U)
+#define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */
+#define COMP_CSR_COMP2LPTIM1IN1_Pos (13U)
+#define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */
+#define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP2POLARITY_Pos (15U)
+#define COMP_CSR_COMP2POLARITY_Msk (0x1UL << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2VALUE_Pos (30U)
+#define COMP_CSR_COMP2VALUE_Msk (0x1UL << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK_Pos (31U)
+#define COMP_CSR_COMP2LOCK_Msk (0x1UL << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
+
+/********************** Bit definition for COMP_CSR register common ****************/
+#define COMP_CSR_COMPxEN_Pos (0U)
+#define COMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
+#define COMP_CSR_COMPxPOLARITY_Pos (15U)
+#define COMP_CSR_COMPxPOLARITY_Msk (0x1UL << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */
+#define COMP_CSR_COMPxOUTVALUE_Pos (30U)
+#define COMP_CSR_COMPxOUTVALUE_Msk (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK_Pos (31U)
+#define COMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
+
+/* Reference defines */
+#define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR (0xFFU) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos (3U)
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos (5U)
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos (7U)
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT_Pos (0U)
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL_Pos (0U)
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_Pos (0U)
+#define DBGMCU_CR_DBG_Msk (0x7UL << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
+#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+
+/******************* Bit definition for DMA_CSELR register *******************/
+#define DMA_CSELR_C1S_Pos (0U)
+#define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
+#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos (4U)
+#define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
+#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos (8U)
+#define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
+#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos (12U)
+#define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
+#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos (16U)
+#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
+#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S_Pos (20U)
+#define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
+#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S_Pos (24U)
+#define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
+#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_IM0_Pos (0U)
+#define EXTI_IMR_IM0_Msk (0x1UL << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_IM1_Pos (1U)
+#define EXTI_IMR_IM1_Msk (0x1UL << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_IM2_Pos (2U)
+#define EXTI_IMR_IM2_Msk (0x1UL << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_IM3_Pos (3U)
+#define EXTI_IMR_IM3_Msk (0x1UL << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_IM4_Pos (4U)
+#define EXTI_IMR_IM4_Msk (0x1UL << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_IM5_Pos (5U)
+#define EXTI_IMR_IM5_Msk (0x1UL << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_IM6_Pos (6U)
+#define EXTI_IMR_IM6_Msk (0x1UL << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_IM7_Pos (7U)
+#define EXTI_IMR_IM7_Msk (0x1UL << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_IM8_Pos (8U)
+#define EXTI_IMR_IM8_Msk (0x1UL << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_IM9_Pos (9U)
+#define EXTI_IMR_IM9_Msk (0x1UL << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_IM10_Pos (10U)
+#define EXTI_IMR_IM10_Msk (0x1UL << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_IM11_Pos (11U)
+#define EXTI_IMR_IM11_Msk (0x1UL << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_IM12_Pos (12U)
+#define EXTI_IMR_IM12_Msk (0x1UL << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_IM13_Pos (13U)
+#define EXTI_IMR_IM13_Msk (0x1UL << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_IM14_Pos (14U)
+#define EXTI_IMR_IM14_Msk (0x1UL << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_IM15_Pos (15U)
+#define EXTI_IMR_IM15_Msk (0x1UL << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_IM16_Pos (16U)
+#define EXTI_IMR_IM16_Msk (0x1UL << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_IM17_Pos (17U)
+#define EXTI_IMR_IM17_Msk (0x1UL << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_IM18_Pos (18U)
+#define EXTI_IMR_IM18_Msk (0x1UL << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_IM19_Pos (19U)
+#define EXTI_IMR_IM19_Msk (0x1UL << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_IM20_Pos (20U)
+#define EXTI_IMR_IM20_Msk (0x1UL << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_IM21_Pos (21U)
+#define EXTI_IMR_IM21_Msk (0x1UL << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_IM22_Pos (22U)
+#define EXTI_IMR_IM22_Msk (0x1UL << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_IM23_Pos (23U)
+#define EXTI_IMR_IM23_Msk (0x1UL << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
+#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_IM25_Pos (25U)
+#define EXTI_IMR_IM25_Msk (0x1UL << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */
+#define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_IM26_Pos (26U)
+#define EXTI_IMR_IM26_Msk (0x1UL << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
+#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_IM28_Pos (28U)
+#define EXTI_IMR_IM28_Msk (0x1UL << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
+#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_IM29_Pos (29U)
+#define EXTI_IMR_IM29_Msk (0x1UL << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
+#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
+
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x36FFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x36FFFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_EM0_Pos (0U)
+#define EXTI_EMR_EM0_Msk (0x1UL << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_EM1_Pos (1U)
+#define EXTI_EMR_EM1_Msk (0x1UL << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_EM2_Pos (2U)
+#define EXTI_EMR_EM2_Msk (0x1UL << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_EM3_Pos (3U)
+#define EXTI_EMR_EM3_Msk (0x1UL << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_EM4_Pos (4U)
+#define EXTI_EMR_EM4_Msk (0x1UL << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_EM5_Pos (5U)
+#define EXTI_EMR_EM5_Msk (0x1UL << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_EM6_Pos (6U)
+#define EXTI_EMR_EM6_Msk (0x1UL << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_EM7_Pos (7U)
+#define EXTI_EMR_EM7_Msk (0x1UL << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_EM8_Pos (8U)
+#define EXTI_EMR_EM8_Msk (0x1UL << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_EM9_Pos (9U)
+#define EXTI_EMR_EM9_Msk (0x1UL << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_EM10_Pos (10U)
+#define EXTI_EMR_EM10_Msk (0x1UL << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_EM11_Pos (11U)
+#define EXTI_EMR_EM11_Msk (0x1UL << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_EM12_Pos (12U)
+#define EXTI_EMR_EM12_Msk (0x1UL << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_EM13_Pos (13U)
+#define EXTI_EMR_EM13_Msk (0x1UL << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_EM14_Pos (14U)
+#define EXTI_EMR_EM14_Msk (0x1UL << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_EM15_Pos (15U)
+#define EXTI_EMR_EM15_Msk (0x1UL << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_EM16_Pos (16U)
+#define EXTI_EMR_EM16_Msk (0x1UL << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_EM17_Pos (17U)
+#define EXTI_EMR_EM17_Msk (0x1UL << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_EM18_Pos (18U)
+#define EXTI_EMR_EM18_Msk (0x1UL << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_EM19_Pos (19U)
+#define EXTI_EMR_EM19_Msk (0x1UL << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_EM20_Pos (20U)
+#define EXTI_EMR_EM20_Msk (0x1UL << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_EM21_Pos (21U)
+#define EXTI_EMR_EM21_Msk (0x1UL << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_EM22_Pos (22U)
+#define EXTI_EMR_EM22_Msk (0x1UL << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */
+#define EXTI_EMR_EM23_Pos (23U)
+#define EXTI_EMR_EM23_Msk (0x1UL << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
+#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
+#define EXTI_EMR_EM25_Pos (25U)
+#define EXTI_EMR_EM25_Msk (0x1UL << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */
+#define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */
+#define EXTI_EMR_EM26_Pos (26U)
+#define EXTI_EMR_EM26_Msk (0x1UL << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
+#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
+#define EXTI_EMR_EM28_Pos (28U)
+#define EXTI_EMR_EM28_Msk (0x1UL << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
+#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
+#define EXTI_EMR_EM29_Pos (29U)
+#define EXTI_EMR_EM29_Msk (0x1UL << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
+#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_RT0_Pos (0U)
+#define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_RT1_Pos (1U)
+#define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_RT2_Pos (2U)
+#define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_RT3_Pos (3U)
+#define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_RT4_Pos (4U)
+#define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_RT5_Pos (5U)
+#define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_RT6_Pos (6U)
+#define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_RT7_Pos (7U)
+#define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_RT8_Pos (8U)
+#define EXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_RT9_Pos (9U)
+#define EXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_RT10_Pos (10U)
+#define EXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_RT11_Pos (11U)
+#define EXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_RT12_Pos (12U)
+#define EXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_RT13_Pos (13U)
+#define EXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_RT14_Pos (14U)
+#define EXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_RT15_Pos (15U)
+#define EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_RT16_Pos (16U)
+#define EXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_RT17_Pos (17U)
+#define EXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_RT19_Pos (19U)
+#define EXTI_RTSR_RT19_Msk (0x1UL << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_RT20_Pos (20U)
+#define EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_RT21_Pos (21U)
+#define EXTI_RTSR_RT21_Msk (0x1UL << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_RT22_Pos (22U)
+#define EXTI_RTSR_RT22_Msk (0x1UL << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
+#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
+#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
+#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
+#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
+#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
+#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
+#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
+#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
+#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
+#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
+#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
+#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
+#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
+#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
+#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
+#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
+#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
+#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
+#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
+#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
+#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_FT0_Pos (0U)
+#define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_FT1_Pos (1U)
+#define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_FT2_Pos (2U)
+#define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_FT3_Pos (3U)
+#define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_FT4_Pos (4U)
+#define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_FT5_Pos (5U)
+#define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_FT6_Pos (6U)
+#define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_FT7_Pos (7U)
+#define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_FT8_Pos (8U)
+#define EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_FT9_Pos (9U)
+#define EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_FT10_Pos (10U)
+#define EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_FT11_Pos (11U)
+#define EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_FT12_Pos (12U)
+#define EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_FT13_Pos (13U)
+#define EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_FT14_Pos (14U)
+#define EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_FT15_Pos (15U)
+#define EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_FT16_Pos (16U)
+#define EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_FT17_Pos (17U)
+#define EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_FT19_Pos (19U)
+#define EXTI_FTSR_FT19_Msk (0x1UL << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_FT20_Pos (20U)
+#define EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_FT21_Pos (21U)
+#define EXTI_FTSR_FT21_Msk (0x1UL << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_FT22_Pos (22U)
+#define EXTI_FTSR_FT22_Msk (0x1UL << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
+#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
+#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
+#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
+#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
+#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
+#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
+#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
+#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
+#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
+#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
+#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
+#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
+#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
+#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
+#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
+#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
+#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
+#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
+#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
+#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
+#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWI0_Pos (0U)
+#define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWI1_Pos (1U)
+#define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWI2_Pos (2U)
+#define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWI3_Pos (3U)
+#define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWI4_Pos (4U)
+#define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWI5_Pos (5U)
+#define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWI6_Pos (6U)
+#define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWI7_Pos (7U)
+#define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWI8_Pos (8U)
+#define EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWI9_Pos (9U)
+#define EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWI10_Pos (10U)
+#define EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWI11_Pos (11U)
+#define EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWI12_Pos (12U)
+#define EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWI13_Pos (13U)
+#define EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWI14_Pos (14U)
+#define EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWI15_Pos (15U)
+#define EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWI16_Pos (16U)
+#define EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWI17_Pos (17U)
+#define EXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWI19_Pos (19U)
+#define EXTI_SWIER_SWI19_Msk (0x1UL << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWI20_Pos (20U)
+#define EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWI21_Pos (21U)
+#define EXTI_SWIER_SWI21_Msk (0x1UL << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWI22_Pos (22U)
+#define EXTI_SWIER_SWI22_Msk (0x1UL << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
+
+/* Legacy defines */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PIF0_Pos (0U)
+#define EXTI_PR_PIF0_Msk (0x1UL << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
+#define EXTI_PR_PIF1_Pos (1U)
+#define EXTI_PR_PIF1_Msk (0x1UL << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
+#define EXTI_PR_PIF2_Pos (2U)
+#define EXTI_PR_PIF2_Msk (0x1UL << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
+#define EXTI_PR_PIF3_Pos (3U)
+#define EXTI_PR_PIF3_Msk (0x1UL << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
+#define EXTI_PR_PIF4_Pos (4U)
+#define EXTI_PR_PIF4_Msk (0x1UL << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
+#define EXTI_PR_PIF5_Pos (5U)
+#define EXTI_PR_PIF5_Msk (0x1UL << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
+#define EXTI_PR_PIF6_Pos (6U)
+#define EXTI_PR_PIF6_Msk (0x1UL << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
+#define EXTI_PR_PIF7_Pos (7U)
+#define EXTI_PR_PIF7_Msk (0x1UL << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
+#define EXTI_PR_PIF8_Pos (8U)
+#define EXTI_PR_PIF8_Msk (0x1UL << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
+#define EXTI_PR_PIF9_Pos (9U)
+#define EXTI_PR_PIF9_Msk (0x1UL << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
+#define EXTI_PR_PIF10_Pos (10U)
+#define EXTI_PR_PIF10_Msk (0x1UL << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
+#define EXTI_PR_PIF11_Pos (11U)
+#define EXTI_PR_PIF11_Msk (0x1UL << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
+#define EXTI_PR_PIF12_Pos (12U)
+#define EXTI_PR_PIF12_Msk (0x1UL << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
+#define EXTI_PR_PIF13_Pos (13U)
+#define EXTI_PR_PIF13_Msk (0x1UL << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
+#define EXTI_PR_PIF14_Pos (14U)
+#define EXTI_PR_PIF14_Msk (0x1UL << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
+#define EXTI_PR_PIF15_Pos (15U)
+#define EXTI_PR_PIF15_Msk (0x1UL << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
+#define EXTI_PR_PIF16_Pos (16U)
+#define EXTI_PR_PIF16_Msk (0x1UL << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
+#define EXTI_PR_PIF17_Pos (17U)
+#define EXTI_PR_PIF17_Msk (0x1UL << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
+#define EXTI_PR_PIF19_Pos (19U)
+#define EXTI_PR_PIF19_Msk (0x1UL << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
+#define EXTI_PR_PIF20_Pos (20U)
+#define EXTI_PR_PIF20_Msk (0x1UL << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
+#define EXTI_PR_PIF21_Pos (21U)
+#define EXTI_PR_PIF21_Msk (0x1UL << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
+#define EXTI_PR_PIF22_Pos (22U)
+#define EXTI_PR_PIF22_Msk (0x1UL << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
+
+/* Legacy defines */
+#define EXTI_PR_PR0 EXTI_PR_PIF0
+#define EXTI_PR_PR1 EXTI_PR_PIF1
+#define EXTI_PR_PR2 EXTI_PR_PIF2
+#define EXTI_PR_PR3 EXTI_PR_PIF3
+#define EXTI_PR_PR4 EXTI_PR_PIF4
+#define EXTI_PR_PR5 EXTI_PR_PIF5
+#define EXTI_PR_PR6 EXTI_PR_PIF6
+#define EXTI_PR_PR7 EXTI_PR_PIF7
+#define EXTI_PR_PR8 EXTI_PR_PIF8
+#define EXTI_PR_PR9 EXTI_PR_PIF9
+#define EXTI_PR_PR10 EXTI_PR_PIF10
+#define EXTI_PR_PR11 EXTI_PR_PIF11
+#define EXTI_PR_PR12 EXTI_PR_PIF12
+#define EXTI_PR_PR13 EXTI_PR_PIF13
+#define EXTI_PR_PR14 EXTI_PR_PIF14
+#define EXTI_PR_PR15 EXTI_PR_PIF15
+#define EXTI_PR_PR16 EXTI_PR_PIF16
+#define EXTI_PR_PR17 EXTI_PR_PIF17
+#define EXTI_PR_PR19 EXTI_PR_PIF19
+#define EXTI_PR_PR20 EXTI_PR_PIF20
+#define EXTI_PR_PR21 EXTI_PR_PIF21
+#define EXTI_PR_PR22 EXTI_PR_PIF22
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
+#define FLASH_ACR_PRFTEN_Pos (1U)
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_SLEEP_PD_Pos (3U)
+#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD_Pos (4U)
+#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
+#define FLASH_ACR_DISAB_BUF_Pos (5U)
+#define FLASH_ACR_DISAB_BUF_Msk (0x1UL << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
+#define FLASH_ACR_PRE_READ_Pos (6U)
+#define FLASH_ACR_PRE_READ_Msk (0x1UL << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
+#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
+
+/******************* Bit definition for FLASH_PECR register ******************/
+#define FLASH_PECR_PELOCK_Pos (0U)
+#define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
+#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK_Pos (1U)
+#define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
+#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK_Pos (2U)
+#define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
+#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG_Pos (3U)
+#define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
+#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
+#define FLASH_PECR_DATA_Pos (4U)
+#define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
+#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
+#define FLASH_PECR_FIX_Pos (8U)
+#define FLASH_PECR_FIX_Msk (0x1UL << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
+#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE_Pos (9U)
+#define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
+#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
+#define FLASH_PECR_FPRG_Pos (10U)
+#define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
+#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_EOPIE_Pos (16U)
+#define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
+#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
+#define FLASH_PECR_ERRIE_Pos (17U)
+#define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
+#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
+#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
+#define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
+#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
+#define FLASH_PECR_HALF_ARRAY_Pos (19U)
+#define FLASH_PECR_HALF_ARRAY_Msk (0x1UL << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
+#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
+
+/****************** Bit definition for FLASH_PDKEYR register ******************/
+#define FLASH_PDKEYR_PDKEYR_Pos (0U)
+#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PEKEYR register ******************/
+#define FLASH_PEKEYR_PEKEYR_Pos (0U)
+#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PRGKEYR register ******************/
+#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
+#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
+
+/****************** Bit definition for FLASH_OPTKEYR register ******************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_EOP_Pos (1U)
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
+#define FLASH_SR_HVOFF_Pos (2U)
+#define FLASH_SR_HVOFF_Msk (0x1UL << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
+#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
+#define FLASH_SR_READY_Pos (3U)
+#define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */
+#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR_Pos (8U)
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
+#define FLASH_SR_PGAERR_Pos (9U)
+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR_Pos (10U)
+#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
+#define FLASH_SR_OPTVERR_Pos (11U)
+#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
+#define FLASH_SR_RDERR_Pos (13U)
+#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
+#define FLASH_SR_NOTZEROERR_Pos (16U)
+#define FLASH_SR_NOTZEROERR_Msk (0x1UL << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
+#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
+#define FLASH_SR_FWWERR_Pos (17U)
+#define FLASH_SR_FWWERR_Msk (0x1UL << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
+#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
+
+/* Legacy defines */
+#define FLASH_SR_FWWER FLASH_SR_FWWERR
+#define FLASH_SR_ENHV FLASH_SR_HVOFF
+#define FLASH_SR_ENDHV FLASH_SR_HVOFF
+
+/****************** Bit definition for FLASH_OPTR register *******************/
+#define FLASH_OPTR_RDPROT_Pos (0U)
+#define FLASH_OPTR_RDPROT_Msk (0xFFUL << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
+#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
+#define FLASH_OPTR_WPRMOD_Pos (8U)
+#define FLASH_OPTR_WPRMOD_Msk (0x1UL << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
+#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
+#define FLASH_OPTR_BOR_LEV_Pos (16U)
+#define FLASH_OPTR_BOR_LEV_Msk (0xFUL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
+#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OPTR_IWDG_SW_Pos (20U)
+#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
+#define FLASH_OPTR_nRST_STOP_Pos (21U)
+#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OPTR_nRST_STDBY_Pos (22U)
+#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OPTR_USER_Pos (20U)
+#define FLASH_OPTR_USER_Msk (0x7UL << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
+#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OPTR_BOOT1_Pos (31U)
+#define FLASH_OPTR_BOOT1_Msk (0x1UL << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
+#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 (0x00000001U)
+#define GPIO_OTYPER_OT_1 (0x00000002U)
+#define GPIO_OTYPER_OT_2 (0x00000004U)
+#define GPIO_OTYPER_OT_3 (0x00000008U)
+#define GPIO_OTYPER_OT_4 (0x00000010U)
+#define GPIO_OTYPER_OT_5 (0x00000020U)
+#define GPIO_OTYPER_OT_6 (0x00000040U)
+#define GPIO_OTYPER_OT_7 (0x00000080U)
+#define GPIO_OTYPER_OT_8 (0x00000100U)
+#define GPIO_OTYPER_OT_9 (0x00000200U)
+#define GPIO_OTYPER_OT_10 (0x00000400U)
+#define GPIO_OTYPER_OT_11 (0x00000800U)
+#define GPIO_OTYPER_OT_12 (0x00001000U)
+#define GPIO_OTYPER_OT_13 (0x00002000U)
+#define GPIO_OTYPER_OT_14 (0x00004000U)
+#define GPIO_OTYPER_OT_15 (0x00008000U)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDER_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
+#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDER_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
+#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDER_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
+#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDER_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
+#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDER_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
+#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDER_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
+#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDER_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
+#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDER_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
+#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDER_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
+#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDER_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
+#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDER_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
+#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDER_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
+#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDER_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
+#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDER_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
+#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDER_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
+#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDER_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
+#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 (0x00000001U)
+#define GPIO_BSRR_BS_1 (0x00000002U)
+#define GPIO_BSRR_BS_2 (0x00000004U)
+#define GPIO_BSRR_BS_3 (0x00000008U)
+#define GPIO_BSRR_BS_4 (0x00000010U)
+#define GPIO_BSRR_BS_5 (0x00000020U)
+#define GPIO_BSRR_BS_6 (0x00000040U)
+#define GPIO_BSRR_BS_7 (0x00000080U)
+#define GPIO_BSRR_BS_8 (0x00000100U)
+#define GPIO_BSRR_BS_9 (0x00000200U)
+#define GPIO_BSRR_BS_10 (0x00000400U)
+#define GPIO_BSRR_BS_11 (0x00000800U)
+#define GPIO_BSRR_BS_12 (0x00001000U)
+#define GPIO_BSRR_BS_13 (0x00002000U)
+#define GPIO_BSRR_BS_14 (0x00004000U)
+#define GPIO_BSRR_BS_15 (0x00008000U)
+#define GPIO_BSRR_BR_0 (0x00010000U)
+#define GPIO_BSRR_BR_1 (0x00020000U)
+#define GPIO_BSRR_BR_2 (0x00040000U)
+#define GPIO_BSRR_BR_3 (0x00080000U)
+#define GPIO_BSRR_BR_4 (0x00100000U)
+#define GPIO_BSRR_BR_5 (0x00200000U)
+#define GPIO_BSRR_BR_6 (0x00400000U)
+#define GPIO_BSRR_BR_7 (0x00800000U)
+#define GPIO_BSRR_BR_8 (0x01000000U)
+#define GPIO_BSRR_BR_9 (0x02000000U)
+#define GPIO_BSRR_BR_10 (0x04000000U)
+#define GPIO_BSRR_BR_11 (0x08000000U)
+#define GPIO_BSRR_BR_12 (0x10000000U)
+#define GPIO_BSRR_BR_13 (0x20000000U)
+#define GPIO_BSRR_BR_14 (0x40000000U)
+#define GPIO_BSRR_BR_15 (0x80000000U)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 (0x00000001U)
+#define GPIO_BRR_BR_1 (0x00000002U)
+#define GPIO_BRR_BR_2 (0x00000004U)
+#define GPIO_BRR_BR_3 (0x00000008U)
+#define GPIO_BRR_BR_4 (0x00000010U)
+#define GPIO_BRR_BR_5 (0x00000020U)
+#define GPIO_BRR_BR_6 (0x00000040U)
+#define GPIO_BRR_BR_7 (0x00000080U)
+#define GPIO_BRR_BR_8 (0x00000100U)
+#define GPIO_BRR_BR_9 (0x00000200U)
+#define GPIO_BRR_BR_10 (0x00000400U)
+#define GPIO_BRR_BR_11 (0x00000800U)
+#define GPIO_BRR_BR_12 (0x00001000U)
+#define GPIO_BRR_BR_13 (0x00002000U)
+#define GPIO_BRR_BR_14 (0x00004000U)
+#define GPIO_BRR_BR_15 (0x00008000U)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos (1U)
+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos (2U)
+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos (3U)
+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos (4U)
+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos (5U)
+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos (6U)
+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos (7U)
+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos (8U)
+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos (12U)
+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos (14U)
+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos (15U)
+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos (16U)
+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos (17U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos (18U)
+#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos (19U)
+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos (20U)
+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos (21U)
+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos (22U)
+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos (23U)
+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD_Pos (0U)
+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos (10U)
+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos (11U)
+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos (12U)
+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos (13U)
+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
+#define I2C_CR2_STOP_Pos (14U)
+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos (15U)
+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos (16U)
+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos (24U)
+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos (25U)
+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos (26U)
+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1_Pos (0U)
+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos (10U)
+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos (15U)
+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2_Pos (1U)
+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos (8U)
+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos (8U)
+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos (9U)
+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos (8U)
+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos (10U)
+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos (8U)
+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos (9U)
+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos (8U)
+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos (15U)
+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos (0U)
+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos (8U)
+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos (16U)
+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos (20U)
+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos (28U)
+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE_Pos (0U)
+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos (1U)
+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos (2U)
+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos (3U)
+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos (4U)
+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos (5U)
+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos (6U)
+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos (7U)
+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos (8U)
+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
+#define I2C_ISR_ARLO_Pos (9U)
+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos (10U)
+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos (11U)
+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos (12U)
+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos (13U)
+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos (15U)
+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
+#define I2C_ISR_DIR_Pos (16U)
+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos (17U)
+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF_Pos (3U)
+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos (4U)
+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos (5U)
+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos (8U)
+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos (9U)
+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos (10U)
+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos (11U)
+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos (12U)
+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos (13U)
+#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define I2C_PECR_PEC_Pos (0U)
+#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA_Pos (0U)
+#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA_Pos (0U)
+#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos (2U)
+#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN_Pos (0U)
+#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM_Pos (0U)
+#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos (1U)
+#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos (2U)
+#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos (3U)
+#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos (4U)
+#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos (5U)
+#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos (6U)
+#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF_Pos (0U)
+#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos (1U)
+#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos (3U)
+#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos (4U)
+#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos (5U)
+#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos (6U)
+#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos (0U)
+#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos (1U)
+#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos (3U)
+#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos (4U)
+#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos (5U)
+#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos (6U)
+#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos (0U)
+#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos (1U)
+#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos (3U)
+#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos (6U)
+#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos (9U)
+#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos (17U)
+#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos (19U)
+#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos (20U)
+#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos (21U)
+#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos (22U)
+#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos (24U)
+#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE_Pos (0U)
+#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos (1U)
+#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos (2U)
+#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP_Pos (0U)
+#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR_Pos (0U)
+#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT_Pos (0U)
+#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
+
+/******************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/******************************************************************************/
+
+#define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPSDSR_Pos (0U)
+#define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP_Pos (9U)
+#define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /*!< 0x00000200 */
+#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
+#define PWR_CR_FWU_Pos (10U)
+#define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /*!< 0x00000400 */
+#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
+
+#define PWR_CR_VOS_Pos (11U)
+#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x00001800 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /*!< 0x00000800 */
+#define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /*!< 0x00001000 */
+#define PWR_CR_DSEEKOFF_Pos (13U)
+#define PWR_CR_DSEEKOFF_Msk (0x1UL << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */
+#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */
+#define PWR_CR_LPRUN_Pos (14U)
+#define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
+#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF_Pos (3U)
+#define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
+#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF_Pos (4U)
+#define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
+#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF_Pos (5U)
+#define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
+#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1_Pos (8U)
+#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2_Pos (9U)
+#define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
+#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP3_Pos (10U)
+#define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
+#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos (1U)
+#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos (2U)
+#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIVEN_Pos (3U)
+#define RCC_CR_HSIDIVEN_Msk (0x1UL << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */
+#define RCC_CR_HSIDIVF_Pos (4U)
+#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */
+#define RCC_CR_HSIOUTEN_Pos (5U)
+#define RCC_CR_HSIOUTEN_Msk (0x1UL << RCC_CR_HSIOUTEN_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_Msk /*!< Internal High Speed clock out enable */
+#define RCC_CR_MSION_Pos (8U)
+#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000100 */
+#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY_Pos (9U)
+#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
+#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON_Pos (19U)
+#define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */
+#define RCC_CR_RTCPRE_Pos (20U)
+#define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
+#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */
+#define RCC_CR_RTCPRE_0 (0x1UL << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */
+#define RCC_CR_RTCPRE_1 (0x2UL << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+/* Reference defines */
+#define RCC_CR_CSSON RCC_CR_CSSHSEON
+
+/******************** Bit definition for RCC_ICSCR register *****************/
+#define RCC_ICSCR_HSICAL_Pos (0U)
+#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
+#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM_Pos (8U)
+#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
+#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE_Pos (13U)
+#define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
+#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
+#define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
+#define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
+#define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
+#define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
+#define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
+#define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
+#define RCC_ICSCR_MSICAL_Pos (16U)
+#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
+#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM_Pos (24U)
+#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
+#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos (15U)
+#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */
+
+/*!< PLL entry clock source*/
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
+
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL_Pos (18U)
+#define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV_Pos (22U)
+#define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
+
+#define RCC_CFGR_PLLDIV2_Pos (22U)
+#define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3_Pos (23U)
+#define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4_Pos (22U)
+#define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCOSEL_Pos (24U)
+#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
+#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
+
+#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
+#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCOSEL_HSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_MSI_Pos (24U)
+#define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
+#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_HSE_Pos (26U)
+#define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCOSEL_PLL_Pos (24U)
+#define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
+#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
+#define RCC_CFGR_MCOSEL_LSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
+#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
+#define RCC_CFGR_MCOSEL_LSE_Pos (24U)
+#define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
+
+#define RCC_CFGR_MCOPRE_Pos (28U)
+#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
+
+#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
+
+/* Legacy defines */
+#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
+#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
+#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
+#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
+#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
+#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
+#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
+#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
+#ifdef RCC_CFGR_MCOSEL_HSI48
+#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48
+#endif
+
+#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
+#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
+
+/*!<****************** Bit definition for RCC_CIER register ********************/
+#define RCC_CIER_LSIRDYIE_Pos (0U)
+#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIER_LSERDYIE_Pos (1U)
+#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIER_HSIRDYIE_Pos (2U)
+#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIER_HSERDYIE_Pos (3U)
+#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIER_PLLRDYIE_Pos (4U)
+#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIER_MSIRDYIE_Pos (5U)
+#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
+#define RCC_CIER_CSSLSE_Pos (7U)
+#define RCC_CIER_CSSLSE_Msk (0x1UL << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */
+
+/* Reference defines */
+#define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
+
+/*!<****************** Bit definition for RCC_CIFR register ********************/
+#define RCC_CIFR_LSIRDYF_Pos (0U)
+#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIFR_LSERDYF_Pos (1U)
+#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIFR_HSIRDYF_Pos (2U)
+#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIFR_HSERDYF_Pos (3U)
+#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIFR_PLLRDYF_Pos (4U)
+#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIFR_MSIRDYF_Pos (5U)
+#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
+#define RCC_CIFR_CSSLSEF_Pos (7U)
+#define RCC_CIFR_CSSLSEF_Msk (0x1UL << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */
+#define RCC_CIFR_CSSHSEF_Pos (8U)
+#define RCC_CIFR_CSSHSEF_Msk (0x1UL << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */
+#define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */
+
+/* Reference defines */
+#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
+#define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
+
+/*!<****************** Bit definition for RCC_CICR register ********************/
+#define RCC_CICR_LSIRDYC_Pos (0U)
+#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CICR_LSERDYC_Pos (1U)
+#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CICR_HSIRDYC_Pos (2U)
+#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CICR_HSERDYC_Pos (3U)
+#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CICR_PLLRDYC_Pos (4U)
+#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CICR_MSIRDYC_Pos (5U)
+#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
+#define RCC_CICR_CSSLSEC_Pos (7U)
+#define RCC_CICR_CSSLSEC_Msk (0x1UL << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */
+#define RCC_CICR_CSSHSEC_Pos (8U)
+#define RCC_CICR_CSSHSEC_Msk (0x1UL << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */
+#define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */
+
+/* Reference defines */
+#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
+#define RCC_CICR_CSSC RCC_CICR_CSSHSEC
+/***************** Bit definition for RCC_IOPRSTR register ******************/
+#define RCC_IOPRSTR_IOPARST_Pos (0U)
+#define RCC_IOPRSTR_IOPARST_Msk (0x1UL << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */
+#define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */
+#define RCC_IOPRSTR_IOPBRST_Pos (1U)
+#define RCC_IOPRSTR_IOPBRST_Msk (0x1UL << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */
+#define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */
+#define RCC_IOPRSTR_IOPCRST_Pos (2U)
+#define RCC_IOPRSTR_IOPCRST_Msk (0x1UL << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */
+#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */
+#define RCC_IOPRSTR_IOPHRST_Pos (7U)
+#define RCC_IOPRSTR_IOPHRST_Msk (0x1UL << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */
+#define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */
+
+/* Reference defines */
+#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
+#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
+#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
+#define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
+
+
+/****************** Bit definition for RCC_AHBRST register ******************/
+#define RCC_AHBRSTR_DMARST_Pos (0U)
+#define RCC_AHBRSTR_DMARST_Msk (0x1UL << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */
+#define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */
+#define RCC_AHBRSTR_MIFRST_Pos (8U)
+#define RCC_AHBRSTR_MIFRST_Msk (0x1UL << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */
+#define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset */
+#define RCC_AHBRSTR_CRCRST_Pos (12U)
+#define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */
+#define RCC_AHBRSTR_CRYPRST_Pos (24U)
+#define RCC_AHBRSTR_CRYPRST_Msk (0x1UL << RCC_AHBRSTR_CRYPRST_Pos) /*!< 0x01000000 */
+#define RCC_AHBRSTR_CRYPRST RCC_AHBRSTR_CRYPRST_Msk /*!< Crypto reset */
+
+/* Reference defines */
+#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
+#define RCC_APB2RSTR_TIM21RST_Pos (2U)
+#define RCC_APB2RSTR_TIM21RST_Msk (0x1UL << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 reset */
+#define RCC_APB2RSTR_TIM22RST_Pos (5U)
+#define RCC_APB2RSTR_TIM22RST_Msk (0x1UL << RCC_APB2RSTR_TIM22RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk /*!< TIM22 reset */
+#define RCC_APB2RSTR_ADCRST_Pos (9U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
+#define RCC_APB2RSTR_DBGRST_Pos (22U)
+#define RCC_APB2RSTR_DBGRST_Msk (0x1UL << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU reset */
+
+/* Reference defines */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 reset */
+#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU reset */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_LPUART1RST_Pos (18U)
+#define RCC_APB1RSTR_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
+#define RCC_APB1RSTR_LPTIM1RST_Pos (31U)
+#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 reset */
+
+/***************** Bit definition for RCC_IOPENR register ******************/
+#define RCC_IOPENR_IOPAEN_Pos (0U)
+#define RCC_IOPENR_IOPAEN_Msk (0x1UL << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */
+#define RCC_IOPENR_IOPBEN_Pos (1U)
+#define RCC_IOPENR_IOPBEN_Msk (0x1UL << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */
+#define RCC_IOPENR_IOPCEN_Pos (2U)
+#define RCC_IOPENR_IOPCEN_Msk (0x1UL << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */
+#define RCC_IOPENR_IOPHEN_Pos (7U)
+#define RCC_IOPENR_IOPHEN_Msk (0x1UL << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */
+
+/* Reference defines */
+#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
+#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
+#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
+#define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
+
+/***************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMAEN_Pos (0U)
+#define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_MIFEN_Pos (8U)
+#define RCC_AHBENR_MIFEN_Msk (0x1UL << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */
+#define RCC_AHBENR_CRCEN_Pos (12U)
+#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+#define RCC_AHBENR_CRYPEN_Pos (24U)
+#define RCC_AHBENR_CRYPEN_Msk (0x1UL << RCC_AHBENR_CRYPEN_Pos) /*!< 0x01000000 */
+#define RCC_AHBENR_CRYPEN RCC_AHBENR_CRYPEN_Msk /*!< Crypto clock enable*/
+
+/* Reference defines */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register ******************/
+#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM21EN_Pos (2U)
+#define RCC_APB2ENR_TIM21EN_Msk (0x1UL << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */
+#define RCC_APB2ENR_TIM22EN_Pos (5U)
+#define RCC_APB2ENR_TIM22EN_Msk (0x1UL << RCC_APB2ENR_TIM22EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk /*!< TIM22 clock enable */
+#define RCC_APB2ENR_FWEN_Pos (7U)
+#define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADCEN_Pos (9U)
+#define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
+#define RCC_APB2ENR_DBGEN_Pos (22U)
+#define RCC_APB2ENR_DBGEN_Msk (0x1UL << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */
+
+/* Reference defines */
+
+#define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
+#define RCC_APB1ENR_LPUART1EN_Pos (18U)
+#define RCC_APB1ENR_LPUART1EN_Msk (0x1UL << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
+#define RCC_APB1ENR_LPTIM1EN_Pos (31U)
+#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */
+
+/****************** Bit definition for RCC_IOPSMENR register ****************/
+#define RCC_IOPSMENR_IOPASMEN_Pos (0U)
+#define RCC_IOPSMENR_IOPASMEN_Msk (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPBSMEN_Pos (1U)
+#define RCC_IOPSMENR_IOPBSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPCSMEN_Pos (2U)
+#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPHSMEN_Pos (7U)
+#define RCC_IOPSMENR_IOPHSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_AHBSMENR register ******************/
+#define RCC_AHBSMENR_DMASMEN_Pos (0U)
+#define RCC_AHBSMENR_DMASMEN_Msk (0x1UL << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */
+#define RCC_AHBSMENR_MIFSMEN_Pos (8U)
+#define RCC_AHBSMENR_MIFSMEN_Msk (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */
+#define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
+#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRCSMEN_Pos (12U)
+#define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRYPSMEN_Pos (24U)
+#define RCC_AHBSMENR_CRYPSMEN_Msk (0x1UL << RCC_AHBSMENR_CRYPSMEN_Pos) /*!< 0x01000000 */
+#define RCC_AHBSMENR_CRYPSMEN RCC_AHBSMENR_CRYPSMEN_Msk /*!< Crypto clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB2SMENR register ******************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM21SMEN_Pos (2U)
+#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM22SMEN_Pos (5U)
+#define RCC_APB2SMENR_TIM22SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk /*!< TIM22 clock enabled in sleep mode */
+#define RCC_APB2SMENR_ADCSMEN_Pos (9U)
+#define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
+#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGSMEN_Pos (22U)
+#define RCC_APB2SMENR_DBGSMEN_Msk (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB1SMENR register ******************/
+#define RCC_APB1SMENR_TIM2SMEN_Pos (0U)
+#define RCC_APB1SMENR_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_WWDGSMEN_Pos (11U)
+#define RCC_APB1SMENR_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART2SMEN_Pos (17U)
+#define RCC_APB1SMENR_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPUART1SMEN_Pos (18U)
+#define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C1SMEN_Pos (21U)
+#define RCC_APB1SMENR_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_PWRSMEN_Pos (28U)
+#define RCC_APB1SMENR_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U)
+#define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */
+
+/*!< USART2 Clock source selection */
+#define RCC_CCIPR_USART2SEL_Pos (2U)
+#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */
+#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+/*!< LPUART1 Clock source selection */
+#define RCC_CCIPR_LPUART1SEL_Pos (10U)
+#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */
+#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */
+#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CCIPR_I2C1SEL_Pos (12U)
+#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */
+#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
+
+
+/*!< LPTIM1 Clock source selection */
+#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
+#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */
+#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+/******************* Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSEON_Pos (8U)
+#define RCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */
+#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_CSR_LSERDY_Pos (9U)
+#define RCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */
+#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP_Pos (10U)
+#define RCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */
+#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_CSR_LSEDRV_Pos (11U)
+#define RCC_CSR_LSEDRV_Msk (0x3UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */
+#define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_CSR_LSEDRV_0 (0x1UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */
+#define RCC_CSR_LSEDRV_1 (0x2UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */
+
+#define RCC_CSR_LSECSSON_Pos (13U)
+#define RCC_CSR_LSECSSON_Msk (0x1UL << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */
+#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */
+#define RCC_CSR_LSECSSD_Pos (14U)
+#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
+#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
+
+/*!< RTC congiguration */
+#define RCC_CSR_RTCSEL_Pos (16U)
+#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
+
+#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CSR_RTCSEL_LSE_Pos (16U)
+#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_LSI_Pos (17U)
+#define RCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */
+#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_HSE_Pos (16U)
+#define RCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */
+
+#define RCC_CSR_RTCEN_Pos (18U)
+#define RCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */
+#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_CSR_RTCRST_Pos (19U)
+#define RCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */
+#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */
+
+#define RCC_CSR_RMVF_Pos (23U)
+#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_FWRSTF_Pos (24U)
+#define RCC_CSR_FWRSTF_Msk (0x1UL << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk /*!< Mifare Firewall reset flag */
+#define RCC_CSR_OBLRSTF_Pos (25U)
+#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+/* Reference defines */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER1_SUPPORT
+#define RTC_TAMPER2_SUPPORT
+#define RTC_TAMPER3_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk /*!< */
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk /*!< */
+#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk /*!< */
+#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */
+#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */
+#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk /*!< */
+#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk /*!< */
+#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk /*!< */
+#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk /*!< */
+#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */
+#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk /*!< */
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk /*!< */
+#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk /*!< */
+#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk /*!< */
+#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk /*!< */
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */
+#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk /*!< */
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< */
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */
+#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */
+#define RTC_ISR_TAMP3F_Pos (15U)
+#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk /*!< */
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */
+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */
+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */
+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */
+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */
+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */
+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */
+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */
+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */
+#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */
+#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */
+#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */
+#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */
+#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */
+#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */
+#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */
+#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */
+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */
+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */
+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */
+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */
+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */
+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */
+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */
+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */
+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */
+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CALR register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */
+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define RTC_CAL_CALP RTC_CALR_CALP
+#define RTC_CAL_CALW8 RTC_CALR_CALW8
+#define RTC_CAL_CALW16 RTC_CALR_CALW16
+#define RTC_CAL_CALM RTC_CALR_CALM
+#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
+
+/******************** Bits definition for RTC_TAMPCR register ****************/
+#define RTC_TAMPCR_TAMP3MF_Pos (24U)
+#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
+#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
+#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
+#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP3IE_Pos (22U)
+#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
+#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2MF_Pos (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2IE_Pos (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1MF_Pos (18U)
+#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
+#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1IE_Pos (16U)
+#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */
+#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */
+#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */
+#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos (7U)
+#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */
+#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
+#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
+#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP3E_Pos (5U)
+#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
+#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk /*!< */
+#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP2E_Pos (3U)
+#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */
+#define RTC_TAMPCR_TAMPIE_Pos (2U)
+#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
+#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP1E_Pos (0U)
+#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_OR register ****************/
+#define RTC_OR_OUT_RMP_Pos (1U)
+#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */
+#define RTC_OR_ALARMOUTTYPE_Pos (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */
+
+/* Legacy defines */
+#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk /*!< */
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER (0x00000005U) /*!< */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/******************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
+#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR1_BOOT_MODE_Pos (8U)
+#define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
+#define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */
+#define SYSCFG_CFGR1_BOOT_MODE_0 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOT_MODE_1 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_FWDISEN_Pos (0U)
+#define SYSCFG_CFGR2_FWDISEN_Msk (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos (8U)
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR2_I2C_PB6_FMP SYSCFG_CFGR2_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos (9U)
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR2_I2C_PB7_FMP SYSCFG_CFGR2_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos (10U)
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
+#define SYSCFG_CFGR2_I2C_PB8_FMP SYSCFG_CFGR2_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos (11U)
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
+#define SYSCFG_CFGR2_I2C_PB9_FMP SYSCFG_CFGR2_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR2_I2C1_FMP_Pos (12U)
+#define SYSCFG_CFGR2_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR2_I2C1_FMP SYSCFG_CFGR2_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
+
+
+/***************** Bit definition for SYSCFG_CFGR3 register ****************/
+#define SYSCFG_CFGR3_EN_VREFINT_Pos (0U)
+#define SYSCFG_CFGR3_EN_VREFINT_Msk (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_EN_VREFINT SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
+#define SYSCFG_CFGR3_VREF_OUT_Pos (4U)
+#define SYSCFG_CFGR3_VREF_OUT_Msk (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
+#define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */
+#define SYSCFG_CFGR3_VREF_OUT_0 (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
+#define SYSCFG_CFGR3_VREF_OUT_1 (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U)
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U)
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U)
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
+#define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U)
+#define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
+#define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
+#define SYSCFG_CFGR3_REF_LOCK_Pos (31U)
+#define SYSCFG_CFGR3_REF_LOCK_Msk (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
+#define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */
+
+/* Legacy defines */
+
+#define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
+#define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
+#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
+#define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+
+/******************************************************************************/
+/* */
+/* Timers (TIM)*/
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
+#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
+ || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#else
+#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
+#endif
+
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFUL << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFUL << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM2_OR_ETR_RMP_Pos (0U)
+#define TIM2_OR_ETR_RMP_Msk (0x7UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000007 */
+#define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
+#define TIM2_OR_ETR_RMP_0 (0x1UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM2_OR_ETR_RMP_1 (0x2UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM2_OR_ETR_RMP_2 (0x4UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000004 */
+#define TIM2_OR_TI4_RMP_Pos (3U)
+#define TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000018 */
+#define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
+#define TIM2_OR_TI4_RMP_0 (0x1UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */
+#define TIM2_OR_TI4_RMP_1 (0x2UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000010 */
+
+#define TIM21_OR_ETR_RMP_Pos (0U)
+#define TIM21_OR_ETR_RMP_Msk (0x3UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
+#define TIM21_OR_ETR_RMP_0 (0x1UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM21_OR_ETR_RMP_1 (0x2UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM21_OR_TI1_RMP_Pos (2U)
+#define TIM21_OR_TI1_RMP_Msk (0x7UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x0000001C */
+#define TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
+#define TIM21_OR_TI1_RMP_0 (0x1UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM21_OR_TI1_RMP_1 (0x2UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+#define TIM21_OR_TI1_RMP_2 (0x4UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000010 */
+#define TIM21_OR_TI2_RMP_Pos (5U)
+#define TIM21_OR_TI2_RMP_Msk (0x1UL << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */
+#define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */
+
+#define TIM22_OR_ETR_RMP_Pos (0U)
+#define TIM22_OR_ETR_RMP_Msk (0x3UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM22_OR_ETR_RMP TIM22_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
+#define TIM22_OR_ETR_RMP_0 (0x1UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM22_OR_ETR_RMP_1 (0x2UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM22_OR_TI1_RMP_Pos (2U)
+#define TIM22_OR_TI1_RMP_Msk (0x3UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x0000000C */
+#define TIM22_OR_TI1_RMP TIM22_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
+#define TIM22_OR_TI1_RMP_0 (0x1UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM22_OR_TI1_RMP_1 (0x2UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE_Pos (0U)
+#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+#define USART_CR1_UESM_Pos (1U)
+#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
+#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_M0_Pos (12U)
+#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
+#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos (13U)
+#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos (14U)
+#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos (16U)
+#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
+#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
+#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
+#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
+#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos (21U)
+#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
+#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
+#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
+#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
+#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos (26U)
+#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos (27U)
+#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos (28U)
+#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
+#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7_Pos (4U)
+#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos (15U)
+#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos (16U)
+#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos (17U)
+#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos (18U)
+#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos (19U)
+#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos (20U)
+#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos (21U)
+#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos (23U)
+#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos (24U)
+#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos (12U)
+#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos (13U)
+#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos (14U)
+#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos (15U)
+#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos (17U)
+#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos (20U)
+#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
+#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
+#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos (22U)
+#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
+#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
+#define USART_CR3_UCESM_Pos (23U)
+#define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
+#define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION_Pos (0U)
+#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos (4U)
+#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO_Pos (0U)
+#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos (24U)
+#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ_Pos (0U)
+#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
+#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos (1U)
+#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
+#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos (2U)
+#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
+#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos (3U)
+#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
+#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos (4U)
+#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
+#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE_Pos (0U)
+#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
+#define USART_ISR_FE_Pos (1U)
+#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
+#define USART_ISR_NE_Pos (2U)
+#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos (3U)
+#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos (4U)
+#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos (5U)
+#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos (6U)
+#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos (7U)
+#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
+#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos (8U)
+#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos (9U)
+#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos (10U)
+#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
+#define USART_ISR_RTOF_Pos (11U)
+#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos (12U)
+#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos (14U)
+#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos (15U)
+#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos (16U)
+#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
+#define USART_ISR_CMF_Pos (17U)
+#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos (18U)
+#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos (19U)
+#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos (20U)
+#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
+#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos (21U)
+#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos (22U)
+#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
+#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF_Pos (0U)
+#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos (1U)
+#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos (2U)
+#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */
+#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos (3U)
+#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos (4U)
+#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos (6U)
+#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF_Pos (8U)
+#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos (9U)
+#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos (11U)
+#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos (12U)
+#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos (17U)
+#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos (20U)
+#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
+#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
+
+/* Compatibility defines with other series */
+#define USART_ICR_NECF USART_ICR_NCF
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR_Pos (0U)
+#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR_Pos (0U)
+#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+/******************************* AES Instances ********************************/
+#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
+
+/******************************* COMP Instances *******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+ ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOH))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
+
+
+
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SMBUS Instances *****************************/
+#define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/************* LPTIM instances supporting the encoder mode feature ************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM21) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM22) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/******************* TIM Instances : output(s) OCXEC register *****************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/****************** USART Instances : Auto Baud Rate detection ****************/
+
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32L0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32L0 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+
+#define RNG_LPUART1_IRQn AES_LPUART1_IRQn
+#define LPUART1_IRQn AES_LPUART1_IRQn
+#define AES_RNG_LPUART1_IRQn AES_LPUART1_IRQn
+#define RCC_CRS_IRQn RCC_IRQn
+#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
+#define ADC1_IRQn ADC1_COMP_IRQn
+
+/* Aliases for __IRQHandler */
+#define LPUART1_IRQHandler AES_LPUART1_IRQHandler
+#define RNG_LPUART1_IRQHandler AES_LPUART1_IRQHandler
+#define AES_RNG_LPUART1_IRQHandler AES_LPUART1_IRQHandler
+#define RCC_CRS_IRQHandler RCC_IRQHandler
+#define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
+#define ADC1_IRQHandler ADC1_COMP_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L041xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/CMSIS/device/stm32l051xx.h b/CMSIS/device/stm32l051xx.h
new file mode 100644
index 0000000..516db35
--- /dev/null
+++ b/CMSIS/device/stm32l051xx.h
@@ -0,0 +1,6265 @@
+/**
+ ******************************************************************************
+ * @file stm32l051xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for stm32l051xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright(c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l051xx
+ * @{
+ */
+
+#ifndef __STM32L051xx_H
+#define __STM32L051xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 1U /*!< STM32L0xx provides an MPU */
+#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
+#define __NVIC_PRIO_BITS 2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief stm32l051xx Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+/*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
+
+/****** STM32L-0 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */
+ RCC_IRQn = 4, /*!< RCC Interrupt */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
+ ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
+ LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 Interrupt */
+ TIM6_IRQn = 17, /*!< TIM6 Interrupt */
+ TIM21_IRQn = 20, /*!< TIM21 Interrupt */
+ TIM22_IRQn = 22, /*!< TIM22 Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */
+ I2C2_IRQn = 24, /*!< I2C2 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ SPI2_IRQn = 26, /*!< SPI2 Interrupt */
+ USART1_IRQn = 27, /*!< USART1 Interrupt */
+ USART2_IRQn = 28, /*!< USART2 Interrupt */
+ LPUART1_IRQn = 29, /*!< LPUART1 Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0plus.h"
+#include "system_stm32l0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+ uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Comparator
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
+} COMP_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+
+/**
+* @brief CRC calculation unit
+*/
+
+typedef struct
+{
+__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+uint8_t RESERVED0; /*!< Reserved, 0x05 */
+uint16_t RESERVED1; /*!< Reserved, 0x06 */
+__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+uint32_t RESERVED2; /*!< Reserved, 0x0C */
+__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
+} DMA_Request_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
+ __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
+ __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
+ __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
+ __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
+ __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
+ __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
+ __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
+ __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
+ __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
+} OB_TypeDef;
+
+
+/**
+ * @brief General Purpose IO
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief LPTIMIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+} LPTIM_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+ * @brief Independent WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief MIFARE Firewall
+ */
+typedef struct
+{
+ __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
+ __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
+ __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
+ __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
+ __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
+ __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
+ __IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x18 */
+ __IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */
+ __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
+
+} FIREWALL_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
+ __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
+ __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
+ __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
+ __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
+ __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
+ __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
+ __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
+ __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
+ __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
+ __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */
+
+#define DATA_EEPROM_BASE (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
+#define DATA_EEPROM_END (0x080807FFUL) /*!< DATA EEPROM end address in the alias region */
+#define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */
+#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8KBytes) */
+
+#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000UL)
+
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL)
+#define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
+#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
+#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800UL)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
+#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
+#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL)
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
+#define COMP1_BASE (APBPERIPH_BASE + 0x00010018UL)
+#define COMP2_BASE (APBPERIPH_BASE + 0x0001001CUL)
+#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL)
+#define TIM21_BASE (APBPERIPH_BASE + 0x00010800UL)
+#define TIM22_BASE (APBPERIPH_BASE + 0x00011400UL)
+#define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00UL)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708UL)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
+#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
+#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL)
+
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
+#define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */
+#define FLASHSIZE_BASE (0x1FF8007CUL) /*!< FLASH Size register base address */
+#define UID_BASE (0x1FF80050UL) /*!< Unique device ID register base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
+
+#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL)
+#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL)
+#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL)
+#define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00UL)
+#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00UL)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
+#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
+#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
+/* Legacy defines */
+#define ADC ADC1_COMMON
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_EOCAL_Pos (11U)
+#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
+#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
+#define ADC_ISR_AWD_Pos (7U)
+#define ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
+#define ADC_ISR_EOSEQ_Pos (3U)
+#define ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_EOCALIE_Pos (11U)
+#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
+#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
+#define ADC_IER_AWDIE_Pos (7U)
+#define ADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE_Pos (3U)
+#define ADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH_Pos (26U)
+#define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
+#define ADC_CFGR1_AWDEN_Pos (23U)
+#define ADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL_Pos (22U)
+#define ADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN_Pos (16U)
+#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF_Pos (15U)
+#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
+#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT_Pos (14U)
+#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
+#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT_Pos (13U)
+#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD_Pos (12U)
+#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN_Pos (10U)
+#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
+#define ADC_CFGR1_EXTSEL_Pos (6U)
+#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
+#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
+#define ADC_CFGR1_ALIGN_Pos (5U)
+#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
+#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
+#define ADC_CFGR1_RES_Pos (3U)
+#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
+#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
+#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
+#define ADC_CFGR1_SCANDIR_Pos (2U)
+#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG_Pos (1U)
+#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
+#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN_Pos (0U)
+#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
+#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_TOVS_Pos (9U)
+#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
+#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+#define ADC_CFGR2_OVSR_Pos (2U)
+#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
+#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+#define ADC_CFGR2_OVSE_Pos (0U)
+#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
+#define ADC_CFGR2_CKMODE_Pos (30U)
+#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
+#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
+#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
+#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
+
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP_Pos (0U)
+#define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
+#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
+#define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
+#define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define ADC_SMPR_SMPR ADC_SMPR_SMP
+#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
+#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
+#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT_Pos (16U)
+#define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
+#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
+#define ADC_TR_LT_Pos (0U)
+#define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL_Pos (0U)
+#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
+#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
+#define ADC_CHSELR_CHSEL18_Pos (18U)
+#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17_Pos (17U)
+#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
+#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL15_Pos (15U)
+#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
+#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14_Pos (14U)
+#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
+#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13_Pos (13U)
+#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
+#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12_Pos (12U)
+#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
+#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11_Pos (11U)
+#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
+#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10_Pos (10U)
+#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
+#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9_Pos (9U)
+#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
+#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8_Pos (8U)
+#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
+#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7_Pos (7U)
+#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
+#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6_Pos (6U)
+#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
+#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5_Pos (5U)
+#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
+#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4_Pos (4U)
+#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
+#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3_Pos (3U)
+#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
+#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2_Pos (2U)
+#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
+#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1_Pos (1U)
+#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
+#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0_Pos (0U)
+#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
+#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_CALFACT_Pos (0U)
+#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_LFMEN_Pos (25U)
+#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
+#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
+#define ADC_CCR_TSEN_Pos (23U)
+#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+/************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN_Pos (0U)
+#define COMP_CSR_COMP1EN_Msk (0x1UL << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
+#define COMP_CSR_COMP1INNSEL_Pos (4U)
+#define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
+#define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP1WM_Pos (8U)
+#define COMP_CSR_COMP1WM_Msk (0x1UL << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */
+#define COMP_CSR_COMP1LPTIM1IN1_Pos (12U)
+#define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP1POLARITY_Pos (15U)
+#define COMP_CSR_COMP1POLARITY_Msk (0x1UL << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1VALUE_Pos (30U)
+#define COMP_CSR_COMP1VALUE_Msk (0x1UL << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK_Pos (31U)
+#define COMP_CSR_COMP1LOCK_Msk (0x1UL << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN_Pos (0U)
+#define COMP_CSR_COMP2EN_Msk (0x1UL << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
+#define COMP_CSR_COMP2SPEED_Pos (3U)
+#define COMP_CSR_COMP2SPEED_Msk (0x1UL << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */
+#define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */
+#define COMP_CSR_COMP2INNSEL_Pos (4U)
+#define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */
+#define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
+#define COMP_CSR_COMP2INPSEL_Pos (8U)
+#define COMP_CSR_COMP2INPSEL_Msk (0x7UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */
+#define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2INPSEL_0 (0x1UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP2INPSEL_1 (0x2UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */
+#define COMP_CSR_COMP2INPSEL_2 (0x4UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */
+#define COMP_CSR_COMP2LPTIM1IN2_Pos (12U)
+#define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */
+#define COMP_CSR_COMP2LPTIM1IN1_Pos (13U)
+#define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */
+#define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP2POLARITY_Pos (15U)
+#define COMP_CSR_COMP2POLARITY_Msk (0x1UL << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2VALUE_Pos (30U)
+#define COMP_CSR_COMP2VALUE_Msk (0x1UL << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK_Pos (31U)
+#define COMP_CSR_COMP2LOCK_Msk (0x1UL << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
+
+/********************** Bit definition for COMP_CSR register common ****************/
+#define COMP_CSR_COMPxEN_Pos (0U)
+#define COMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
+#define COMP_CSR_COMPxPOLARITY_Pos (15U)
+#define COMP_CSR_COMPxPOLARITY_Msk (0x1UL << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */
+#define COMP_CSR_COMPxOUTVALUE_Pos (30U)
+#define COMP_CSR_COMPxOUTVALUE_Msk (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK_Pos (31U)
+#define COMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
+
+/* Reference defines */
+#define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR (0xFFU) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos (3U)
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos (5U)
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos (7U)
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT_Pos (0U)
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL_Pos (0U)
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_Pos (0U)
+#define DBGMCU_CR_DBG_Msk (0x7UL << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
+#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+
+/******************* Bit definition for DMA_CSELR register *******************/
+#define DMA_CSELR_C1S_Pos (0U)
+#define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
+#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos (4U)
+#define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
+#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos (8U)
+#define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
+#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos (12U)
+#define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
+#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos (16U)
+#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
+#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S_Pos (20U)
+#define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
+#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S_Pos (24U)
+#define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
+#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_IM0_Pos (0U)
+#define EXTI_IMR_IM0_Msk (0x1UL << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_IM1_Pos (1U)
+#define EXTI_IMR_IM1_Msk (0x1UL << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_IM2_Pos (2U)
+#define EXTI_IMR_IM2_Msk (0x1UL << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_IM3_Pos (3U)
+#define EXTI_IMR_IM3_Msk (0x1UL << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_IM4_Pos (4U)
+#define EXTI_IMR_IM4_Msk (0x1UL << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_IM5_Pos (5U)
+#define EXTI_IMR_IM5_Msk (0x1UL << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_IM6_Pos (6U)
+#define EXTI_IMR_IM6_Msk (0x1UL << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_IM7_Pos (7U)
+#define EXTI_IMR_IM7_Msk (0x1UL << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_IM8_Pos (8U)
+#define EXTI_IMR_IM8_Msk (0x1UL << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_IM9_Pos (9U)
+#define EXTI_IMR_IM9_Msk (0x1UL << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_IM10_Pos (10U)
+#define EXTI_IMR_IM10_Msk (0x1UL << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_IM11_Pos (11U)
+#define EXTI_IMR_IM11_Msk (0x1UL << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_IM12_Pos (12U)
+#define EXTI_IMR_IM12_Msk (0x1UL << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_IM13_Pos (13U)
+#define EXTI_IMR_IM13_Msk (0x1UL << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_IM14_Pos (14U)
+#define EXTI_IMR_IM14_Msk (0x1UL << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_IM15_Pos (15U)
+#define EXTI_IMR_IM15_Msk (0x1UL << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_IM16_Pos (16U)
+#define EXTI_IMR_IM16_Msk (0x1UL << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_IM17_Pos (17U)
+#define EXTI_IMR_IM17_Msk (0x1UL << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_IM18_Pos (18U)
+#define EXTI_IMR_IM18_Msk (0x1UL << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_IM19_Pos (19U)
+#define EXTI_IMR_IM19_Msk (0x1UL << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_IM20_Pos (20U)
+#define EXTI_IMR_IM20_Msk (0x1UL << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_IM21_Pos (21U)
+#define EXTI_IMR_IM21_Msk (0x1UL << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_IM22_Pos (22U)
+#define EXTI_IMR_IM22_Msk (0x1UL << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_IM23_Pos (23U)
+#define EXTI_IMR_IM23_Msk (0x1UL << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
+#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_IM25_Pos (25U)
+#define EXTI_IMR_IM25_Msk (0x1UL << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */
+#define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_IM26_Pos (26U)
+#define EXTI_IMR_IM26_Msk (0x1UL << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
+#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_IM28_Pos (28U)
+#define EXTI_IMR_IM28_Msk (0x1UL << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
+#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_IM29_Pos (29U)
+#define EXTI_IMR_IM29_Msk (0x1UL << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
+#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
+
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x36FFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x36FFFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_EM0_Pos (0U)
+#define EXTI_EMR_EM0_Msk (0x1UL << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_EM1_Pos (1U)
+#define EXTI_EMR_EM1_Msk (0x1UL << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_EM2_Pos (2U)
+#define EXTI_EMR_EM2_Msk (0x1UL << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_EM3_Pos (3U)
+#define EXTI_EMR_EM3_Msk (0x1UL << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_EM4_Pos (4U)
+#define EXTI_EMR_EM4_Msk (0x1UL << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_EM5_Pos (5U)
+#define EXTI_EMR_EM5_Msk (0x1UL << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_EM6_Pos (6U)
+#define EXTI_EMR_EM6_Msk (0x1UL << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_EM7_Pos (7U)
+#define EXTI_EMR_EM7_Msk (0x1UL << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_EM8_Pos (8U)
+#define EXTI_EMR_EM8_Msk (0x1UL << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_EM9_Pos (9U)
+#define EXTI_EMR_EM9_Msk (0x1UL << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_EM10_Pos (10U)
+#define EXTI_EMR_EM10_Msk (0x1UL << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_EM11_Pos (11U)
+#define EXTI_EMR_EM11_Msk (0x1UL << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_EM12_Pos (12U)
+#define EXTI_EMR_EM12_Msk (0x1UL << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_EM13_Pos (13U)
+#define EXTI_EMR_EM13_Msk (0x1UL << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_EM14_Pos (14U)
+#define EXTI_EMR_EM14_Msk (0x1UL << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_EM15_Pos (15U)
+#define EXTI_EMR_EM15_Msk (0x1UL << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_EM16_Pos (16U)
+#define EXTI_EMR_EM16_Msk (0x1UL << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_EM17_Pos (17U)
+#define EXTI_EMR_EM17_Msk (0x1UL << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_EM18_Pos (18U)
+#define EXTI_EMR_EM18_Msk (0x1UL << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_EM19_Pos (19U)
+#define EXTI_EMR_EM19_Msk (0x1UL << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_EM20_Pos (20U)
+#define EXTI_EMR_EM20_Msk (0x1UL << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_EM21_Pos (21U)
+#define EXTI_EMR_EM21_Msk (0x1UL << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_EM22_Pos (22U)
+#define EXTI_EMR_EM22_Msk (0x1UL << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */
+#define EXTI_EMR_EM23_Pos (23U)
+#define EXTI_EMR_EM23_Msk (0x1UL << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
+#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
+#define EXTI_EMR_EM25_Pos (25U)
+#define EXTI_EMR_EM25_Msk (0x1UL << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */
+#define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */
+#define EXTI_EMR_EM26_Pos (26U)
+#define EXTI_EMR_EM26_Msk (0x1UL << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
+#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
+#define EXTI_EMR_EM28_Pos (28U)
+#define EXTI_EMR_EM28_Msk (0x1UL << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
+#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
+#define EXTI_EMR_EM29_Pos (29U)
+#define EXTI_EMR_EM29_Msk (0x1UL << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
+#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_RT0_Pos (0U)
+#define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_RT1_Pos (1U)
+#define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_RT2_Pos (2U)
+#define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_RT3_Pos (3U)
+#define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_RT4_Pos (4U)
+#define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_RT5_Pos (5U)
+#define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_RT6_Pos (6U)
+#define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_RT7_Pos (7U)
+#define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_RT8_Pos (8U)
+#define EXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_RT9_Pos (9U)
+#define EXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_RT10_Pos (10U)
+#define EXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_RT11_Pos (11U)
+#define EXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_RT12_Pos (12U)
+#define EXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_RT13_Pos (13U)
+#define EXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_RT14_Pos (14U)
+#define EXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_RT15_Pos (15U)
+#define EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_RT16_Pos (16U)
+#define EXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_RT17_Pos (17U)
+#define EXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_RT19_Pos (19U)
+#define EXTI_RTSR_RT19_Msk (0x1UL << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_RT20_Pos (20U)
+#define EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_RT21_Pos (21U)
+#define EXTI_RTSR_RT21_Msk (0x1UL << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_RT22_Pos (22U)
+#define EXTI_RTSR_RT22_Msk (0x1UL << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
+#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
+#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
+#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
+#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
+#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
+#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
+#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
+#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
+#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
+#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
+#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
+#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
+#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
+#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
+#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
+#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
+#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
+#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
+#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
+#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
+#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_FT0_Pos (0U)
+#define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_FT1_Pos (1U)
+#define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_FT2_Pos (2U)
+#define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_FT3_Pos (3U)
+#define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_FT4_Pos (4U)
+#define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_FT5_Pos (5U)
+#define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_FT6_Pos (6U)
+#define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_FT7_Pos (7U)
+#define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_FT8_Pos (8U)
+#define EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_FT9_Pos (9U)
+#define EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_FT10_Pos (10U)
+#define EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_FT11_Pos (11U)
+#define EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_FT12_Pos (12U)
+#define EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_FT13_Pos (13U)
+#define EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_FT14_Pos (14U)
+#define EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_FT15_Pos (15U)
+#define EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_FT16_Pos (16U)
+#define EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_FT17_Pos (17U)
+#define EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_FT19_Pos (19U)
+#define EXTI_FTSR_FT19_Msk (0x1UL << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_FT20_Pos (20U)
+#define EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_FT21_Pos (21U)
+#define EXTI_FTSR_FT21_Msk (0x1UL << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_FT22_Pos (22U)
+#define EXTI_FTSR_FT22_Msk (0x1UL << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
+#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
+#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
+#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
+#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
+#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
+#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
+#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
+#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
+#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
+#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
+#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
+#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
+#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
+#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
+#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
+#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
+#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
+#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
+#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
+#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
+#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWI0_Pos (0U)
+#define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWI1_Pos (1U)
+#define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWI2_Pos (2U)
+#define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWI3_Pos (3U)
+#define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWI4_Pos (4U)
+#define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWI5_Pos (5U)
+#define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWI6_Pos (6U)
+#define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWI7_Pos (7U)
+#define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWI8_Pos (8U)
+#define EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWI9_Pos (9U)
+#define EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWI10_Pos (10U)
+#define EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWI11_Pos (11U)
+#define EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWI12_Pos (12U)
+#define EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWI13_Pos (13U)
+#define EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWI14_Pos (14U)
+#define EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWI15_Pos (15U)
+#define EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWI16_Pos (16U)
+#define EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWI17_Pos (17U)
+#define EXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWI19_Pos (19U)
+#define EXTI_SWIER_SWI19_Msk (0x1UL << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWI20_Pos (20U)
+#define EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWI21_Pos (21U)
+#define EXTI_SWIER_SWI21_Msk (0x1UL << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWI22_Pos (22U)
+#define EXTI_SWIER_SWI22_Msk (0x1UL << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
+
+/* Legacy defines */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PIF0_Pos (0U)
+#define EXTI_PR_PIF0_Msk (0x1UL << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
+#define EXTI_PR_PIF1_Pos (1U)
+#define EXTI_PR_PIF1_Msk (0x1UL << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
+#define EXTI_PR_PIF2_Pos (2U)
+#define EXTI_PR_PIF2_Msk (0x1UL << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
+#define EXTI_PR_PIF3_Pos (3U)
+#define EXTI_PR_PIF3_Msk (0x1UL << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
+#define EXTI_PR_PIF4_Pos (4U)
+#define EXTI_PR_PIF4_Msk (0x1UL << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
+#define EXTI_PR_PIF5_Pos (5U)
+#define EXTI_PR_PIF5_Msk (0x1UL << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
+#define EXTI_PR_PIF6_Pos (6U)
+#define EXTI_PR_PIF6_Msk (0x1UL << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
+#define EXTI_PR_PIF7_Pos (7U)
+#define EXTI_PR_PIF7_Msk (0x1UL << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
+#define EXTI_PR_PIF8_Pos (8U)
+#define EXTI_PR_PIF8_Msk (0x1UL << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
+#define EXTI_PR_PIF9_Pos (9U)
+#define EXTI_PR_PIF9_Msk (0x1UL << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
+#define EXTI_PR_PIF10_Pos (10U)
+#define EXTI_PR_PIF10_Msk (0x1UL << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
+#define EXTI_PR_PIF11_Pos (11U)
+#define EXTI_PR_PIF11_Msk (0x1UL << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
+#define EXTI_PR_PIF12_Pos (12U)
+#define EXTI_PR_PIF12_Msk (0x1UL << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
+#define EXTI_PR_PIF13_Pos (13U)
+#define EXTI_PR_PIF13_Msk (0x1UL << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
+#define EXTI_PR_PIF14_Pos (14U)
+#define EXTI_PR_PIF14_Msk (0x1UL << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
+#define EXTI_PR_PIF15_Pos (15U)
+#define EXTI_PR_PIF15_Msk (0x1UL << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
+#define EXTI_PR_PIF16_Pos (16U)
+#define EXTI_PR_PIF16_Msk (0x1UL << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
+#define EXTI_PR_PIF17_Pos (17U)
+#define EXTI_PR_PIF17_Msk (0x1UL << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
+#define EXTI_PR_PIF19_Pos (19U)
+#define EXTI_PR_PIF19_Msk (0x1UL << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
+#define EXTI_PR_PIF20_Pos (20U)
+#define EXTI_PR_PIF20_Msk (0x1UL << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
+#define EXTI_PR_PIF21_Pos (21U)
+#define EXTI_PR_PIF21_Msk (0x1UL << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
+#define EXTI_PR_PIF22_Pos (22U)
+#define EXTI_PR_PIF22_Msk (0x1UL << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
+
+/* Legacy defines */
+#define EXTI_PR_PR0 EXTI_PR_PIF0
+#define EXTI_PR_PR1 EXTI_PR_PIF1
+#define EXTI_PR_PR2 EXTI_PR_PIF2
+#define EXTI_PR_PR3 EXTI_PR_PIF3
+#define EXTI_PR_PR4 EXTI_PR_PIF4
+#define EXTI_PR_PR5 EXTI_PR_PIF5
+#define EXTI_PR_PR6 EXTI_PR_PIF6
+#define EXTI_PR_PR7 EXTI_PR_PIF7
+#define EXTI_PR_PR8 EXTI_PR_PIF8
+#define EXTI_PR_PR9 EXTI_PR_PIF9
+#define EXTI_PR_PR10 EXTI_PR_PIF10
+#define EXTI_PR_PR11 EXTI_PR_PIF11
+#define EXTI_PR_PR12 EXTI_PR_PIF12
+#define EXTI_PR_PR13 EXTI_PR_PIF13
+#define EXTI_PR_PR14 EXTI_PR_PIF14
+#define EXTI_PR_PR15 EXTI_PR_PIF15
+#define EXTI_PR_PR16 EXTI_PR_PIF16
+#define EXTI_PR_PR17 EXTI_PR_PIF17
+#define EXTI_PR_PR19 EXTI_PR_PIF19
+#define EXTI_PR_PR20 EXTI_PR_PIF20
+#define EXTI_PR_PR21 EXTI_PR_PIF21
+#define EXTI_PR_PR22 EXTI_PR_PIF22
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
+#define FLASH_ACR_PRFTEN_Pos (1U)
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_SLEEP_PD_Pos (3U)
+#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD_Pos (4U)
+#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
+#define FLASH_ACR_DISAB_BUF_Pos (5U)
+#define FLASH_ACR_DISAB_BUF_Msk (0x1UL << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
+#define FLASH_ACR_PRE_READ_Pos (6U)
+#define FLASH_ACR_PRE_READ_Msk (0x1UL << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
+#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
+
+/******************* Bit definition for FLASH_PECR register ******************/
+#define FLASH_PECR_PELOCK_Pos (0U)
+#define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
+#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK_Pos (1U)
+#define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
+#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK_Pos (2U)
+#define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
+#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG_Pos (3U)
+#define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
+#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
+#define FLASH_PECR_DATA_Pos (4U)
+#define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
+#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
+#define FLASH_PECR_FIX_Pos (8U)
+#define FLASH_PECR_FIX_Msk (0x1UL << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
+#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE_Pos (9U)
+#define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
+#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
+#define FLASH_PECR_FPRG_Pos (10U)
+#define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
+#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_EOPIE_Pos (16U)
+#define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
+#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
+#define FLASH_PECR_ERRIE_Pos (17U)
+#define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
+#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
+#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
+#define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
+#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
+#define FLASH_PECR_HALF_ARRAY_Pos (19U)
+#define FLASH_PECR_HALF_ARRAY_Msk (0x1UL << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
+#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
+
+/****************** Bit definition for FLASH_PDKEYR register ******************/
+#define FLASH_PDKEYR_PDKEYR_Pos (0U)
+#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PEKEYR register ******************/
+#define FLASH_PEKEYR_PEKEYR_Pos (0U)
+#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PRGKEYR register ******************/
+#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
+#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
+
+/****************** Bit definition for FLASH_OPTKEYR register ******************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_EOP_Pos (1U)
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
+#define FLASH_SR_HVOFF_Pos (2U)
+#define FLASH_SR_HVOFF_Msk (0x1UL << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
+#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
+#define FLASH_SR_READY_Pos (3U)
+#define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */
+#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR_Pos (8U)
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
+#define FLASH_SR_PGAERR_Pos (9U)
+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR_Pos (10U)
+#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
+#define FLASH_SR_OPTVERR_Pos (11U)
+#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
+#define FLASH_SR_RDERR_Pos (13U)
+#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
+#define FLASH_SR_NOTZEROERR_Pos (16U)
+#define FLASH_SR_NOTZEROERR_Msk (0x1UL << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
+#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
+#define FLASH_SR_FWWERR_Pos (17U)
+#define FLASH_SR_FWWERR_Msk (0x1UL << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
+#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
+
+/* Legacy defines */
+#define FLASH_SR_FWWER FLASH_SR_FWWERR
+#define FLASH_SR_ENHV FLASH_SR_HVOFF
+#define FLASH_SR_ENDHV FLASH_SR_HVOFF
+
+/****************** Bit definition for FLASH_OPTR register *******************/
+#define FLASH_OPTR_RDPROT_Pos (0U)
+#define FLASH_OPTR_RDPROT_Msk (0xFFUL << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
+#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
+#define FLASH_OPTR_WPRMOD_Pos (8U)
+#define FLASH_OPTR_WPRMOD_Msk (0x1UL << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
+#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
+#define FLASH_OPTR_BOR_LEV_Pos (16U)
+#define FLASH_OPTR_BOR_LEV_Msk (0xFUL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
+#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OPTR_IWDG_SW_Pos (20U)
+#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
+#define FLASH_OPTR_nRST_STOP_Pos (21U)
+#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OPTR_nRST_STDBY_Pos (22U)
+#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OPTR_USER_Pos (20U)
+#define FLASH_OPTR_USER_Msk (0x7UL << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
+#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OPTR_BOOT1_Pos (31U)
+#define FLASH_OPTR_BOOT1_Msk (0x1UL << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
+#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 (0x00000001U)
+#define GPIO_OTYPER_OT_1 (0x00000002U)
+#define GPIO_OTYPER_OT_2 (0x00000004U)
+#define GPIO_OTYPER_OT_3 (0x00000008U)
+#define GPIO_OTYPER_OT_4 (0x00000010U)
+#define GPIO_OTYPER_OT_5 (0x00000020U)
+#define GPIO_OTYPER_OT_6 (0x00000040U)
+#define GPIO_OTYPER_OT_7 (0x00000080U)
+#define GPIO_OTYPER_OT_8 (0x00000100U)
+#define GPIO_OTYPER_OT_9 (0x00000200U)
+#define GPIO_OTYPER_OT_10 (0x00000400U)
+#define GPIO_OTYPER_OT_11 (0x00000800U)
+#define GPIO_OTYPER_OT_12 (0x00001000U)
+#define GPIO_OTYPER_OT_13 (0x00002000U)
+#define GPIO_OTYPER_OT_14 (0x00004000U)
+#define GPIO_OTYPER_OT_15 (0x00008000U)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDER_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
+#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDER_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
+#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDER_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
+#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDER_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
+#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDER_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
+#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDER_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
+#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDER_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
+#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDER_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
+#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDER_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
+#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDER_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
+#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDER_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
+#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDER_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
+#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDER_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
+#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDER_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
+#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDER_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
+#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDER_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
+#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 (0x00000001U)
+#define GPIO_BSRR_BS_1 (0x00000002U)
+#define GPIO_BSRR_BS_2 (0x00000004U)
+#define GPIO_BSRR_BS_3 (0x00000008U)
+#define GPIO_BSRR_BS_4 (0x00000010U)
+#define GPIO_BSRR_BS_5 (0x00000020U)
+#define GPIO_BSRR_BS_6 (0x00000040U)
+#define GPIO_BSRR_BS_7 (0x00000080U)
+#define GPIO_BSRR_BS_8 (0x00000100U)
+#define GPIO_BSRR_BS_9 (0x00000200U)
+#define GPIO_BSRR_BS_10 (0x00000400U)
+#define GPIO_BSRR_BS_11 (0x00000800U)
+#define GPIO_BSRR_BS_12 (0x00001000U)
+#define GPIO_BSRR_BS_13 (0x00002000U)
+#define GPIO_BSRR_BS_14 (0x00004000U)
+#define GPIO_BSRR_BS_15 (0x00008000U)
+#define GPIO_BSRR_BR_0 (0x00010000U)
+#define GPIO_BSRR_BR_1 (0x00020000U)
+#define GPIO_BSRR_BR_2 (0x00040000U)
+#define GPIO_BSRR_BR_3 (0x00080000U)
+#define GPIO_BSRR_BR_4 (0x00100000U)
+#define GPIO_BSRR_BR_5 (0x00200000U)
+#define GPIO_BSRR_BR_6 (0x00400000U)
+#define GPIO_BSRR_BR_7 (0x00800000U)
+#define GPIO_BSRR_BR_8 (0x01000000U)
+#define GPIO_BSRR_BR_9 (0x02000000U)
+#define GPIO_BSRR_BR_10 (0x04000000U)
+#define GPIO_BSRR_BR_11 (0x08000000U)
+#define GPIO_BSRR_BR_12 (0x10000000U)
+#define GPIO_BSRR_BR_13 (0x20000000U)
+#define GPIO_BSRR_BR_14 (0x40000000U)
+#define GPIO_BSRR_BR_15 (0x80000000U)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 (0x00000001U)
+#define GPIO_BRR_BR_1 (0x00000002U)
+#define GPIO_BRR_BR_2 (0x00000004U)
+#define GPIO_BRR_BR_3 (0x00000008U)
+#define GPIO_BRR_BR_4 (0x00000010U)
+#define GPIO_BRR_BR_5 (0x00000020U)
+#define GPIO_BRR_BR_6 (0x00000040U)
+#define GPIO_BRR_BR_7 (0x00000080U)
+#define GPIO_BRR_BR_8 (0x00000100U)
+#define GPIO_BRR_BR_9 (0x00000200U)
+#define GPIO_BRR_BR_10 (0x00000400U)
+#define GPIO_BRR_BR_11 (0x00000800U)
+#define GPIO_BRR_BR_12 (0x00001000U)
+#define GPIO_BRR_BR_13 (0x00002000U)
+#define GPIO_BRR_BR_14 (0x00004000U)
+#define GPIO_BRR_BR_15 (0x00008000U)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos (1U)
+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos (2U)
+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos (3U)
+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos (4U)
+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos (5U)
+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos (6U)
+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos (7U)
+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos (8U)
+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos (12U)
+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos (14U)
+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos (15U)
+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos (16U)
+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos (17U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos (18U)
+#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos (19U)
+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos (20U)
+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos (21U)
+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos (22U)
+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos (23U)
+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD_Pos (0U)
+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos (10U)
+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos (11U)
+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos (12U)
+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos (13U)
+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
+#define I2C_CR2_STOP_Pos (14U)
+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos (15U)
+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos (16U)
+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos (24U)
+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos (25U)
+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos (26U)
+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1_Pos (0U)
+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos (10U)
+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos (15U)
+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2_Pos (1U)
+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos (8U)
+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos (8U)
+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos (9U)
+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos (8U)
+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos (10U)
+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos (8U)
+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos (9U)
+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos (8U)
+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos (15U)
+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos (0U)
+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos (8U)
+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos (16U)
+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos (20U)
+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos (28U)
+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE_Pos (0U)
+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos (1U)
+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos (2U)
+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos (3U)
+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos (4U)
+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos (5U)
+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos (6U)
+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos (7U)
+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos (8U)
+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
+#define I2C_ISR_ARLO_Pos (9U)
+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos (10U)
+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos (11U)
+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos (12U)
+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos (13U)
+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos (15U)
+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
+#define I2C_ISR_DIR_Pos (16U)
+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos (17U)
+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF_Pos (3U)
+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos (4U)
+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos (5U)
+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos (8U)
+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos (9U)
+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos (10U)
+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos (11U)
+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos (12U)
+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos (13U)
+#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define I2C_PECR_PEC_Pos (0U)
+#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA_Pos (0U)
+#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA_Pos (0U)
+#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos (2U)
+#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN_Pos (0U)
+#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM_Pos (0U)
+#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos (1U)
+#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos (2U)
+#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos (3U)
+#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos (4U)
+#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos (5U)
+#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos (6U)
+#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF_Pos (0U)
+#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos (1U)
+#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos (3U)
+#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos (4U)
+#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos (5U)
+#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos (6U)
+#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos (0U)
+#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos (1U)
+#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos (3U)
+#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos (4U)
+#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos (5U)
+#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos (6U)
+#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos (0U)
+#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos (1U)
+#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos (3U)
+#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos (6U)
+#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos (9U)
+#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos (17U)
+#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos (19U)
+#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos (20U)
+#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos (21U)
+#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos (22U)
+#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos (24U)
+#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE_Pos (0U)
+#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos (1U)
+#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos (2U)
+#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP_Pos (0U)
+#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR_Pos (0U)
+#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT_Pos (0U)
+#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
+
+/******************************************************************************/
+/* */
+/* MIFARE Firewall */
+/* */
+/******************************************************************************/
+
+/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
+#define FW_CSSA_ADD_Pos (8U)
+#define FW_CSSA_ADD_Msk (0xFFFFUL << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
+#define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
+#define FW_CSL_LENG_Pos (8U)
+#define FW_CSL_LENG_Msk (0x3FFFUL << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
+#define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
+#define FW_NVDSSA_ADD_Pos (8U)
+#define FW_NVDSSA_ADD_Msk (0xFFFFUL << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
+#define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
+#define FW_NVDSL_LENG_Pos (8U)
+#define FW_NVDSL_LENG_Msk (0x3FFFUL << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
+#define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
+#define FW_VDSSA_ADD_Pos (6U)
+#define FW_VDSSA_ADD_Msk (0x3FFUL << FW_VDSSA_ADD_Pos) /*!< 0x0000FFC0 */
+#define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
+#define FW_VDSL_LENG_Pos (6U)
+#define FW_VDSL_LENG_Msk (0x3FFUL << FW_VDSL_LENG_Pos) /*!< 0x0000FFC0 */
+#define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
+
+/**************************Bit definition for CR register *********************/
+#define FW_CR_FPA_Pos (0U)
+#define FW_CR_FPA_Msk (0x1UL << FW_CR_FPA_Pos) /*!< 0x00000001 */
+#define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
+#define FW_CR_VDS_Pos (1U)
+#define FW_CR_VDS_Msk (0x1UL << FW_CR_VDS_Pos) /*!< 0x00000002 */
+#define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
+#define FW_CR_VDE_Pos (2U)
+#define FW_CR_VDE_Msk (0x1UL << FW_CR_VDE_Pos) /*!< 0x00000004 */
+#define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
+
+/******************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/******************************************************************************/
+
+#define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPSDSR_Pos (0U)
+#define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP_Pos (9U)
+#define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /*!< 0x00000200 */
+#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
+#define PWR_CR_FWU_Pos (10U)
+#define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /*!< 0x00000400 */
+#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
+
+#define PWR_CR_VOS_Pos (11U)
+#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x00001800 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /*!< 0x00000800 */
+#define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /*!< 0x00001000 */
+#define PWR_CR_DSEEKOFF_Pos (13U)
+#define PWR_CR_DSEEKOFF_Msk (0x1UL << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */
+#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */
+#define PWR_CR_LPRUN_Pos (14U)
+#define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
+#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF_Pos (3U)
+#define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
+#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF_Pos (4U)
+#define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
+#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF_Pos (5U)
+#define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
+#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1_Pos (8U)
+#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2_Pos (9U)
+#define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
+#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos (1U)
+#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos (2U)
+#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIVEN_Pos (3U)
+#define RCC_CR_HSIDIVEN_Msk (0x1UL << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */
+#define RCC_CR_HSIDIVF_Pos (4U)
+#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */
+#define RCC_CR_MSION_Pos (8U)
+#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000100 */
+#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY_Pos (9U)
+#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
+#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON_Pos (19U)
+#define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */
+#define RCC_CR_RTCPRE_Pos (20U)
+#define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
+#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */
+#define RCC_CR_RTCPRE_0 (0x1UL << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */
+#define RCC_CR_RTCPRE_1 (0x2UL << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+/* Reference defines */
+#define RCC_CR_CSSON RCC_CR_CSSHSEON
+
+/******************** Bit definition for RCC_ICSCR register *****************/
+#define RCC_ICSCR_HSICAL_Pos (0U)
+#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
+#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM_Pos (8U)
+#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
+#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE_Pos (13U)
+#define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
+#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
+#define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
+#define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
+#define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
+#define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
+#define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
+#define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
+#define RCC_ICSCR_MSICAL_Pos (16U)
+#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
+#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM_Pos (24U)
+#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
+#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos (15U)
+#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */
+
+/*!< PLL entry clock source*/
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
+
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL_Pos (18U)
+#define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV_Pos (22U)
+#define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
+
+#define RCC_CFGR_PLLDIV2_Pos (22U)
+#define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3_Pos (23U)
+#define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4_Pos (22U)
+#define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCOSEL_Pos (24U)
+#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
+#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
+
+#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
+#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCOSEL_HSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_MSI_Pos (24U)
+#define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
+#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_HSE_Pos (26U)
+#define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCOSEL_PLL_Pos (24U)
+#define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
+#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
+#define RCC_CFGR_MCOSEL_LSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
+#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
+#define RCC_CFGR_MCOSEL_LSE_Pos (24U)
+#define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
+
+#define RCC_CFGR_MCOPRE_Pos (28U)
+#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
+
+#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
+
+/* Legacy defines */
+#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
+#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
+#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
+#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
+#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
+#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
+#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
+#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
+#ifdef RCC_CFGR_MCOSEL_HSI48
+#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48
+#endif
+
+#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
+#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
+
+/*!<****************** Bit definition for RCC_CIER register ********************/
+#define RCC_CIER_LSIRDYIE_Pos (0U)
+#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIER_LSERDYIE_Pos (1U)
+#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIER_HSIRDYIE_Pos (2U)
+#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIER_HSERDYIE_Pos (3U)
+#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIER_PLLRDYIE_Pos (4U)
+#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIER_MSIRDYIE_Pos (5U)
+#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
+#define RCC_CIER_CSSLSE_Pos (7U)
+#define RCC_CIER_CSSLSE_Msk (0x1UL << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */
+
+/* Reference defines */
+#define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
+
+/*!<****************** Bit definition for RCC_CIFR register ********************/
+#define RCC_CIFR_LSIRDYF_Pos (0U)
+#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIFR_LSERDYF_Pos (1U)
+#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIFR_HSIRDYF_Pos (2U)
+#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIFR_HSERDYF_Pos (3U)
+#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIFR_PLLRDYF_Pos (4U)
+#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIFR_MSIRDYF_Pos (5U)
+#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
+#define RCC_CIFR_CSSLSEF_Pos (7U)
+#define RCC_CIFR_CSSLSEF_Msk (0x1UL << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */
+#define RCC_CIFR_CSSHSEF_Pos (8U)
+#define RCC_CIFR_CSSHSEF_Msk (0x1UL << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */
+#define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */
+
+/* Reference defines */
+#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
+#define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
+
+/*!<****************** Bit definition for RCC_CICR register ********************/
+#define RCC_CICR_LSIRDYC_Pos (0U)
+#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CICR_LSERDYC_Pos (1U)
+#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CICR_HSIRDYC_Pos (2U)
+#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CICR_HSERDYC_Pos (3U)
+#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CICR_PLLRDYC_Pos (4U)
+#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CICR_MSIRDYC_Pos (5U)
+#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
+#define RCC_CICR_CSSLSEC_Pos (7U)
+#define RCC_CICR_CSSLSEC_Msk (0x1UL << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */
+#define RCC_CICR_CSSHSEC_Pos (8U)
+#define RCC_CICR_CSSHSEC_Msk (0x1UL << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */
+#define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */
+
+/* Reference defines */
+#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
+#define RCC_CICR_CSSC RCC_CICR_CSSHSEC
+/***************** Bit definition for RCC_IOPRSTR register ******************/
+#define RCC_IOPRSTR_IOPARST_Pos (0U)
+#define RCC_IOPRSTR_IOPARST_Msk (0x1UL << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */
+#define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */
+#define RCC_IOPRSTR_IOPBRST_Pos (1U)
+#define RCC_IOPRSTR_IOPBRST_Msk (0x1UL << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */
+#define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */
+#define RCC_IOPRSTR_IOPCRST_Pos (2U)
+#define RCC_IOPRSTR_IOPCRST_Msk (0x1UL << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */
+#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */
+#define RCC_IOPRSTR_IOPDRST_Pos (3U)
+#define RCC_IOPRSTR_IOPDRST_Msk (0x1UL << RCC_IOPRSTR_IOPDRST_Pos) /*!< 0x00000008 */
+#define RCC_IOPRSTR_IOPDRST RCC_IOPRSTR_IOPDRST_Msk /*!< GPIO port D reset */
+#define RCC_IOPRSTR_IOPHRST_Pos (7U)
+#define RCC_IOPRSTR_IOPHRST_Msk (0x1UL << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */
+#define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */
+
+/* Reference defines */
+#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
+#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
+#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
+#define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_IOPDRST /*!< GPIO port D reset */
+#define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
+
+
+/****************** Bit definition for RCC_AHBRST register ******************/
+#define RCC_AHBRSTR_DMARST_Pos (0U)
+#define RCC_AHBRSTR_DMARST_Msk (0x1UL << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */
+#define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */
+#define RCC_AHBRSTR_MIFRST_Pos (8U)
+#define RCC_AHBRSTR_MIFRST_Msk (0x1UL << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */
+#define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset */
+#define RCC_AHBRSTR_CRCRST_Pos (12U)
+#define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */
+
+/* Reference defines */
+#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
+#define RCC_APB2RSTR_TIM21RST_Pos (2U)
+#define RCC_APB2RSTR_TIM21RST_Msk (0x1UL << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 reset */
+#define RCC_APB2RSTR_TIM22RST_Pos (5U)
+#define RCC_APB2RSTR_TIM22RST_Msk (0x1UL << RCC_APB2RSTR_TIM22RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk /*!< TIM22 reset */
+#define RCC_APB2RSTR_ADCRST_Pos (9U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
+#define RCC_APB2RSTR_DBGRST_Pos (22U)
+#define RCC_APB2RSTR_DBGRST_Msk (0x1UL << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU reset */
+
+/* Reference defines */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 reset */
+#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU reset */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_LPUART1RST_Pos (18U)
+#define RCC_APB1RSTR_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
+#define RCC_APB1RSTR_LPTIM1RST_Pos (31U)
+#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 reset */
+
+/***************** Bit definition for RCC_IOPENR register ******************/
+#define RCC_IOPENR_IOPAEN_Pos (0U)
+#define RCC_IOPENR_IOPAEN_Msk (0x1UL << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */
+#define RCC_IOPENR_IOPBEN_Pos (1U)
+#define RCC_IOPENR_IOPBEN_Msk (0x1UL << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */
+#define RCC_IOPENR_IOPCEN_Pos (2U)
+#define RCC_IOPENR_IOPCEN_Msk (0x1UL << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */
+#define RCC_IOPENR_IOPDEN_Pos (3U)
+#define RCC_IOPENR_IOPDEN_Msk (0x1UL << RCC_IOPENR_IOPDEN_Pos) /*!< 0x00000008 */
+#define RCC_IOPENR_IOPDEN RCC_IOPENR_IOPDEN_Msk /*!< GPIO port D clock enable */
+#define RCC_IOPENR_IOPHEN_Pos (7U)
+#define RCC_IOPENR_IOPHEN_Msk (0x1UL << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */
+
+/* Reference defines */
+#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
+#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
+#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
+#define RCC_IOPENR_GPIODEN RCC_IOPENR_IOPDEN /*!< GPIO port D clock enable */
+#define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
+
+/***************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMAEN_Pos (0U)
+#define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_MIFEN_Pos (8U)
+#define RCC_AHBENR_MIFEN_Msk (0x1UL << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */
+#define RCC_AHBENR_CRCEN_Pos (12U)
+#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+
+/* Reference defines */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register ******************/
+#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM21EN_Pos (2U)
+#define RCC_APB2ENR_TIM21EN_Msk (0x1UL << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */
+#define RCC_APB2ENR_TIM22EN_Pos (5U)
+#define RCC_APB2ENR_TIM22EN_Msk (0x1UL << RCC_APB2ENR_TIM22EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk /*!< TIM22 clock enable */
+#define RCC_APB2ENR_FWEN_Pos (7U)
+#define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADCEN_Pos (9U)
+#define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
+#define RCC_APB2ENR_DBGEN_Pos (22U)
+#define RCC_APB2ENR_DBGEN_Msk (0x1UL << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */
+
+/* Reference defines */
+
+#define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
+#define RCC_APB1ENR_LPUART1EN_Pos (18U)
+#define RCC_APB1ENR_LPUART1EN_Msk (0x1UL << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
+#define RCC_APB1ENR_LPTIM1EN_Pos (31U)
+#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */
+
+/****************** Bit definition for RCC_IOPSMENR register ****************/
+#define RCC_IOPSMENR_IOPASMEN_Pos (0U)
+#define RCC_IOPSMENR_IOPASMEN_Msk (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPBSMEN_Pos (1U)
+#define RCC_IOPSMENR_IOPBSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPCSMEN_Pos (2U)
+#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPDSMEN_Pos (3U)
+#define RCC_IOPSMENR_IOPDSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos) /*!< 0x00000008 */
+#define RCC_IOPSMENR_IOPDSMEN RCC_IOPSMENR_IOPDSMEN_Msk /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPHSMEN_Pos (7U)
+#define RCC_IOPSMENR_IOPHSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_IOPDSMEN /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_AHBSMENR register ******************/
+#define RCC_AHBSMENR_DMASMEN_Pos (0U)
+#define RCC_AHBSMENR_DMASMEN_Msk (0x1UL << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */
+#define RCC_AHBSMENR_MIFSMEN_Pos (8U)
+#define RCC_AHBSMENR_MIFSMEN_Msk (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */
+#define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
+#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRCSMEN_Pos (12U)
+#define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB2SMENR register ******************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM21SMEN_Pos (2U)
+#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM22SMEN_Pos (5U)
+#define RCC_APB2SMENR_TIM22SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk /*!< TIM22 clock enabled in sleep mode */
+#define RCC_APB2SMENR_ADCSMEN_Pos (9U)
+#define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
+#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
+#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk /*!< USART1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGSMEN_Pos (22U)
+#define RCC_APB2SMENR_DBGSMEN_Msk (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB1SMENR register ******************/
+#define RCC_APB1SMENR_TIM2SMEN_Pos (0U)
+#define RCC_APB1SMENR_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_TIM6SMEN_Pos (4U)
+#define RCC_APB1SMENR_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM6SMEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1SMENR_TIM6SMEN RCC_APB1SMENR_TIM6SMEN_Msk /*!< Timer 6 clock enabled in sleep mode */
+#define RCC_APB1SMENR_WWDGSMEN_Pos (11U)
+#define RCC_APB1SMENR_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */
+#define RCC_APB1SMENR_SPI2SMEN_Pos (14U)
+#define RCC_APB1SMENR_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR_SPI2SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1SMENR_SPI2SMEN RCC_APB1SMENR_SPI2SMEN_Msk /*!< SPI2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART2SMEN_Pos (17U)
+#define RCC_APB1SMENR_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPUART1SMEN_Pos (18U)
+#define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C1SMEN_Pos (21U)
+#define RCC_APB1SMENR_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C2SMEN_Pos (22U)
+#define RCC_APB1SMENR_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1SMENR_I2C2SMEN RCC_APB1SMENR_I2C2SMEN_Msk /*!< I2C2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_PWRSMEN_Pos (28U)
+#define RCC_APB1SMENR_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U)
+#define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */
+
+/******************* Bit definition for RCC_CCIPR register *******************/
+/*!< USART1 Clock source selection */
+#define RCC_CCIPR_USART1SEL_Pos (0U)
+#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
+#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk /*!< USART1SEL[1:0] bits */
+#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
+
+/*!< USART2 Clock source selection */
+#define RCC_CCIPR_USART2SEL_Pos (2U)
+#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */
+#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+/*!< LPUART1 Clock source selection */
+#define RCC_CCIPR_LPUART1SEL_Pos (10U)
+#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */
+#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */
+#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CCIPR_I2C1SEL_Pos (12U)
+#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */
+#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
+
+
+/*!< LPTIM1 Clock source selection */
+#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
+#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */
+#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+/******************* Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSEON_Pos (8U)
+#define RCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */
+#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_CSR_LSERDY_Pos (9U)
+#define RCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */
+#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP_Pos (10U)
+#define RCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */
+#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_CSR_LSEDRV_Pos (11U)
+#define RCC_CSR_LSEDRV_Msk (0x3UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */
+#define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_CSR_LSEDRV_0 (0x1UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */
+#define RCC_CSR_LSEDRV_1 (0x2UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */
+
+#define RCC_CSR_LSECSSON_Pos (13U)
+#define RCC_CSR_LSECSSON_Msk (0x1UL << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */
+#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */
+#define RCC_CSR_LSECSSD_Pos (14U)
+#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
+#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
+
+/*!< RTC congiguration */
+#define RCC_CSR_RTCSEL_Pos (16U)
+#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
+
+#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CSR_RTCSEL_LSE_Pos (16U)
+#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_LSI_Pos (17U)
+#define RCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */
+#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_HSE_Pos (16U)
+#define RCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */
+
+#define RCC_CSR_RTCEN_Pos (18U)
+#define RCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */
+#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_CSR_RTCRST_Pos (19U)
+#define RCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */
+#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */
+
+#define RCC_CSR_RMVF_Pos (23U)
+#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_FWRSTF_Pos (24U)
+#define RCC_CSR_FWRSTF_Msk (0x1UL << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk /*!< Mifare Firewall reset flag */
+#define RCC_CSR_OBLRSTF_Pos (25U)
+#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+/* Reference defines */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER1_SUPPORT
+#define RTC_TAMPER2_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk /*!< */
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk /*!< */
+#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk /*!< */
+#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */
+#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */
+#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk /*!< */
+#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk /*!< */
+#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk /*!< */
+#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk /*!< */
+#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */
+#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk /*!< */
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk /*!< */
+#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk /*!< */
+#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk /*!< */
+#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk /*!< */
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */
+#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk /*!< */
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< */
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */
+#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */
+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */
+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */
+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */
+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */
+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */
+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */
+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */
+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */
+#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */
+#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */
+#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */
+#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */
+#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */
+#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */
+#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */
+#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */
+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */
+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */
+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */
+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */
+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */
+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */
+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */
+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */
+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */
+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CALR register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */
+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define RTC_CAL_CALP RTC_CALR_CALP
+#define RTC_CAL_CALW8 RTC_CALR_CALW8
+#define RTC_CAL_CALW16 RTC_CALR_CALW16
+#define RTC_CAL_CALM RTC_CALR_CALM
+#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
+
+/******************** Bits definition for RTC_TAMPCR register ****************/
+#define RTC_TAMPCR_TAMP2MF_Pos (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2IE_Pos (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1MF_Pos (18U)
+#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
+#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1IE_Pos (16U)
+#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */
+#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */
+#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */
+#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos (7U)
+#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */
+#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP2E_Pos (3U)
+#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */
+#define RTC_TAMPCR_TAMPIE_Pos (2U)
+#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
+#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP1E_Pos (0U)
+#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_OR register ****************/
+#define RTC_OR_OUT_RMP_Pos (1U)
+#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */
+#define RTC_OR_ALARMOUTTYPE_Pos (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */
+
+/* Legacy defines */
+#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk /*!< */
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER (0x00000005U) /*!< */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+#define SPI_I2S_SUPPORT /*!< I2S support */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
+#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR1_BOOT_MODE_Pos (8U)
+#define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
+#define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */
+#define SYSCFG_CFGR1_BOOT_MODE_0 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOT_MODE_1 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_FWDISEN_Pos (0U)
+#define SYSCFG_CFGR2_FWDISEN_Msk (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos (8U)
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR2_I2C_PB6_FMP SYSCFG_CFGR2_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos (9U)
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR2_I2C_PB7_FMP SYSCFG_CFGR2_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos (10U)
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
+#define SYSCFG_CFGR2_I2C_PB8_FMP SYSCFG_CFGR2_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos (11U)
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
+#define SYSCFG_CFGR2_I2C_PB9_FMP SYSCFG_CFGR2_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR2_I2C1_FMP_Pos (12U)
+#define SYSCFG_CFGR2_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR2_I2C1_FMP SYSCFG_CFGR2_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR2_I2C2_FMP_Pos (13U)
+#define SYSCFG_CFGR2_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
+#define SYSCFG_CFGR2_I2C2_FMP SYSCFG_CFGR2_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
+
+
+/***************** Bit definition for SYSCFG_CFGR3 register ****************/
+#define SYSCFG_CFGR3_EN_VREFINT_Pos (0U)
+#define SYSCFG_CFGR3_EN_VREFINT_Msk (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_EN_VREFINT SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
+#define SYSCFG_CFGR3_VREF_OUT_Pos (4U)
+#define SYSCFG_CFGR3_VREF_OUT_Msk (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
+#define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */
+#define SYSCFG_CFGR3_VREF_OUT_0 (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
+#define SYSCFG_CFGR3_VREF_OUT_1 (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U)
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U)
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U)
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
+#define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U)
+#define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
+#define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
+#define SYSCFG_CFGR3_REF_LOCK_Pos (31U)
+#define SYSCFG_CFGR3_REF_LOCK_Msk (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
+#define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */
+
+/* Legacy defines */
+
+#define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
+#define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
+#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
+#define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+
+/******************************************************************************/
+/* */
+/* Timers (TIM)*/
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
+#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
+ || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#else
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#endif
+
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFUL << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFUL << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM2_OR_ETR_RMP_Pos (0U)
+#define TIM2_OR_ETR_RMP_Msk (0x7UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000007 */
+#define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
+#define TIM2_OR_ETR_RMP_0 (0x1UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM2_OR_ETR_RMP_1 (0x2UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM2_OR_ETR_RMP_2 (0x4UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000004 */
+#define TIM2_OR_TI4_RMP_Pos (3U)
+#define TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000018 */
+#define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
+#define TIM2_OR_TI4_RMP_0 (0x1UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */
+#define TIM2_OR_TI4_RMP_1 (0x2UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000010 */
+
+#define TIM21_OR_ETR_RMP_Pos (0U)
+#define TIM21_OR_ETR_RMP_Msk (0x3UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
+#define TIM21_OR_ETR_RMP_0 (0x1UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM21_OR_ETR_RMP_1 (0x2UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM21_OR_TI1_RMP_Pos (2U)
+#define TIM21_OR_TI1_RMP_Msk (0x7UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x0000001C */
+#define TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
+#define TIM21_OR_TI1_RMP_0 (0x1UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM21_OR_TI1_RMP_1 (0x2UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+#define TIM21_OR_TI1_RMP_2 (0x4UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000010 */
+#define TIM21_OR_TI2_RMP_Pos (5U)
+#define TIM21_OR_TI2_RMP_Msk (0x1UL << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */
+#define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */
+
+#define TIM22_OR_ETR_RMP_Pos (0U)
+#define TIM22_OR_ETR_RMP_Msk (0x3UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM22_OR_ETR_RMP TIM22_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
+#define TIM22_OR_ETR_RMP_0 (0x1UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM22_OR_ETR_RMP_1 (0x2UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM22_OR_TI1_RMP_Pos (2U)
+#define TIM22_OR_TI1_RMP_Msk (0x3UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x0000000C */
+#define TIM22_OR_TI1_RMP TIM22_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
+#define TIM22_OR_TI1_RMP_0 (0x1UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM22_OR_TI1_RMP_1 (0x2UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE_Pos (0U)
+#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+#define USART_CR1_UESM_Pos (1U)
+#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
+#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_M0_Pos (12U)
+#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
+#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos (13U)
+#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos (14U)
+#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos (16U)
+#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
+#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
+#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
+#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
+#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos (21U)
+#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
+#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
+#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
+#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
+#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos (26U)
+#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos (27U)
+#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos (28U)
+#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
+#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7_Pos (4U)
+#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos (15U)
+#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos (16U)
+#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos (17U)
+#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos (18U)
+#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos (19U)
+#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos (20U)
+#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos (21U)
+#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos (23U)
+#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos (24U)
+#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos (12U)
+#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos (13U)
+#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos (14U)
+#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos (15U)
+#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos (17U)
+#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos (20U)
+#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
+#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
+#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos (22U)
+#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
+#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
+#define USART_CR3_UCESM_Pos (23U)
+#define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
+#define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION_Pos (0U)
+#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos (4U)
+#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO_Pos (0U)
+#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos (24U)
+#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ_Pos (0U)
+#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
+#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos (1U)
+#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
+#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos (2U)
+#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
+#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos (3U)
+#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
+#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos (4U)
+#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
+#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE_Pos (0U)
+#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
+#define USART_ISR_FE_Pos (1U)
+#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
+#define USART_ISR_NE_Pos (2U)
+#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos (3U)
+#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos (4U)
+#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos (5U)
+#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos (6U)
+#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos (7U)
+#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
+#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos (8U)
+#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos (9U)
+#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos (10U)
+#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
+#define USART_ISR_RTOF_Pos (11U)
+#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos (12U)
+#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos (14U)
+#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos (15U)
+#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos (16U)
+#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
+#define USART_ISR_CMF_Pos (17U)
+#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos (18U)
+#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos (19U)
+#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos (20U)
+#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
+#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos (21U)
+#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos (22U)
+#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
+#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF_Pos (0U)
+#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos (1U)
+#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos (2U)
+#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */
+#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos (3U)
+#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos (4U)
+#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos (6U)
+#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF_Pos (8U)
+#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos (9U)
+#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos (11U)
+#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos (12U)
+#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos (17U)
+#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos (20U)
+#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
+#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
+
+/* Compatibility defines with other series */
+#define USART_ICR_NECF USART_ICR_NCF
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR_Pos (0U)
+#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR_Pos (0U)
+#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+/******************************* COMP Instances *******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+ ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOH))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
+
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2)
+
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SMBUS Instances *****************************/
+#define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/************* LPTIM instances supporting the encoder mode feature ************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM6))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM21) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM22) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/******************* TIM Instances : output(s) OCXEC register *****************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** USART Instances : Auto Baud Rate detection ****************/
+
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32L0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32L0 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+
+#define RNG_LPUART1_IRQn LPUART1_IRQn
+#define AES_LPUART1_IRQn LPUART1_IRQn
+#define AES_RNG_LPUART1_IRQn LPUART1_IRQn
+#define TIM6_DAC_IRQn TIM6_IRQn
+#define RCC_CRS_IRQn RCC_IRQn
+#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
+#define ADC1_IRQn ADC1_COMP_IRQn
+
+/* Aliases for __IRQHandler */
+#define RNG_LPUART1_IRQHandler LPUART1_IRQHandler
+#define AES_LPUART1_IRQHandler LPUART1_IRQHandler
+#define AES_RNG_LPUART1_IRQHandler LPUART1_IRQHandler
+#define TIM6_DAC_IRQHandler TIM6_IRQHandler
+#define RCC_CRS_IRQHandler RCC_IRQHandler
+#define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
+#define ADC1_IRQHandler ADC1_COMP_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L051xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/CMSIS/device/stm32l052xx.h b/CMSIS/device/stm32l052xx.h
new file mode 100644
index 0000000..3ebe463
--- /dev/null
+++ b/CMSIS/device/stm32l052xx.h
@@ -0,0 +1,7349 @@
+/**
+ ******************************************************************************
+ * @file stm32l052xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for stm32l052xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright(c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l052xx
+ * @{
+ */
+
+#ifndef __STM32L052xx_H
+#define __STM32L052xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 1U /*!< STM32L0xx provides an MPU */
+#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
+#define __NVIC_PRIO_BITS 2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief stm32l052xx Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+/*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
+
+/****** STM32L-0 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */
+ RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ TSC_IRQn = 8, /*!< TSC Interrupt */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
+ ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
+ LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 Interrupt */
+ TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
+ TIM21_IRQn = 20, /*!< TIM21 Interrupt */
+ TIM22_IRQn = 22, /*!< TIM22 Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */
+ I2C2_IRQn = 24, /*!< I2C2 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ SPI2_IRQn = 26, /*!< SPI2 Interrupt */
+ USART1_IRQn = 27, /*!< USART1 Interrupt */
+ USART2_IRQn = 28, /*!< USART2 Interrupt */
+ RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */
+ USB_IRQn = 31, /*!< USB global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0plus.h"
+#include "system_stm32l0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+ uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Comparator
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
+} COMP_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+
+/**
+* @brief CRC calculation unit
+*/
+
+typedef struct
+{
+__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+uint8_t RESERVED0; /*!< Reserved, 0x05 */
+uint16_t RESERVED1; /*!< Reserved, 0x06 */
+__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+uint32_t RESERVED2; /*!< Reserved, 0x0C */
+__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Clock Recovery System
+ */
+
+typedef struct
+{
+__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
+__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
+__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
+__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
+} CRS_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ uint32_t RESERVED0[6]; /*!< 0x14-0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ uint32_t RESERVED1; /*!< 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
+} DMA_Request_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
+ __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
+ __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
+ __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
+ __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
+ __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
+ __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
+ __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
+ __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
+ __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
+} OB_TypeDef;
+
+
+/**
+ * @brief General Purpose IO
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief LPTIMIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+} LPTIM_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+ * @brief Independent WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief MIFARE Firewall
+ */
+typedef struct
+{
+ __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
+ __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
+ __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
+ __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
+ __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
+ __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
+ __IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x18 */
+ __IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */
+ __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
+
+} FIREWALL_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
+ __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
+ __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
+ __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
+ __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
+ __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
+ __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
+ __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
+ __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
+ __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
+ __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
+} RCC_TypeDef;
+
+/**
+ * @brief Random numbers generator
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Touch Sensing Controller (TSC)
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
+ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
+ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
+ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
+ __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief Universal Serial Bus Full Speed Device
+ */
+typedef struct
+{
+ __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
+ __IO uint16_t RESERVED0; /*!< Reserved */
+ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
+ __IO uint16_t RESERVED1; /*!< Reserved */
+ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
+ __IO uint16_t RESERVED2; /*!< Reserved */
+ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
+ __IO uint16_t RESERVED3; /*!< Reserved */
+ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
+ __IO uint16_t RESERVED4; /*!< Reserved */
+ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
+ __IO uint16_t RESERVED5; /*!< Reserved */
+ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
+ __IO uint16_t RESERVED6; /*!< Reserved */
+ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
+ __IO uint16_t RESERVED7[17]; /*!< Reserved */
+ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
+ __IO uint16_t RESERVED8; /*!< Reserved */
+ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
+ __IO uint16_t RESERVED9; /*!< Reserved */
+ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
+ __IO uint16_t RESERVEDA; /*!< Reserved */
+ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
+ __IO uint16_t RESERVEDB; /*!< Reserved */
+ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
+ __IO uint16_t RESERVEDC; /*!< Reserved */
+ __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
+ __IO uint16_t RESERVEDD; /*!< Reserved */
+ __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
+ __IO uint16_t RESERVEDE; /*!< Reserved */
+} USB_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */
+
+#define DATA_EEPROM_BASE (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
+#define DATA_EEPROM_END (0x080807FFUL) /*!< DATA EEPROM end address in the alias region */
+#define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */
+#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8KBytes) */
+
+#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000UL)
+
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL)
+#define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
+#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
+#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800UL)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
+#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL)
+#define CRS_BASE (APBPERIPH_BASE + 0x00006C00UL)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
+#define DAC_BASE (APBPERIPH_BASE + 0x00007400UL)
+#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL)
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
+#define COMP1_BASE (APBPERIPH_BASE + 0x00010018UL)
+#define COMP2_BASE (APBPERIPH_BASE + 0x0001001CUL)
+#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL)
+#define TIM21_BASE (APBPERIPH_BASE + 0x00010800UL)
+#define TIM22_BASE (APBPERIPH_BASE + 0x00011400UL)
+#define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00UL)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708UL)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
+#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
+#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL)
+
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
+#define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */
+#define FLASHSIZE_BASE (0x1FF8007CUL) /*!< FLASH Size register base address */
+#define UID_BASE (0x1FF80050UL) /*!< Unique device ID register base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
+#define TSC_BASE (AHBPERIPH_BASE + 0x00004000UL)
+#define RNG_BASE (AHBPERIPH_BASE + 0x00005000UL)
+
+#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL)
+#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL)
+#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL)
+#define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00UL)
+#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00UL)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define CRS ((CRS_TypeDef *) CRS_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
+#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
+#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
+/* Legacy defines */
+#define ADC ADC1_COMMON
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define TSC ((TSC_TypeDef *) TSC_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+
+#define USB ((USB_TypeDef *) USB_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_EOCAL_Pos (11U)
+#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
+#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
+#define ADC_ISR_AWD_Pos (7U)
+#define ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
+#define ADC_ISR_EOSEQ_Pos (3U)
+#define ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_EOCALIE_Pos (11U)
+#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
+#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
+#define ADC_IER_AWDIE_Pos (7U)
+#define ADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE_Pos (3U)
+#define ADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH_Pos (26U)
+#define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
+#define ADC_CFGR1_AWDEN_Pos (23U)
+#define ADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL_Pos (22U)
+#define ADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN_Pos (16U)
+#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF_Pos (15U)
+#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
+#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT_Pos (14U)
+#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
+#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT_Pos (13U)
+#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD_Pos (12U)
+#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN_Pos (10U)
+#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
+#define ADC_CFGR1_EXTSEL_Pos (6U)
+#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
+#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
+#define ADC_CFGR1_ALIGN_Pos (5U)
+#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
+#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
+#define ADC_CFGR1_RES_Pos (3U)
+#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
+#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
+#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
+#define ADC_CFGR1_SCANDIR_Pos (2U)
+#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG_Pos (1U)
+#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
+#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN_Pos (0U)
+#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
+#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_TOVS_Pos (9U)
+#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
+#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+#define ADC_CFGR2_OVSR_Pos (2U)
+#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
+#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+#define ADC_CFGR2_OVSE_Pos (0U)
+#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
+#define ADC_CFGR2_CKMODE_Pos (30U)
+#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
+#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
+#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
+#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
+
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP_Pos (0U)
+#define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
+#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
+#define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
+#define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define ADC_SMPR_SMPR ADC_SMPR_SMP
+#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
+#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
+#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT_Pos (16U)
+#define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
+#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
+#define ADC_TR_LT_Pos (0U)
+#define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL_Pos (0U)
+#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
+#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
+#define ADC_CHSELR_CHSEL18_Pos (18U)
+#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17_Pos (17U)
+#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
+#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL15_Pos (15U)
+#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
+#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14_Pos (14U)
+#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
+#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13_Pos (13U)
+#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
+#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12_Pos (12U)
+#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
+#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11_Pos (11U)
+#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
+#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10_Pos (10U)
+#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
+#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9_Pos (9U)
+#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
+#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8_Pos (8U)
+#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
+#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7_Pos (7U)
+#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
+#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6_Pos (6U)
+#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
+#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5_Pos (5U)
+#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
+#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4_Pos (4U)
+#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
+#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3_Pos (3U)
+#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
+#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2_Pos (2U)
+#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
+#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1_Pos (1U)
+#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
+#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0_Pos (0U)
+#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
+#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_CALFACT_Pos (0U)
+#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_LFMEN_Pos (25U)
+#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
+#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
+#define ADC_CCR_TSEN_Pos (23U)
+#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+/************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN_Pos (0U)
+#define COMP_CSR_COMP1EN_Msk (0x1UL << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
+#define COMP_CSR_COMP1INNSEL_Pos (4U)
+#define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
+#define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP1WM_Pos (8U)
+#define COMP_CSR_COMP1WM_Msk (0x1UL << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */
+#define COMP_CSR_COMP1LPTIM1IN1_Pos (12U)
+#define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP1POLARITY_Pos (15U)
+#define COMP_CSR_COMP1POLARITY_Msk (0x1UL << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1VALUE_Pos (30U)
+#define COMP_CSR_COMP1VALUE_Msk (0x1UL << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK_Pos (31U)
+#define COMP_CSR_COMP1LOCK_Msk (0x1UL << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN_Pos (0U)
+#define COMP_CSR_COMP2EN_Msk (0x1UL << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
+#define COMP_CSR_COMP2SPEED_Pos (3U)
+#define COMP_CSR_COMP2SPEED_Msk (0x1UL << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */
+#define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */
+#define COMP_CSR_COMP2INNSEL_Pos (4U)
+#define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */
+#define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
+#define COMP_CSR_COMP2INPSEL_Pos (8U)
+#define COMP_CSR_COMP2INPSEL_Msk (0x7UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */
+#define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2INPSEL_0 (0x1UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP2INPSEL_1 (0x2UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */
+#define COMP_CSR_COMP2INPSEL_2 (0x4UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */
+#define COMP_CSR_COMP2LPTIM1IN2_Pos (12U)
+#define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */
+#define COMP_CSR_COMP2LPTIM1IN1_Pos (13U)
+#define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */
+#define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP2POLARITY_Pos (15U)
+#define COMP_CSR_COMP2POLARITY_Msk (0x1UL << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2VALUE_Pos (30U)
+#define COMP_CSR_COMP2VALUE_Msk (0x1UL << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK_Pos (31U)
+#define COMP_CSR_COMP2LOCK_Msk (0x1UL << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
+
+/********************** Bit definition for COMP_CSR register common ****************/
+#define COMP_CSR_COMPxEN_Pos (0U)
+#define COMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
+#define COMP_CSR_COMPxPOLARITY_Pos (15U)
+#define COMP_CSR_COMPxPOLARITY_Msk (0x1UL << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */
+#define COMP_CSR_COMPxOUTVALUE_Pos (30U)
+#define COMP_CSR_COMPxOUTVALUE_Msk (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK_Pos (31U)
+#define COMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
+
+/* Reference defines */
+#define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR (0xFFU) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos (3U)
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos (5U)
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos (7U)
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT_Pos (0U)
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL_Pos (0U)
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* CRS Clock Recovery System */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRS_CR register *********************/
+#define CRS_CR_SYNCOKIE_Pos (0U)
+#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
+#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /* SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE_Pos (1U)
+#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
+#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /* SYNC warning interrupt enable */
+#define CRS_CR_ERRIE_Pos (2U)
+#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
+#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /* SYNC error interrupt enable */
+#define CRS_CR_ESYNCIE_Pos (3U)
+#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
+#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /* Expected SYNC(ESYNCF) interrupt Enable*/
+#define CRS_CR_CEN_Pos (5U)
+#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
+#define CRS_CR_CEN CRS_CR_CEN_Msk /* Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN_Pos (6U)
+#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
+#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /* Automatic trimming enable */
+#define CRS_CR_SWSYNC_Pos (7U)
+#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
+#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /* A Software SYNC event is generated */
+#define CRS_CR_TRIM_Pos (8U)
+#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
+#define CRS_CR_TRIM CRS_CR_TRIM_Msk /* HSI48 oscillator smooth trimming */
+
+/******************* Bit definition for CRS_CFGR register *********************/
+#define CRS_CFGR_RELOAD_Pos (0U)
+#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
+#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /* Counter reload value */
+#define CRS_CFGR_FELIM_Pos (16U)
+#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
+#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /* Frequency error limit */
+
+#define CRS_CFGR_SYNCDIV_Pos (24U)
+#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
+#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /* SYNC divider */
+#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
+#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
+#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
+
+#define CRS_CFGR_SYNCSRC_Pos (28U)
+#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
+#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /* SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
+#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
+
+#define CRS_CFGR_SYNCPOL_Pos (31U)
+#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
+#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /* SYNC polarity selection */
+
+/******************* Bit definition for CRS_ISR register *********************/
+#define CRS_ISR_SYNCOKF_Pos (0U)
+#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
+#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /* SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF_Pos (1U)
+#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
+#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /* SYNC warning */
+#define CRS_ISR_ERRF_Pos (2U)
+#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
+#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /* SYNC error flag */
+#define CRS_ISR_ESYNCF_Pos (3U)
+#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
+#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /* Expected SYNC flag */
+#define CRS_ISR_SYNCERR_Pos (8U)
+#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
+#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /* SYNC error */
+#define CRS_ISR_SYNCMISS_Pos (9U)
+#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
+#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /* SYNC missed */
+#define CRS_ISR_TRIMOVF_Pos (10U)
+#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
+#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /* Trimming overflow or underflow */
+#define CRS_ISR_FEDIR_Pos (15U)
+#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
+#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /* Frequency error direction */
+#define CRS_ISR_FECAP_Pos (16U)
+#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
+#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /* Frequency error capture */
+
+/******************* Bit definition for CRS_ICR register *********************/
+#define CRS_ICR_SYNCOKC_Pos (0U)
+#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
+#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /* SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC_Pos (1U)
+#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
+#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /* SYNC warning clear flag */
+#define CRS_ICR_ERRC_Pos (2U)
+#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
+#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /* Error clear flag */
+#define CRS_ICR_ESYNCC_Pos (3U)
+#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
+#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /* Expected SYNC clear flag */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter (DAC) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos (1U)
+#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos (2U)
+#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (3U)
+#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos (13U)
+#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun interrupt enable */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1_Pos (13U)
+#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_Pos (0U)
+#define DBGMCU_CR_DBG_Msk (0x7UL << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
+#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+
+/******************* Bit definition for DMA_CSELR register *******************/
+#define DMA_CSELR_C1S_Pos (0U)
+#define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
+#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos (4U)
+#define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
+#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos (8U)
+#define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
+#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos (12U)
+#define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
+#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos (16U)
+#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
+#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S_Pos (20U)
+#define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
+#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S_Pos (24U)
+#define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
+#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_IM0_Pos (0U)
+#define EXTI_IMR_IM0_Msk (0x1UL << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_IM1_Pos (1U)
+#define EXTI_IMR_IM1_Msk (0x1UL << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_IM2_Pos (2U)
+#define EXTI_IMR_IM2_Msk (0x1UL << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_IM3_Pos (3U)
+#define EXTI_IMR_IM3_Msk (0x1UL << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_IM4_Pos (4U)
+#define EXTI_IMR_IM4_Msk (0x1UL << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_IM5_Pos (5U)
+#define EXTI_IMR_IM5_Msk (0x1UL << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_IM6_Pos (6U)
+#define EXTI_IMR_IM6_Msk (0x1UL << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_IM7_Pos (7U)
+#define EXTI_IMR_IM7_Msk (0x1UL << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_IM8_Pos (8U)
+#define EXTI_IMR_IM8_Msk (0x1UL << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_IM9_Pos (9U)
+#define EXTI_IMR_IM9_Msk (0x1UL << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_IM10_Pos (10U)
+#define EXTI_IMR_IM10_Msk (0x1UL << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_IM11_Pos (11U)
+#define EXTI_IMR_IM11_Msk (0x1UL << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_IM12_Pos (12U)
+#define EXTI_IMR_IM12_Msk (0x1UL << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_IM13_Pos (13U)
+#define EXTI_IMR_IM13_Msk (0x1UL << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_IM14_Pos (14U)
+#define EXTI_IMR_IM14_Msk (0x1UL << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_IM15_Pos (15U)
+#define EXTI_IMR_IM15_Msk (0x1UL << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_IM16_Pos (16U)
+#define EXTI_IMR_IM16_Msk (0x1UL << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_IM17_Pos (17U)
+#define EXTI_IMR_IM17_Msk (0x1UL << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_IM18_Pos (18U)
+#define EXTI_IMR_IM18_Msk (0x1UL << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_IM19_Pos (19U)
+#define EXTI_IMR_IM19_Msk (0x1UL << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_IM20_Pos (20U)
+#define EXTI_IMR_IM20_Msk (0x1UL << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_IM21_Pos (21U)
+#define EXTI_IMR_IM21_Msk (0x1UL << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_IM22_Pos (22U)
+#define EXTI_IMR_IM22_Msk (0x1UL << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_IM23_Pos (23U)
+#define EXTI_IMR_IM23_Msk (0x1UL << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
+#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_IM25_Pos (25U)
+#define EXTI_IMR_IM25_Msk (0x1UL << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */
+#define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_IM26_Pos (26U)
+#define EXTI_IMR_IM26_Msk (0x1UL << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
+#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_IM28_Pos (28U)
+#define EXTI_IMR_IM28_Msk (0x1UL << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
+#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_IM29_Pos (29U)
+#define EXTI_IMR_IM29_Msk (0x1UL << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
+#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
+
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x36FFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x36FFFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_EM0_Pos (0U)
+#define EXTI_EMR_EM0_Msk (0x1UL << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_EM1_Pos (1U)
+#define EXTI_EMR_EM1_Msk (0x1UL << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_EM2_Pos (2U)
+#define EXTI_EMR_EM2_Msk (0x1UL << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_EM3_Pos (3U)
+#define EXTI_EMR_EM3_Msk (0x1UL << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_EM4_Pos (4U)
+#define EXTI_EMR_EM4_Msk (0x1UL << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_EM5_Pos (5U)
+#define EXTI_EMR_EM5_Msk (0x1UL << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_EM6_Pos (6U)
+#define EXTI_EMR_EM6_Msk (0x1UL << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_EM7_Pos (7U)
+#define EXTI_EMR_EM7_Msk (0x1UL << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_EM8_Pos (8U)
+#define EXTI_EMR_EM8_Msk (0x1UL << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_EM9_Pos (9U)
+#define EXTI_EMR_EM9_Msk (0x1UL << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_EM10_Pos (10U)
+#define EXTI_EMR_EM10_Msk (0x1UL << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_EM11_Pos (11U)
+#define EXTI_EMR_EM11_Msk (0x1UL << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_EM12_Pos (12U)
+#define EXTI_EMR_EM12_Msk (0x1UL << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_EM13_Pos (13U)
+#define EXTI_EMR_EM13_Msk (0x1UL << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_EM14_Pos (14U)
+#define EXTI_EMR_EM14_Msk (0x1UL << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_EM15_Pos (15U)
+#define EXTI_EMR_EM15_Msk (0x1UL << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_EM16_Pos (16U)
+#define EXTI_EMR_EM16_Msk (0x1UL << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_EM17_Pos (17U)
+#define EXTI_EMR_EM17_Msk (0x1UL << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_EM18_Pos (18U)
+#define EXTI_EMR_EM18_Msk (0x1UL << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_EM19_Pos (19U)
+#define EXTI_EMR_EM19_Msk (0x1UL << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_EM20_Pos (20U)
+#define EXTI_EMR_EM20_Msk (0x1UL << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_EM21_Pos (21U)
+#define EXTI_EMR_EM21_Msk (0x1UL << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_EM22_Pos (22U)
+#define EXTI_EMR_EM22_Msk (0x1UL << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */
+#define EXTI_EMR_EM23_Pos (23U)
+#define EXTI_EMR_EM23_Msk (0x1UL << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
+#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
+#define EXTI_EMR_EM25_Pos (25U)
+#define EXTI_EMR_EM25_Msk (0x1UL << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */
+#define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */
+#define EXTI_EMR_EM26_Pos (26U)
+#define EXTI_EMR_EM26_Msk (0x1UL << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
+#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
+#define EXTI_EMR_EM28_Pos (28U)
+#define EXTI_EMR_EM28_Msk (0x1UL << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
+#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
+#define EXTI_EMR_EM29_Pos (29U)
+#define EXTI_EMR_EM29_Msk (0x1UL << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
+#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_RT0_Pos (0U)
+#define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_RT1_Pos (1U)
+#define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_RT2_Pos (2U)
+#define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_RT3_Pos (3U)
+#define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_RT4_Pos (4U)
+#define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_RT5_Pos (5U)
+#define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_RT6_Pos (6U)
+#define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_RT7_Pos (7U)
+#define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_RT8_Pos (8U)
+#define EXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_RT9_Pos (9U)
+#define EXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_RT10_Pos (10U)
+#define EXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_RT11_Pos (11U)
+#define EXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_RT12_Pos (12U)
+#define EXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_RT13_Pos (13U)
+#define EXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_RT14_Pos (14U)
+#define EXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_RT15_Pos (15U)
+#define EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_RT16_Pos (16U)
+#define EXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_RT17_Pos (17U)
+#define EXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_RT19_Pos (19U)
+#define EXTI_RTSR_RT19_Msk (0x1UL << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_RT20_Pos (20U)
+#define EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_RT21_Pos (21U)
+#define EXTI_RTSR_RT21_Msk (0x1UL << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_RT22_Pos (22U)
+#define EXTI_RTSR_RT22_Msk (0x1UL << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
+#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
+#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
+#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
+#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
+#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
+#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
+#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
+#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
+#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
+#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
+#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
+#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
+#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
+#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
+#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
+#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
+#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
+#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
+#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
+#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
+#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_FT0_Pos (0U)
+#define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_FT1_Pos (1U)
+#define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_FT2_Pos (2U)
+#define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_FT3_Pos (3U)
+#define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_FT4_Pos (4U)
+#define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_FT5_Pos (5U)
+#define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_FT6_Pos (6U)
+#define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_FT7_Pos (7U)
+#define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_FT8_Pos (8U)
+#define EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_FT9_Pos (9U)
+#define EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_FT10_Pos (10U)
+#define EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_FT11_Pos (11U)
+#define EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_FT12_Pos (12U)
+#define EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_FT13_Pos (13U)
+#define EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_FT14_Pos (14U)
+#define EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_FT15_Pos (15U)
+#define EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_FT16_Pos (16U)
+#define EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_FT17_Pos (17U)
+#define EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_FT19_Pos (19U)
+#define EXTI_FTSR_FT19_Msk (0x1UL << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_FT20_Pos (20U)
+#define EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_FT21_Pos (21U)
+#define EXTI_FTSR_FT21_Msk (0x1UL << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_FT22_Pos (22U)
+#define EXTI_FTSR_FT22_Msk (0x1UL << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
+#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
+#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
+#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
+#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
+#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
+#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
+#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
+#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
+#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
+#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
+#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
+#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
+#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
+#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
+#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
+#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
+#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
+#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
+#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
+#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
+#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWI0_Pos (0U)
+#define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWI1_Pos (1U)
+#define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWI2_Pos (2U)
+#define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWI3_Pos (3U)
+#define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWI4_Pos (4U)
+#define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWI5_Pos (5U)
+#define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWI6_Pos (6U)
+#define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWI7_Pos (7U)
+#define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWI8_Pos (8U)
+#define EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWI9_Pos (9U)
+#define EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWI10_Pos (10U)
+#define EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWI11_Pos (11U)
+#define EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWI12_Pos (12U)
+#define EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWI13_Pos (13U)
+#define EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWI14_Pos (14U)
+#define EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWI15_Pos (15U)
+#define EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWI16_Pos (16U)
+#define EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWI17_Pos (17U)
+#define EXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWI19_Pos (19U)
+#define EXTI_SWIER_SWI19_Msk (0x1UL << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWI20_Pos (20U)
+#define EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWI21_Pos (21U)
+#define EXTI_SWIER_SWI21_Msk (0x1UL << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWI22_Pos (22U)
+#define EXTI_SWIER_SWI22_Msk (0x1UL << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
+
+/* Legacy defines */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PIF0_Pos (0U)
+#define EXTI_PR_PIF0_Msk (0x1UL << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
+#define EXTI_PR_PIF1_Pos (1U)
+#define EXTI_PR_PIF1_Msk (0x1UL << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
+#define EXTI_PR_PIF2_Pos (2U)
+#define EXTI_PR_PIF2_Msk (0x1UL << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
+#define EXTI_PR_PIF3_Pos (3U)
+#define EXTI_PR_PIF3_Msk (0x1UL << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
+#define EXTI_PR_PIF4_Pos (4U)
+#define EXTI_PR_PIF4_Msk (0x1UL << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
+#define EXTI_PR_PIF5_Pos (5U)
+#define EXTI_PR_PIF5_Msk (0x1UL << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
+#define EXTI_PR_PIF6_Pos (6U)
+#define EXTI_PR_PIF6_Msk (0x1UL << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
+#define EXTI_PR_PIF7_Pos (7U)
+#define EXTI_PR_PIF7_Msk (0x1UL << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
+#define EXTI_PR_PIF8_Pos (8U)
+#define EXTI_PR_PIF8_Msk (0x1UL << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
+#define EXTI_PR_PIF9_Pos (9U)
+#define EXTI_PR_PIF9_Msk (0x1UL << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
+#define EXTI_PR_PIF10_Pos (10U)
+#define EXTI_PR_PIF10_Msk (0x1UL << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
+#define EXTI_PR_PIF11_Pos (11U)
+#define EXTI_PR_PIF11_Msk (0x1UL << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
+#define EXTI_PR_PIF12_Pos (12U)
+#define EXTI_PR_PIF12_Msk (0x1UL << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
+#define EXTI_PR_PIF13_Pos (13U)
+#define EXTI_PR_PIF13_Msk (0x1UL << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
+#define EXTI_PR_PIF14_Pos (14U)
+#define EXTI_PR_PIF14_Msk (0x1UL << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
+#define EXTI_PR_PIF15_Pos (15U)
+#define EXTI_PR_PIF15_Msk (0x1UL << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
+#define EXTI_PR_PIF16_Pos (16U)
+#define EXTI_PR_PIF16_Msk (0x1UL << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
+#define EXTI_PR_PIF17_Pos (17U)
+#define EXTI_PR_PIF17_Msk (0x1UL << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
+#define EXTI_PR_PIF19_Pos (19U)
+#define EXTI_PR_PIF19_Msk (0x1UL << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
+#define EXTI_PR_PIF20_Pos (20U)
+#define EXTI_PR_PIF20_Msk (0x1UL << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
+#define EXTI_PR_PIF21_Pos (21U)
+#define EXTI_PR_PIF21_Msk (0x1UL << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
+#define EXTI_PR_PIF22_Pos (22U)
+#define EXTI_PR_PIF22_Msk (0x1UL << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
+
+/* Legacy defines */
+#define EXTI_PR_PR0 EXTI_PR_PIF0
+#define EXTI_PR_PR1 EXTI_PR_PIF1
+#define EXTI_PR_PR2 EXTI_PR_PIF2
+#define EXTI_PR_PR3 EXTI_PR_PIF3
+#define EXTI_PR_PR4 EXTI_PR_PIF4
+#define EXTI_PR_PR5 EXTI_PR_PIF5
+#define EXTI_PR_PR6 EXTI_PR_PIF6
+#define EXTI_PR_PR7 EXTI_PR_PIF7
+#define EXTI_PR_PR8 EXTI_PR_PIF8
+#define EXTI_PR_PR9 EXTI_PR_PIF9
+#define EXTI_PR_PR10 EXTI_PR_PIF10
+#define EXTI_PR_PR11 EXTI_PR_PIF11
+#define EXTI_PR_PR12 EXTI_PR_PIF12
+#define EXTI_PR_PR13 EXTI_PR_PIF13
+#define EXTI_PR_PR14 EXTI_PR_PIF14
+#define EXTI_PR_PR15 EXTI_PR_PIF15
+#define EXTI_PR_PR16 EXTI_PR_PIF16
+#define EXTI_PR_PR17 EXTI_PR_PIF17
+#define EXTI_PR_PR19 EXTI_PR_PIF19
+#define EXTI_PR_PR20 EXTI_PR_PIF20
+#define EXTI_PR_PR21 EXTI_PR_PIF21
+#define EXTI_PR_PR22 EXTI_PR_PIF22
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
+#define FLASH_ACR_PRFTEN_Pos (1U)
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_SLEEP_PD_Pos (3U)
+#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD_Pos (4U)
+#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
+#define FLASH_ACR_DISAB_BUF_Pos (5U)
+#define FLASH_ACR_DISAB_BUF_Msk (0x1UL << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
+#define FLASH_ACR_PRE_READ_Pos (6U)
+#define FLASH_ACR_PRE_READ_Msk (0x1UL << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
+#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
+
+/******************* Bit definition for FLASH_PECR register ******************/
+#define FLASH_PECR_PELOCK_Pos (0U)
+#define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
+#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK_Pos (1U)
+#define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
+#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK_Pos (2U)
+#define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
+#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG_Pos (3U)
+#define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
+#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
+#define FLASH_PECR_DATA_Pos (4U)
+#define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
+#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
+#define FLASH_PECR_FIX_Pos (8U)
+#define FLASH_PECR_FIX_Msk (0x1UL << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
+#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE_Pos (9U)
+#define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
+#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
+#define FLASH_PECR_FPRG_Pos (10U)
+#define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
+#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_EOPIE_Pos (16U)
+#define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
+#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
+#define FLASH_PECR_ERRIE_Pos (17U)
+#define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
+#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
+#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
+#define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
+#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
+#define FLASH_PECR_HALF_ARRAY_Pos (19U)
+#define FLASH_PECR_HALF_ARRAY_Msk (0x1UL << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
+#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
+
+/****************** Bit definition for FLASH_PDKEYR register ******************/
+#define FLASH_PDKEYR_PDKEYR_Pos (0U)
+#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PEKEYR register ******************/
+#define FLASH_PEKEYR_PEKEYR_Pos (0U)
+#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PRGKEYR register ******************/
+#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
+#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
+
+/****************** Bit definition for FLASH_OPTKEYR register ******************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_EOP_Pos (1U)
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
+#define FLASH_SR_HVOFF_Pos (2U)
+#define FLASH_SR_HVOFF_Msk (0x1UL << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
+#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
+#define FLASH_SR_READY_Pos (3U)
+#define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */
+#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR_Pos (8U)
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
+#define FLASH_SR_PGAERR_Pos (9U)
+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR_Pos (10U)
+#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
+#define FLASH_SR_OPTVERR_Pos (11U)
+#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
+#define FLASH_SR_RDERR_Pos (13U)
+#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
+#define FLASH_SR_NOTZEROERR_Pos (16U)
+#define FLASH_SR_NOTZEROERR_Msk (0x1UL << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
+#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
+#define FLASH_SR_FWWERR_Pos (17U)
+#define FLASH_SR_FWWERR_Msk (0x1UL << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
+#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
+
+/* Legacy defines */
+#define FLASH_SR_FWWER FLASH_SR_FWWERR
+#define FLASH_SR_ENHV FLASH_SR_HVOFF
+#define FLASH_SR_ENDHV FLASH_SR_HVOFF
+
+/****************** Bit definition for FLASH_OPTR register *******************/
+#define FLASH_OPTR_RDPROT_Pos (0U)
+#define FLASH_OPTR_RDPROT_Msk (0xFFUL << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
+#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
+#define FLASH_OPTR_WPRMOD_Pos (8U)
+#define FLASH_OPTR_WPRMOD_Msk (0x1UL << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
+#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
+#define FLASH_OPTR_BOR_LEV_Pos (16U)
+#define FLASH_OPTR_BOR_LEV_Msk (0xFUL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
+#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OPTR_IWDG_SW_Pos (20U)
+#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
+#define FLASH_OPTR_nRST_STOP_Pos (21U)
+#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OPTR_nRST_STDBY_Pos (22U)
+#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OPTR_USER_Pos (20U)
+#define FLASH_OPTR_USER_Msk (0x7UL << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
+#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OPTR_BOOT1_Pos (31U)
+#define FLASH_OPTR_BOOT1_Msk (0x1UL << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
+#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 (0x00000001U)
+#define GPIO_OTYPER_OT_1 (0x00000002U)
+#define GPIO_OTYPER_OT_2 (0x00000004U)
+#define GPIO_OTYPER_OT_3 (0x00000008U)
+#define GPIO_OTYPER_OT_4 (0x00000010U)
+#define GPIO_OTYPER_OT_5 (0x00000020U)
+#define GPIO_OTYPER_OT_6 (0x00000040U)
+#define GPIO_OTYPER_OT_7 (0x00000080U)
+#define GPIO_OTYPER_OT_8 (0x00000100U)
+#define GPIO_OTYPER_OT_9 (0x00000200U)
+#define GPIO_OTYPER_OT_10 (0x00000400U)
+#define GPIO_OTYPER_OT_11 (0x00000800U)
+#define GPIO_OTYPER_OT_12 (0x00001000U)
+#define GPIO_OTYPER_OT_13 (0x00002000U)
+#define GPIO_OTYPER_OT_14 (0x00004000U)
+#define GPIO_OTYPER_OT_15 (0x00008000U)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDER_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
+#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDER_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
+#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDER_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
+#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDER_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
+#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDER_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
+#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDER_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
+#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDER_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
+#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDER_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
+#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDER_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
+#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDER_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
+#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDER_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
+#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDER_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
+#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDER_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
+#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDER_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
+#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDER_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
+#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDER_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
+#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 (0x00000001U)
+#define GPIO_BSRR_BS_1 (0x00000002U)
+#define GPIO_BSRR_BS_2 (0x00000004U)
+#define GPIO_BSRR_BS_3 (0x00000008U)
+#define GPIO_BSRR_BS_4 (0x00000010U)
+#define GPIO_BSRR_BS_5 (0x00000020U)
+#define GPIO_BSRR_BS_6 (0x00000040U)
+#define GPIO_BSRR_BS_7 (0x00000080U)
+#define GPIO_BSRR_BS_8 (0x00000100U)
+#define GPIO_BSRR_BS_9 (0x00000200U)
+#define GPIO_BSRR_BS_10 (0x00000400U)
+#define GPIO_BSRR_BS_11 (0x00000800U)
+#define GPIO_BSRR_BS_12 (0x00001000U)
+#define GPIO_BSRR_BS_13 (0x00002000U)
+#define GPIO_BSRR_BS_14 (0x00004000U)
+#define GPIO_BSRR_BS_15 (0x00008000U)
+#define GPIO_BSRR_BR_0 (0x00010000U)
+#define GPIO_BSRR_BR_1 (0x00020000U)
+#define GPIO_BSRR_BR_2 (0x00040000U)
+#define GPIO_BSRR_BR_3 (0x00080000U)
+#define GPIO_BSRR_BR_4 (0x00100000U)
+#define GPIO_BSRR_BR_5 (0x00200000U)
+#define GPIO_BSRR_BR_6 (0x00400000U)
+#define GPIO_BSRR_BR_7 (0x00800000U)
+#define GPIO_BSRR_BR_8 (0x01000000U)
+#define GPIO_BSRR_BR_9 (0x02000000U)
+#define GPIO_BSRR_BR_10 (0x04000000U)
+#define GPIO_BSRR_BR_11 (0x08000000U)
+#define GPIO_BSRR_BR_12 (0x10000000U)
+#define GPIO_BSRR_BR_13 (0x20000000U)
+#define GPIO_BSRR_BR_14 (0x40000000U)
+#define GPIO_BSRR_BR_15 (0x80000000U)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 (0x00000001U)
+#define GPIO_BRR_BR_1 (0x00000002U)
+#define GPIO_BRR_BR_2 (0x00000004U)
+#define GPIO_BRR_BR_3 (0x00000008U)
+#define GPIO_BRR_BR_4 (0x00000010U)
+#define GPIO_BRR_BR_5 (0x00000020U)
+#define GPIO_BRR_BR_6 (0x00000040U)
+#define GPIO_BRR_BR_7 (0x00000080U)
+#define GPIO_BRR_BR_8 (0x00000100U)
+#define GPIO_BRR_BR_9 (0x00000200U)
+#define GPIO_BRR_BR_10 (0x00000400U)
+#define GPIO_BRR_BR_11 (0x00000800U)
+#define GPIO_BRR_BR_12 (0x00001000U)
+#define GPIO_BRR_BR_13 (0x00002000U)
+#define GPIO_BRR_BR_14 (0x00004000U)
+#define GPIO_BRR_BR_15 (0x00008000U)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos (1U)
+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos (2U)
+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos (3U)
+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos (4U)
+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos (5U)
+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos (6U)
+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos (7U)
+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos (8U)
+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos (12U)
+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos (14U)
+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos (15U)
+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos (16U)
+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos (17U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos (18U)
+#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos (19U)
+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos (20U)
+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos (21U)
+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos (22U)
+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos (23U)
+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD_Pos (0U)
+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos (10U)
+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos (11U)
+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos (12U)
+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos (13U)
+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
+#define I2C_CR2_STOP_Pos (14U)
+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos (15U)
+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos (16U)
+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos (24U)
+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos (25U)
+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos (26U)
+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1_Pos (0U)
+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos (10U)
+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos (15U)
+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2_Pos (1U)
+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos (8U)
+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos (8U)
+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos (9U)
+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos (8U)
+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos (10U)
+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos (8U)
+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos (9U)
+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos (8U)
+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos (15U)
+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos (0U)
+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos (8U)
+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos (16U)
+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos (20U)
+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos (28U)
+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE_Pos (0U)
+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos (1U)
+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos (2U)
+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos (3U)
+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos (4U)
+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos (5U)
+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos (6U)
+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos (7U)
+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos (8U)
+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
+#define I2C_ISR_ARLO_Pos (9U)
+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos (10U)
+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos (11U)
+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos (12U)
+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos (13U)
+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos (15U)
+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
+#define I2C_ISR_DIR_Pos (16U)
+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos (17U)
+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF_Pos (3U)
+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos (4U)
+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos (5U)
+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos (8U)
+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos (9U)
+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos (10U)
+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos (11U)
+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos (12U)
+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos (13U)
+#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define I2C_PECR_PEC_Pos (0U)
+#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA_Pos (0U)
+#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA_Pos (0U)
+#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos (2U)
+#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN_Pos (0U)
+#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM_Pos (0U)
+#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos (1U)
+#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos (2U)
+#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos (3U)
+#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos (4U)
+#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos (5U)
+#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos (6U)
+#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF_Pos (0U)
+#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos (1U)
+#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos (3U)
+#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos (4U)
+#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos (5U)
+#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos (6U)
+#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos (0U)
+#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos (1U)
+#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos (3U)
+#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos (4U)
+#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos (5U)
+#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos (6U)
+#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos (0U)
+#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos (1U)
+#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos (3U)
+#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos (6U)
+#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos (9U)
+#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos (17U)
+#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos (19U)
+#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos (20U)
+#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos (21U)
+#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos (22U)
+#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos (24U)
+#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE_Pos (0U)
+#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos (1U)
+#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos (2U)
+#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP_Pos (0U)
+#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR_Pos (0U)
+#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT_Pos (0U)
+#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
+
+/******************************************************************************/
+/* */
+/* MIFARE Firewall */
+/* */
+/******************************************************************************/
+
+/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
+#define FW_CSSA_ADD_Pos (8U)
+#define FW_CSSA_ADD_Msk (0xFFFFUL << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
+#define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
+#define FW_CSL_LENG_Pos (8U)
+#define FW_CSL_LENG_Msk (0x3FFFUL << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
+#define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
+#define FW_NVDSSA_ADD_Pos (8U)
+#define FW_NVDSSA_ADD_Msk (0xFFFFUL << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
+#define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
+#define FW_NVDSL_LENG_Pos (8U)
+#define FW_NVDSL_LENG_Msk (0x3FFFUL << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
+#define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
+#define FW_VDSSA_ADD_Pos (6U)
+#define FW_VDSSA_ADD_Msk (0x3FFUL << FW_VDSSA_ADD_Pos) /*!< 0x0000FFC0 */
+#define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
+#define FW_VDSL_LENG_Pos (6U)
+#define FW_VDSL_LENG_Msk (0x3FFUL << FW_VDSL_LENG_Pos) /*!< 0x0000FFC0 */
+#define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
+
+/**************************Bit definition for CR register *********************/
+#define FW_CR_FPA_Pos (0U)
+#define FW_CR_FPA_Msk (0x1UL << FW_CR_FPA_Pos) /*!< 0x00000001 */
+#define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
+#define FW_CR_VDS_Pos (1U)
+#define FW_CR_VDS_Msk (0x1UL << FW_CR_VDS_Pos) /*!< 0x00000002 */
+#define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
+#define FW_CR_VDE_Pos (2U)
+#define FW_CR_VDE_Msk (0x1UL << FW_CR_VDE_Pos) /*!< 0x00000004 */
+#define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
+
+/******************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/******************************************************************************/
+
+#define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPSDSR_Pos (0U)
+#define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP_Pos (9U)
+#define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /*!< 0x00000200 */
+#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
+#define PWR_CR_FWU_Pos (10U)
+#define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /*!< 0x00000400 */
+#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
+
+#define PWR_CR_VOS_Pos (11U)
+#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x00001800 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /*!< 0x00000800 */
+#define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /*!< 0x00001000 */
+#define PWR_CR_DSEEKOFF_Pos (13U)
+#define PWR_CR_DSEEKOFF_Msk (0x1UL << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */
+#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */
+#define PWR_CR_LPRUN_Pos (14U)
+#define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
+#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF_Pos (3U)
+#define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
+#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF_Pos (4U)
+#define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
+#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF_Pos (5U)
+#define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
+#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1_Pos (8U)
+#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2_Pos (9U)
+#define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
+#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+#define RCC_HSI48_SUPPORT /*!< HSI48 feature support */
+#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos (1U)
+#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos (2U)
+#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIVEN_Pos (3U)
+#define RCC_CR_HSIDIVEN_Msk (0x1UL << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */
+#define RCC_CR_HSIDIVF_Pos (4U)
+#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */
+#define RCC_CR_MSION_Pos (8U)
+#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000100 */
+#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY_Pos (9U)
+#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
+#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON_Pos (19U)
+#define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */
+#define RCC_CR_RTCPRE_Pos (20U)
+#define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
+#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */
+#define RCC_CR_RTCPRE_0 (0x1UL << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */
+#define RCC_CR_RTCPRE_1 (0x2UL << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+/* Reference defines */
+#define RCC_CR_CSSON RCC_CR_CSSHSEON
+
+/******************** Bit definition for RCC_ICSCR register *****************/
+#define RCC_ICSCR_HSICAL_Pos (0U)
+#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
+#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM_Pos (8U)
+#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
+#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE_Pos (13U)
+#define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
+#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
+#define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
+#define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
+#define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
+#define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
+#define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
+#define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
+#define RCC_ICSCR_MSICAL_Pos (16U)
+#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
+#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM_Pos (24U)
+#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
+#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
+
+/******************** Bit definition for RCC_CRRCR register *****************/
+#define RCC_CRRCR_HSI48ON_Pos (0U)
+#define RCC_CRRCR_HSI48ON_Msk (0x1UL << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
+#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk /*!< HSI 48MHz clock enable */
+#define RCC_CRRCR_HSI48RDY_Pos (1U)
+#define RCC_CRRCR_HSI48RDY_Msk (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
+#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk /*!< HSI 48MHz clock ready flag */
+#define RCC_CRRCR_HSI48CAL_Pos (8U)
+#define RCC_CRRCR_HSI48CAL_Msk (0xFFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI 48MHz clock Calibration */
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos (15U)
+#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */
+
+/*!< PLL entry clock source*/
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
+
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL_Pos (18U)
+#define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV_Pos (22U)
+#define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
+
+#define RCC_CFGR_PLLDIV2_Pos (22U)
+#define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3_Pos (23U)
+#define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4_Pos (22U)
+#define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCOSEL_Pos (24U)
+#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
+#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
+
+#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
+#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCOSEL_HSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_MSI_Pos (24U)
+#define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
+#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_HSE_Pos (26U)
+#define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCOSEL_PLL_Pos (24U)
+#define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
+#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
+#define RCC_CFGR_MCOSEL_LSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
+#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
+#define RCC_CFGR_MCOSEL_LSE_Pos (24U)
+#define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
+#define RCC_CFGR_MCOSEL_HSI48_Pos (27U)
+#define RCC_CFGR_MCOSEL_HSI48_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */
+#define RCC_CFGR_MCOSEL_HSI48 RCC_CFGR_MCOSEL_HSI48_Msk /*!< HSI48 clock selected as MCO source */
+
+#define RCC_CFGR_MCOPRE_Pos (28U)
+#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
+
+#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
+
+/* Legacy defines */
+#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
+#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
+#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
+#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
+#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
+#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
+#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
+#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
+#ifdef RCC_CFGR_MCOSEL_HSI48
+#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48
+#endif
+
+#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
+#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
+
+/*!<****************** Bit definition for RCC_CIER register ********************/
+#define RCC_CIER_LSIRDYIE_Pos (0U)
+#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIER_LSERDYIE_Pos (1U)
+#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIER_HSIRDYIE_Pos (2U)
+#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIER_HSERDYIE_Pos (3U)
+#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIER_PLLRDYIE_Pos (4U)
+#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIER_MSIRDYIE_Pos (5U)
+#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
+#define RCC_CIER_HSI48RDYIE_Pos (6U)
+#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000040 */
+#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk /*!< HSI48 Ready Interrupt Enable */
+#define RCC_CIER_CSSLSE_Pos (7U)
+#define RCC_CIER_CSSLSE_Msk (0x1UL << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */
+
+/* Reference defines */
+#define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
+
+/*!<****************** Bit definition for RCC_CIFR register ********************/
+#define RCC_CIFR_LSIRDYF_Pos (0U)
+#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIFR_LSERDYF_Pos (1U)
+#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIFR_HSIRDYF_Pos (2U)
+#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIFR_HSERDYF_Pos (3U)
+#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIFR_PLLRDYF_Pos (4U)
+#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIFR_MSIRDYF_Pos (5U)
+#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
+#define RCC_CIFR_HSI48RDYF_Pos (6U)
+#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk /*!< HSI48 Ready Interrupt flag */
+#define RCC_CIFR_CSSLSEF_Pos (7U)
+#define RCC_CIFR_CSSLSEF_Msk (0x1UL << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */
+#define RCC_CIFR_CSSHSEF_Pos (8U)
+#define RCC_CIFR_CSSHSEF_Msk (0x1UL << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */
+#define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */
+
+/* Reference defines */
+#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
+#define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
+
+/*!<****************** Bit definition for RCC_CICR register ********************/
+#define RCC_CICR_LSIRDYC_Pos (0U)
+#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CICR_LSERDYC_Pos (1U)
+#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CICR_HSIRDYC_Pos (2U)
+#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CICR_HSERDYC_Pos (3U)
+#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CICR_PLLRDYC_Pos (4U)
+#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CICR_MSIRDYC_Pos (5U)
+#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
+#define RCC_CICR_HSI48RDYC_Pos (6U)
+#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000040 */
+#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk /*!< HSI48 Ready Interrupt Clear */
+#define RCC_CICR_CSSLSEC_Pos (7U)
+#define RCC_CICR_CSSLSEC_Msk (0x1UL << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */
+#define RCC_CICR_CSSHSEC_Pos (8U)
+#define RCC_CICR_CSSHSEC_Msk (0x1UL << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */
+#define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */
+
+/* Reference defines */
+#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
+#define RCC_CICR_CSSC RCC_CICR_CSSHSEC
+/***************** Bit definition for RCC_IOPRSTR register ******************/
+#define RCC_IOPRSTR_IOPARST_Pos (0U)
+#define RCC_IOPRSTR_IOPARST_Msk (0x1UL << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */
+#define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */
+#define RCC_IOPRSTR_IOPBRST_Pos (1U)
+#define RCC_IOPRSTR_IOPBRST_Msk (0x1UL << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */
+#define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */
+#define RCC_IOPRSTR_IOPCRST_Pos (2U)
+#define RCC_IOPRSTR_IOPCRST_Msk (0x1UL << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */
+#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */
+#define RCC_IOPRSTR_IOPDRST_Pos (3U)
+#define RCC_IOPRSTR_IOPDRST_Msk (0x1UL << RCC_IOPRSTR_IOPDRST_Pos) /*!< 0x00000008 */
+#define RCC_IOPRSTR_IOPDRST RCC_IOPRSTR_IOPDRST_Msk /*!< GPIO port D reset */
+#define RCC_IOPRSTR_IOPHRST_Pos (7U)
+#define RCC_IOPRSTR_IOPHRST_Msk (0x1UL << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */
+#define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */
+
+/* Reference defines */
+#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
+#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
+#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
+#define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_IOPDRST /*!< GPIO port D reset */
+#define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
+
+
+/****************** Bit definition for RCC_AHBRST register ******************/
+#define RCC_AHBRSTR_DMARST_Pos (0U)
+#define RCC_AHBRSTR_DMARST_Msk (0x1UL << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */
+#define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */
+#define RCC_AHBRSTR_MIFRST_Pos (8U)
+#define RCC_AHBRSTR_MIFRST_Msk (0x1UL << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */
+#define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset */
+#define RCC_AHBRSTR_CRCRST_Pos (12U)
+#define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */
+#define RCC_AHBRSTR_TSCRST_Pos (16U)
+#define RCC_AHBRSTR_TSCRST_Msk (0x1UL << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x00010000 */
+#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TSC reset */
+#define RCC_AHBRSTR_RNGRST_Pos (20U)
+#define RCC_AHBRSTR_RNGRST_Msk (0x1UL << RCC_AHBRSTR_RNGRST_Pos) /*!< 0x00100000 */
+#define RCC_AHBRSTR_RNGRST RCC_AHBRSTR_RNGRST_Msk /*!< RNG reset */
+
+/* Reference defines */
+#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
+#define RCC_APB2RSTR_TIM21RST_Pos (2U)
+#define RCC_APB2RSTR_TIM21RST_Msk (0x1UL << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 reset */
+#define RCC_APB2RSTR_TIM22RST_Pos (5U)
+#define RCC_APB2RSTR_TIM22RST_Msk (0x1UL << RCC_APB2RSTR_TIM22RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk /*!< TIM22 reset */
+#define RCC_APB2RSTR_ADCRST_Pos (9U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
+#define RCC_APB2RSTR_DBGRST_Pos (22U)
+#define RCC_APB2RSTR_DBGRST_Msk (0x1UL << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU reset */
+
+/* Reference defines */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 reset */
+#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU reset */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_LPUART1RST_Pos (18U)
+#define RCC_APB1RSTR_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
+#define RCC_APB1RSTR_USBRST_Pos (23U)
+#define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */
+#define RCC_APB1RSTR_CRSRST_Pos (27U)
+#define RCC_APB1RSTR_CRSRST_Msk (0x1UL << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
+#define RCC_APB1RSTR_DACRST_Pos (29U)
+#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC reset */
+#define RCC_APB1RSTR_LPTIM1RST_Pos (31U)
+#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 reset */
+
+/***************** Bit definition for RCC_IOPENR register ******************/
+#define RCC_IOPENR_IOPAEN_Pos (0U)
+#define RCC_IOPENR_IOPAEN_Msk (0x1UL << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */
+#define RCC_IOPENR_IOPBEN_Pos (1U)
+#define RCC_IOPENR_IOPBEN_Msk (0x1UL << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */
+#define RCC_IOPENR_IOPCEN_Pos (2U)
+#define RCC_IOPENR_IOPCEN_Msk (0x1UL << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */
+#define RCC_IOPENR_IOPDEN_Pos (3U)
+#define RCC_IOPENR_IOPDEN_Msk (0x1UL << RCC_IOPENR_IOPDEN_Pos) /*!< 0x00000008 */
+#define RCC_IOPENR_IOPDEN RCC_IOPENR_IOPDEN_Msk /*!< GPIO port D clock enable */
+#define RCC_IOPENR_IOPHEN_Pos (7U)
+#define RCC_IOPENR_IOPHEN_Msk (0x1UL << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */
+
+/* Reference defines */
+#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
+#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
+#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
+#define RCC_IOPENR_GPIODEN RCC_IOPENR_IOPDEN /*!< GPIO port D clock enable */
+#define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
+
+/***************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMAEN_Pos (0U)
+#define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_MIFEN_Pos (8U)
+#define RCC_AHBENR_MIFEN_Msk (0x1UL << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */
+#define RCC_AHBENR_CRCEN_Pos (12U)
+#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+#define RCC_AHBENR_TSCEN_Pos (16U)
+#define RCC_AHBENR_TSCEN_Msk (0x1UL << RCC_AHBENR_TSCEN_Pos) /*!< 0x00010000 */
+#define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TSC clock enable */
+#define RCC_AHBENR_RNGEN_Pos (20U)
+#define RCC_AHBENR_RNGEN_Msk (0x1UL << RCC_AHBENR_RNGEN_Pos) /*!< 0x00100000 */
+#define RCC_AHBENR_RNGEN RCC_AHBENR_RNGEN_Msk /*!< RNG clock enable */
+
+/* Reference defines */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register ******************/
+#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM21EN_Pos (2U)
+#define RCC_APB2ENR_TIM21EN_Msk (0x1UL << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */
+#define RCC_APB2ENR_TIM22EN_Pos (5U)
+#define RCC_APB2ENR_TIM22EN_Msk (0x1UL << RCC_APB2ENR_TIM22EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk /*!< TIM22 clock enable */
+#define RCC_APB2ENR_FWEN_Pos (7U)
+#define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADCEN_Pos (9U)
+#define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
+#define RCC_APB2ENR_DBGEN_Pos (22U)
+#define RCC_APB2ENR_DBGEN_Msk (0x1UL << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */
+
+/* Reference defines */
+
+#define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
+#define RCC_APB1ENR_LPUART1EN_Pos (18U)
+#define RCC_APB1ENR_LPUART1EN_Msk (0x1UL << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */
+#define RCC_APB1ENR_USBEN_Pos (23U)
+#define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */
+#define RCC_APB1ENR_CRSEN_Pos (27U)
+#define RCC_APB1ENR_CRSEN_Msk (0x1UL << RCC_APB1ENR_CRSEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
+#define RCC_APB1ENR_DACEN_Pos (29U)
+#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC clock enable */
+#define RCC_APB1ENR_LPTIM1EN_Pos (31U)
+#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */
+
+/****************** Bit definition for RCC_IOPSMENR register ****************/
+#define RCC_IOPSMENR_IOPASMEN_Pos (0U)
+#define RCC_IOPSMENR_IOPASMEN_Msk (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPBSMEN_Pos (1U)
+#define RCC_IOPSMENR_IOPBSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPCSMEN_Pos (2U)
+#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPDSMEN_Pos (3U)
+#define RCC_IOPSMENR_IOPDSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos) /*!< 0x00000008 */
+#define RCC_IOPSMENR_IOPDSMEN RCC_IOPSMENR_IOPDSMEN_Msk /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPHSMEN_Pos (7U)
+#define RCC_IOPSMENR_IOPHSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_IOPDSMEN /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_AHBSMENR register ******************/
+#define RCC_AHBSMENR_DMASMEN_Pos (0U)
+#define RCC_AHBSMENR_DMASMEN_Msk (0x1UL << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */
+#define RCC_AHBSMENR_MIFSMEN_Pos (8U)
+#define RCC_AHBSMENR_MIFSMEN_Msk (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */
+#define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
+#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRCSMEN_Pos (12U)
+#define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */
+#define RCC_AHBSMENR_TSCSMEN_Pos (16U)
+#define RCC_AHBSMENR_TSCSMEN_Msk (0x1UL << RCC_AHBSMENR_TSCSMEN_Pos) /*!< 0x00010000 */
+#define RCC_AHBSMENR_TSCSMEN RCC_AHBSMENR_TSCSMEN_Msk /*!< TSC clock enabled in sleep mode */
+#define RCC_AHBSMENR_RNGSMEN_Pos (20U)
+#define RCC_AHBSMENR_RNGSMEN_Msk (0x1UL << RCC_AHBSMENR_RNGSMEN_Pos) /*!< 0x00100000 */
+#define RCC_AHBSMENR_RNGSMEN RCC_AHBSMENR_RNGSMEN_Msk /*!< RNG clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB2SMENR register ******************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM21SMEN_Pos (2U)
+#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM22SMEN_Pos (5U)
+#define RCC_APB2SMENR_TIM22SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk /*!< TIM22 clock enabled in sleep mode */
+#define RCC_APB2SMENR_ADCSMEN_Pos (9U)
+#define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
+#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
+#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk /*!< USART1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGSMEN_Pos (22U)
+#define RCC_APB2SMENR_DBGSMEN_Msk (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB1SMENR register ******************/
+#define RCC_APB1SMENR_TIM2SMEN_Pos (0U)
+#define RCC_APB1SMENR_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_TIM6SMEN_Pos (4U)
+#define RCC_APB1SMENR_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM6SMEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1SMENR_TIM6SMEN RCC_APB1SMENR_TIM6SMEN_Msk /*!< Timer 6 clock enabled in sleep mode */
+#define RCC_APB1SMENR_WWDGSMEN_Pos (11U)
+#define RCC_APB1SMENR_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */
+#define RCC_APB1SMENR_SPI2SMEN_Pos (14U)
+#define RCC_APB1SMENR_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR_SPI2SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1SMENR_SPI2SMEN RCC_APB1SMENR_SPI2SMEN_Msk /*!< SPI2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART2SMEN_Pos (17U)
+#define RCC_APB1SMENR_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPUART1SMEN_Pos (18U)
+#define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C1SMEN_Pos (21U)
+#define RCC_APB1SMENR_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C2SMEN_Pos (22U)
+#define RCC_APB1SMENR_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1SMENR_I2C2SMEN RCC_APB1SMENR_I2C2SMEN_Msk /*!< I2C2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USBSMEN_Pos (23U)
+#define RCC_APB1SMENR_USBSMEN_Msk (0x1UL << RCC_APB1SMENR_USBSMEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1SMENR_USBSMEN RCC_APB1SMENR_USBSMEN_Msk /*!< USB clock enabled in sleep mode */
+#define RCC_APB1SMENR_CRSSMEN_Pos (27U)
+#define RCC_APB1SMENR_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR_CRSSMEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1SMENR_CRSSMEN RCC_APB1SMENR_CRSSMEN_Msk /*!< CRS clock enabled in sleep mode */
+#define RCC_APB1SMENR_PWRSMEN_Pos (28U)
+#define RCC_APB1SMENR_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */
+#define RCC_APB1SMENR_DACSMEN_Pos (29U)
+#define RCC_APB1SMENR_DACSMEN_Msk (0x1UL << RCC_APB1SMENR_DACSMEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1SMENR_DACSMEN RCC_APB1SMENR_DACSMEN_Msk /*!< DAC clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U)
+#define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */
+
+/******************* Bit definition for RCC_CCIPR register *******************/
+/*!< USART1 Clock source selection */
+#define RCC_CCIPR_USART1SEL_Pos (0U)
+#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
+#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk /*!< USART1SEL[1:0] bits */
+#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
+
+/*!< USART2 Clock source selection */
+#define RCC_CCIPR_USART2SEL_Pos (2U)
+#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */
+#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+/*!< LPUART1 Clock source selection */
+#define RCC_CCIPR_LPUART1SEL_Pos (10U)
+#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */
+#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */
+#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CCIPR_I2C1SEL_Pos (12U)
+#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */
+#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
+
+
+/*!< LPTIM1 Clock source selection */
+#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
+#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */
+#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+/*!< HSI48 Clock source selection */
+#define RCC_CCIPR_HSI48SEL_Pos (26U)
+#define RCC_CCIPR_HSI48SEL_Msk (0x1UL << RCC_CCIPR_HSI48SEL_Pos) /*!< 0x04000000 */
+#define RCC_CCIPR_HSI48SEL RCC_CCIPR_HSI48SEL_Msk /*!< HSI48 RC clock source selection bit for USB and RNG*/
+
+/* Legacy defines */
+#define RCC_CCIPR_HSI48MSEL RCC_CCIPR_HSI48SEL
+
+/******************* Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSEON_Pos (8U)
+#define RCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */
+#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_CSR_LSERDY_Pos (9U)
+#define RCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */
+#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP_Pos (10U)
+#define RCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */
+#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_CSR_LSEDRV_Pos (11U)
+#define RCC_CSR_LSEDRV_Msk (0x3UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */
+#define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_CSR_LSEDRV_0 (0x1UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */
+#define RCC_CSR_LSEDRV_1 (0x2UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */
+
+#define RCC_CSR_LSECSSON_Pos (13U)
+#define RCC_CSR_LSECSSON_Msk (0x1UL << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */
+#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */
+#define RCC_CSR_LSECSSD_Pos (14U)
+#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
+#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
+
+/*!< RTC congiguration */
+#define RCC_CSR_RTCSEL_Pos (16U)
+#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
+
+#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CSR_RTCSEL_LSE_Pos (16U)
+#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_LSI_Pos (17U)
+#define RCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */
+#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_HSE_Pos (16U)
+#define RCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */
+
+#define RCC_CSR_RTCEN_Pos (18U)
+#define RCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */
+#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_CSR_RTCRST_Pos (19U)
+#define RCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */
+#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */
+
+#define RCC_CSR_RMVF_Pos (23U)
+#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_FWRSTF_Pos (24U)
+#define RCC_CSR_FWRSTF_Msk (0x1UL << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk /*!< Mifare Firewall reset flag */
+#define RCC_CSR_OBLRSTF_Pos (25U)
+#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+/* Reference defines */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN_Pos (2U)
+#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
+#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos (3U)
+#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
+#define RNG_CR_IE RNG_CR_IE_Msk
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY_Pos (0U)
+#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
+#define RNG_SR_DRDY RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos (1U)
+#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
+#define RNG_SR_CECS RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos (2U)
+#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
+#define RNG_SR_SECS RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos (5U)
+#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
+#define RNG_SR_CEIS RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos (6U)
+#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
+#define RNG_SR_SEIS RNG_SR_SEIS_Msk
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER1_SUPPORT
+#define RTC_TAMPER2_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk /*!< */
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk /*!< */
+#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk /*!< */
+#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */
+#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */
+#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk /*!< */
+#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk /*!< */
+#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk /*!< */
+#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk /*!< */
+#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */
+#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk /*!< */
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk /*!< */
+#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk /*!< */
+#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk /*!< */
+#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk /*!< */
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */
+#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk /*!< */
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< */
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */
+#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */
+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */
+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */
+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */
+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */
+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */
+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */
+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */
+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */
+#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */
+#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */
+#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */
+#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */
+#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */
+#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */
+#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */
+#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */
+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */
+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */
+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */
+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */
+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */
+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */
+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */
+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */
+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */
+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CALR register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */
+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define RTC_CAL_CALP RTC_CALR_CALP
+#define RTC_CAL_CALW8 RTC_CALR_CALW8
+#define RTC_CAL_CALW16 RTC_CALR_CALW16
+#define RTC_CAL_CALM RTC_CALR_CALM
+#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
+
+/******************** Bits definition for RTC_TAMPCR register ****************/
+#define RTC_TAMPCR_TAMP2MF_Pos (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2IE_Pos (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1MF_Pos (18U)
+#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
+#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1IE_Pos (16U)
+#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */
+#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */
+#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */
+#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos (7U)
+#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */
+#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP2E_Pos (3U)
+#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */
+#define RTC_TAMPCR_TAMPIE_Pos (2U)
+#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
+#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP1E_Pos (0U)
+#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_OR register ****************/
+#define RTC_OR_OUT_RMP_Pos (1U)
+#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */
+#define RTC_OR_ALARMOUTTYPE_Pos (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */
+
+/* Legacy defines */
+#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk /*!< */
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER (0x00000005U) /*!< */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+#define SPI_I2S_SUPPORT /*!< I2S support */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
+#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR1_BOOT_MODE_Pos (8U)
+#define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
+#define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */
+#define SYSCFG_CFGR1_BOOT_MODE_0 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOT_MODE_1 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_FWDISEN_Pos (0U)
+#define SYSCFG_CFGR2_FWDISEN_Msk (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos (8U)
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR2_I2C_PB6_FMP SYSCFG_CFGR2_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos (9U)
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR2_I2C_PB7_FMP SYSCFG_CFGR2_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos (10U)
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
+#define SYSCFG_CFGR2_I2C_PB8_FMP SYSCFG_CFGR2_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos (11U)
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
+#define SYSCFG_CFGR2_I2C_PB9_FMP SYSCFG_CFGR2_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR2_I2C1_FMP_Pos (12U)
+#define SYSCFG_CFGR2_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR2_I2C1_FMP SYSCFG_CFGR2_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR2_I2C2_FMP_Pos (13U)
+#define SYSCFG_CFGR2_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
+#define SYSCFG_CFGR2_I2C2_FMP SYSCFG_CFGR2_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
+
+
+/***************** Bit definition for SYSCFG_CFGR3 register ****************/
+#define SYSCFG_CFGR3_EN_VREFINT_Pos (0U)
+#define SYSCFG_CFGR3_EN_VREFINT_Msk (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_EN_VREFINT SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
+#define SYSCFG_CFGR3_VREF_OUT_Pos (4U)
+#define SYSCFG_CFGR3_VREF_OUT_Msk (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
+#define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */
+#define SYSCFG_CFGR3_VREF_OUT_0 (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
+#define SYSCFG_CFGR3_VREF_OUT_1 (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U)
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U)
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U)
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
+#define SYSCFG_CFGR3_ENREF_HSI48_Pos (13U)
+#define SYSCFG_CFGR3_ENREF_HSI48_Msk (0x1UL << SYSCFG_CFGR3_ENREF_HSI48_Pos) /*!< 0x00002000 */
+#define SYSCFG_CFGR3_ENREF_HSI48 SYSCFG_CFGR3_ENREF_HSI48_Msk /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
+#define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U)
+#define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
+#define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
+#define SYSCFG_CFGR3_REF_LOCK_Pos (31U)
+#define SYSCFG_CFGR3_REF_LOCK_Msk (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
+#define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */
+
+/* Legacy defines */
+
+#define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
+#define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
+#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
+#define SYSCFG_CFGR3_ENREF_RC48MHz SYSCFG_CFGR3_ENREF_HSI48
+#define SYSCFG_CFGR3_REF_RC48MHz_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_REF_HSI48_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+
+/******************************************************************************/
+/* */
+/* Timers (TIM)*/
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
+#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
+ || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#else
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#endif
+
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFUL << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFUL << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM2_OR_ETR_RMP_Pos (0U)
+#define TIM2_OR_ETR_RMP_Msk (0x7UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000007 */
+#define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
+#define TIM2_OR_ETR_RMP_0 (0x1UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM2_OR_ETR_RMP_1 (0x2UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM2_OR_ETR_RMP_2 (0x4UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000004 */
+#define TIM2_OR_TI4_RMP_Pos (3U)
+#define TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000018 */
+#define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
+#define TIM2_OR_TI4_RMP_0 (0x1UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */
+#define TIM2_OR_TI4_RMP_1 (0x2UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000010 */
+
+#define TIM21_OR_ETR_RMP_Pos (0U)
+#define TIM21_OR_ETR_RMP_Msk (0x3UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
+#define TIM21_OR_ETR_RMP_0 (0x1UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM21_OR_ETR_RMP_1 (0x2UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM21_OR_TI1_RMP_Pos (2U)
+#define TIM21_OR_TI1_RMP_Msk (0x7UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x0000001C */
+#define TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
+#define TIM21_OR_TI1_RMP_0 (0x1UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM21_OR_TI1_RMP_1 (0x2UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+#define TIM21_OR_TI1_RMP_2 (0x4UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000010 */
+#define TIM21_OR_TI2_RMP_Pos (5U)
+#define TIM21_OR_TI2_RMP_Msk (0x1UL << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */
+#define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */
+
+#define TIM22_OR_ETR_RMP_Pos (0U)
+#define TIM22_OR_ETR_RMP_Msk (0x3UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM22_OR_ETR_RMP TIM22_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
+#define TIM22_OR_ETR_RMP_0 (0x1UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM22_OR_ETR_RMP_1 (0x2UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM22_OR_TI1_RMP_Pos (2U)
+#define TIM22_OR_TI1_RMP_Msk (0x3UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x0000000C */
+#define TIM22_OR_TI1_RMP TIM22_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
+#define TIM22_OR_TI1_RMP_0 (0x1UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM22_OR_TI1_RMP_1 (0x2UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+
+
+/******************************************************************************/
+/* */
+/* Touch Sensing Controller (TSC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TSC_CR register *********************/
+#define TSC_CR_TSCE_Pos (0U)
+#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
+#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
+#define TSC_CR_START_Pos (1U)
+#define TSC_CR_START_Msk (0x1UL << TSC_CR_START_Pos) /*!< 0x00000002 */
+#define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
+#define TSC_CR_AM_Pos (2U)
+#define TSC_CR_AM_Msk (0x1UL << TSC_CR_AM_Pos) /*!< 0x00000004 */
+#define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL_Pos (3U)
+#define TSC_CR_SYNCPOL_Msk (0x1UL << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
+#define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF_Pos (4U)
+#define TSC_CR_IODEF_Msk (0x1UL << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
+#define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
+
+#define TSC_CR_MCV_Pos (5U)
+#define TSC_CR_MCV_Msk (0x7UL << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
+#define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0 (0x1UL << TSC_CR_MCV_Pos) /*!< 0x00000020 */
+#define TSC_CR_MCV_1 (0x2UL << TSC_CR_MCV_Pos) /*!< 0x00000040 */
+#define TSC_CR_MCV_2 (0x4UL << TSC_CR_MCV_Pos) /*!< 0x00000080 */
+
+#define TSC_CR_PGPSC_Pos (12U)
+#define TSC_CR_PGPSC_Msk (0x7UL << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
+#define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0 (0x1UL << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
+#define TSC_CR_PGPSC_1 (0x2UL << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
+#define TSC_CR_PGPSC_2 (0x4UL << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
+
+#define TSC_CR_SSPSC_Pos (15U)
+#define TSC_CR_SSPSC_Msk (0x1UL << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
+#define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE_Pos (16U)
+#define TSC_CR_SSE_Msk (0x1UL << TSC_CR_SSE_Pos) /*!< 0x00010000 */
+#define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD_Pos (17U)
+#define TSC_CR_SSD_Msk (0x7FUL << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
+#define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0 (0x01UL << TSC_CR_SSD_Pos) /*!< 0x00020000 */
+#define TSC_CR_SSD_1 (0x02UL << TSC_CR_SSD_Pos) /*!< 0x00040000 */
+#define TSC_CR_SSD_2 (0x04UL << TSC_CR_SSD_Pos) /*!< 0x00080000 */
+#define TSC_CR_SSD_3 (0x08UL << TSC_CR_SSD_Pos) /*!< 0x00100000 */
+#define TSC_CR_SSD_4 (0x10UL << TSC_CR_SSD_Pos) /*!< 0x00200000 */
+#define TSC_CR_SSD_5 (0x20UL << TSC_CR_SSD_Pos) /*!< 0x00400000 */
+#define TSC_CR_SSD_6 (0x40UL << TSC_CR_SSD_Pos) /*!< 0x00800000 */
+
+#define TSC_CR_CTPL_Pos (24U)
+#define TSC_CR_CTPL_Msk (0xFUL << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
+#define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0 (0x1UL << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
+#define TSC_CR_CTPL_1 (0x2UL << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
+#define TSC_CR_CTPL_2 (0x4UL << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
+#define TSC_CR_CTPL_3 (0x8UL << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
+
+#define TSC_CR_CTPH_Pos (28U)
+#define TSC_CR_CTPH_Msk (0xFUL << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
+#define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0 (0x1UL << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
+#define TSC_CR_CTPH_1 (0x2UL << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
+#define TSC_CR_CTPH_2 (0x4UL << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
+#define TSC_CR_CTPH_3 (0x8UL << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for TSC_IER register ********************/
+#define TSC_IER_EOAIE_Pos (0U)
+#define TSC_IER_EOAIE_Msk (0x1UL << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
+#define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE_Pos (1U)
+#define TSC_IER_MCEIE_Msk (0x1UL << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
+#define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
+
+/******************* Bit definition for TSC_ICR register ********************/
+#define TSC_ICR_EOAIC_Pos (0U)
+#define TSC_ICR_EOAIC_Msk (0x1UL << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
+#define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC_Pos (1U)
+#define TSC_ICR_MCEIC_Msk (0x1UL << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
+#define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
+
+/******************* Bit definition for TSC_ISR register ********************/
+#define TSC_ISR_EOAF_Pos (0U)
+#define TSC_ISR_EOAF_Msk (0x1UL << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
+#define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
+#define TSC_ISR_MCEF_Pos (1U)
+#define TSC_ISR_MCEF_Msk (0x1UL << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
+#define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
+
+/******************* Bit definition for TSC_IOHCR register ******************/
+#define TSC_IOHCR_G1_IO1_Pos (0U)
+#define TSC_IOHCR_G1_IO1_Msk (0x1UL << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2_Pos (1U)
+#define TSC_IOHCR_G1_IO2_Msk (0x1UL << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3_Pos (2U)
+#define TSC_IOHCR_G1_IO3_Msk (0x1UL << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4_Pos (3U)
+#define TSC_IOHCR_G1_IO4_Msk (0x1UL << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1_Pos (4U)
+#define TSC_IOHCR_G2_IO1_Msk (0x1UL << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2_Pos (5U)
+#define TSC_IOHCR_G2_IO2_Msk (0x1UL << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3_Pos (6U)
+#define TSC_IOHCR_G2_IO3_Msk (0x1UL << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4_Pos (7U)
+#define TSC_IOHCR_G2_IO4_Msk (0x1UL << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1_Pos (8U)
+#define TSC_IOHCR_G3_IO1_Msk (0x1UL << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2_Pos (9U)
+#define TSC_IOHCR_G3_IO2_Msk (0x1UL << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3_Pos (10U)
+#define TSC_IOHCR_G3_IO3_Msk (0x1UL << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4_Pos (11U)
+#define TSC_IOHCR_G3_IO4_Msk (0x1UL << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1_Pos (12U)
+#define TSC_IOHCR_G4_IO1_Msk (0x1UL << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2_Pos (13U)
+#define TSC_IOHCR_G4_IO2_Msk (0x1UL << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3_Pos (14U)
+#define TSC_IOHCR_G4_IO3_Msk (0x1UL << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4_Pos (15U)
+#define TSC_IOHCR_G4_IO4_Msk (0x1UL << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1_Pos (16U)
+#define TSC_IOHCR_G5_IO1_Msk (0x1UL << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2_Pos (17U)
+#define TSC_IOHCR_G5_IO2_Msk (0x1UL << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3_Pos (18U)
+#define TSC_IOHCR_G5_IO3_Msk (0x1UL << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4_Pos (19U)
+#define TSC_IOHCR_G5_IO4_Msk (0x1UL << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1_Pos (20U)
+#define TSC_IOHCR_G6_IO1_Msk (0x1UL << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2_Pos (21U)
+#define TSC_IOHCR_G6_IO2_Msk (0x1UL << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3_Pos (22U)
+#define TSC_IOHCR_G6_IO3_Msk (0x1UL << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4_Pos (23U)
+#define TSC_IOHCR_G6_IO4_Msk (0x1UL << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1_Pos (24U)
+#define TSC_IOHCR_G7_IO1_Msk (0x1UL << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2_Pos (25U)
+#define TSC_IOHCR_G7_IO2_Msk (0x1UL << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3_Pos (26U)
+#define TSC_IOHCR_G7_IO3_Msk (0x1UL << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4_Pos (27U)
+#define TSC_IOHCR_G7_IO4_Msk (0x1UL << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1_Pos (28U)
+#define TSC_IOHCR_G8_IO1_Msk (0x1UL << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2_Pos (29U)
+#define TSC_IOHCR_G8_IO2_Msk (0x1UL << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3_Pos (30U)
+#define TSC_IOHCR_G8_IO3_Msk (0x1UL << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4_Pos (31U)
+#define TSC_IOHCR_G8_IO4_Msk (0x1UL << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+
+/******************* Bit definition for TSC_IOASCR register *****************/
+#define TSC_IOASCR_G1_IO1_Pos (0U)
+#define TSC_IOASCR_G1_IO1_Msk (0x1UL << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2_Pos (1U)
+#define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3_Pos (2U)
+#define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4_Pos (3U)
+#define TSC_IOASCR_G1_IO4_Msk (0x1UL << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1_Pos (4U)
+#define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2_Pos (5U)
+#define TSC_IOASCR_G2_IO2_Msk (0x1UL << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3_Pos (6U)
+#define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4_Pos (7U)
+#define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1_Pos (8U)
+#define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2_Pos (9U)
+#define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3_Pos (10U)
+#define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4_Pos (11U)
+#define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1_Pos (12U)
+#define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2_Pos (13U)
+#define TSC_IOASCR_G4_IO2_Msk (0x1UL << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3_Pos (14U)
+#define TSC_IOASCR_G4_IO3_Msk (0x1UL << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4_Pos (15U)
+#define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1_Pos (16U)
+#define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2_Pos (17U)
+#define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3_Pos (18U)
+#define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4_Pos (19U)
+#define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1_Pos (20U)
+#define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2_Pos (21U)
+#define TSC_IOASCR_G6_IO2_Msk (0x1UL << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3_Pos (22U)
+#define TSC_IOASCR_G6_IO3_Msk (0x1UL << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4_Pos (23U)
+#define TSC_IOASCR_G6_IO4_Msk (0x1UL << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1_Pos (24U)
+#define TSC_IOASCR_G7_IO1_Msk (0x1UL << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2_Pos (25U)
+#define TSC_IOASCR_G7_IO2_Msk (0x1UL << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3_Pos (26U)
+#define TSC_IOASCR_G7_IO3_Msk (0x1UL << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4_Pos (27U)
+#define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1_Pos (28U)
+#define TSC_IOASCR_G8_IO1_Msk (0x1UL << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2_Pos (29U)
+#define TSC_IOASCR_G8_IO2_Msk (0x1UL << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3_Pos (30U)
+#define TSC_IOASCR_G8_IO3_Msk (0x1UL << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4_Pos (31U)
+#define TSC_IOASCR_G8_IO4_Msk (0x1UL << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */
+
+/******************* Bit definition for TSC_IOSCR register ******************/
+#define TSC_IOSCR_G1_IO1_Pos (0U)
+#define TSC_IOSCR_G1_IO1_Msk (0x1UL << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2_Pos (1U)
+#define TSC_IOSCR_G1_IO2_Msk (0x1UL << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3_Pos (2U)
+#define TSC_IOSCR_G1_IO3_Msk (0x1UL << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4_Pos (3U)
+#define TSC_IOSCR_G1_IO4_Msk (0x1UL << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1_Pos (4U)
+#define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2_Pos (5U)
+#define TSC_IOSCR_G2_IO2_Msk (0x1UL << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3_Pos (6U)
+#define TSC_IOSCR_G2_IO3_Msk (0x1UL << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4_Pos (7U)
+#define TSC_IOSCR_G2_IO4_Msk (0x1UL << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1_Pos (8U)
+#define TSC_IOSCR_G3_IO1_Msk (0x1UL << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2_Pos (9U)
+#define TSC_IOSCR_G3_IO2_Msk (0x1UL << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3_Pos (10U)
+#define TSC_IOSCR_G3_IO3_Msk (0x1UL << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4_Pos (11U)
+#define TSC_IOSCR_G3_IO4_Msk (0x1UL << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1_Pos (12U)
+#define TSC_IOSCR_G4_IO1_Msk (0x1UL << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2_Pos (13U)
+#define TSC_IOSCR_G4_IO2_Msk (0x1UL << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3_Pos (14U)
+#define TSC_IOSCR_G4_IO3_Msk (0x1UL << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4_Pos (15U)
+#define TSC_IOSCR_G4_IO4_Msk (0x1UL << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1_Pos (16U)
+#define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2_Pos (17U)
+#define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3_Pos (18U)
+#define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4_Pos (19U)
+#define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1_Pos (20U)
+#define TSC_IOSCR_G6_IO1_Msk (0x1UL << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2_Pos (21U)
+#define TSC_IOSCR_G6_IO2_Msk (0x1UL << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3_Pos (22U)
+#define TSC_IOSCR_G6_IO3_Msk (0x1UL << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4_Pos (23U)
+#define TSC_IOSCR_G6_IO4_Msk (0x1UL << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1_Pos (24U)
+#define TSC_IOSCR_G7_IO1_Msk (0x1UL << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2_Pos (25U)
+#define TSC_IOSCR_G7_IO2_Msk (0x1UL << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3_Pos (26U)
+#define TSC_IOSCR_G7_IO3_Msk (0x1UL << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4_Pos (27U)
+#define TSC_IOSCR_G7_IO4_Msk (0x1UL << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1_Pos (28U)
+#define TSC_IOSCR_G8_IO1_Msk (0x1UL << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2_Pos (29U)
+#define TSC_IOSCR_G8_IO2_Msk (0x1UL << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3_Pos (30U)
+#define TSC_IOSCR_G8_IO3_Msk (0x1UL << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4_Pos (31U)
+#define TSC_IOSCR_G8_IO4_Msk (0x1UL << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */
+
+/******************* Bit definition for TSC_IOCCR register ******************/
+#define TSC_IOCCR_G1_IO1_Pos (0U)
+#define TSC_IOCCR_G1_IO1_Msk (0x1UL << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2_Pos (1U)
+#define TSC_IOCCR_G1_IO2_Msk (0x1UL << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3_Pos (2U)
+#define TSC_IOCCR_G1_IO3_Msk (0x1UL << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4_Pos (3U)
+#define TSC_IOCCR_G1_IO4_Msk (0x1UL << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1_Pos (4U)
+#define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2_Pos (5U)
+#define TSC_IOCCR_G2_IO2_Msk (0x1UL << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3_Pos (6U)
+#define TSC_IOCCR_G2_IO3_Msk (0x1UL << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4_Pos (7U)
+#define TSC_IOCCR_G2_IO4_Msk (0x1UL << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1_Pos (8U)
+#define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2_Pos (9U)
+#define TSC_IOCCR_G3_IO2_Msk (0x1UL << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3_Pos (10U)
+#define TSC_IOCCR_G3_IO3_Msk (0x1UL << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4_Pos (11U)
+#define TSC_IOCCR_G3_IO4_Msk (0x1UL << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1_Pos (12U)
+#define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2_Pos (13U)
+#define TSC_IOCCR_G4_IO2_Msk (0x1UL << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3_Pos (14U)
+#define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4_Pos (15U)
+#define TSC_IOCCR_G4_IO4_Msk (0x1UL << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1_Pos (16U)
+#define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2_Pos (17U)
+#define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3_Pos (18U)
+#define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4_Pos (19U)
+#define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1_Pos (20U)
+#define TSC_IOCCR_G6_IO1_Msk (0x1UL << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2_Pos (21U)
+#define TSC_IOCCR_G6_IO2_Msk (0x1UL << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3_Pos (22U)
+#define TSC_IOCCR_G6_IO3_Msk (0x1UL << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4_Pos (23U)
+#define TSC_IOCCR_G6_IO4_Msk (0x1UL << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1_Pos (24U)
+#define TSC_IOCCR_G7_IO1_Msk (0x1UL << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2_Pos (25U)
+#define TSC_IOCCR_G7_IO2_Msk (0x1UL << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3_Pos (26U)
+#define TSC_IOCCR_G7_IO3_Msk (0x1UL << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4_Pos (27U)
+#define TSC_IOCCR_G7_IO4_Msk (0x1UL << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1_Pos (28U)
+#define TSC_IOCCR_G8_IO1_Msk (0x1UL << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2_Pos (29U)
+#define TSC_IOCCR_G8_IO2_Msk (0x1UL << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3_Pos (30U)
+#define TSC_IOCCR_G8_IO3_Msk (0x1UL << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4_Pos (31U)
+#define TSC_IOCCR_G8_IO4_Msk (0x1UL << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */
+
+/******************* Bit definition for TSC_IOGCSR register *****************/
+#define TSC_IOGCSR_G1E_Pos (0U)
+#define TSC_IOGCSR_G1E_Msk (0x1UL << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
+#define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E_Pos (1U)
+#define TSC_IOGCSR_G2E_Msk (0x1UL << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
+#define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E_Pos (2U)
+#define TSC_IOGCSR_G3E_Msk (0x1UL << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
+#define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E_Pos (3U)
+#define TSC_IOGCSR_G4E_Msk (0x1UL << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
+#define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E_Pos (4U)
+#define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
+#define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E_Pos (5U)
+#define TSC_IOGCSR_G6E_Msk (0x1UL << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
+#define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E_Pos (6U)
+#define TSC_IOGCSR_G7E_Msk (0x1UL << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
+#define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E_Pos (7U)
+#define TSC_IOGCSR_G8E_Msk (0x1UL << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */
+#define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S_Pos (16U)
+#define TSC_IOGCSR_G1S_Msk (0x1UL << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
+#define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S_Pos (17U)
+#define TSC_IOGCSR_G2S_Msk (0x1UL << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
+#define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S_Pos (18U)
+#define TSC_IOGCSR_G3S_Msk (0x1UL << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
+#define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S_Pos (19U)
+#define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
+#define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S_Pos (20U)
+#define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
+#define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S_Pos (21U)
+#define TSC_IOGCSR_G6S_Msk (0x1UL << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
+#define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S_Pos (22U)
+#define TSC_IOGCSR_G7S_Msk (0x1UL << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
+#define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S_Pos (23U)
+#define TSC_IOGCSR_G8S_Msk (0x1UL << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */
+#define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */
+
+/******************* Bit definition for TSC_IOGXCR register *****************/
+#define TSC_IOGXCR_CNT_Pos (0U)
+#define TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
+#define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE_Pos (0U)
+#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+#define USART_CR1_UESM_Pos (1U)
+#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
+#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_M0_Pos (12U)
+#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
+#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos (13U)
+#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos (14U)
+#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos (16U)
+#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
+#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
+#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
+#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
+#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos (21U)
+#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
+#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
+#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
+#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
+#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos (26U)
+#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos (27U)
+#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos (28U)
+#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
+#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7_Pos (4U)
+#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos (15U)
+#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos (16U)
+#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos (17U)
+#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos (18U)
+#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos (19U)
+#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos (20U)
+#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos (21U)
+#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos (23U)
+#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos (24U)
+#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos (12U)
+#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos (13U)
+#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos (14U)
+#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos (15U)
+#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos (17U)
+#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos (20U)
+#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
+#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
+#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos (22U)
+#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
+#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
+#define USART_CR3_UCESM_Pos (23U)
+#define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
+#define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION_Pos (0U)
+#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos (4U)
+#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO_Pos (0U)
+#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos (24U)
+#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ_Pos (0U)
+#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
+#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos (1U)
+#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
+#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos (2U)
+#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
+#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos (3U)
+#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
+#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos (4U)
+#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
+#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE_Pos (0U)
+#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
+#define USART_ISR_FE_Pos (1U)
+#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
+#define USART_ISR_NE_Pos (2U)
+#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos (3U)
+#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos (4U)
+#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos (5U)
+#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos (6U)
+#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos (7U)
+#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
+#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos (8U)
+#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos (9U)
+#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos (10U)
+#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
+#define USART_ISR_RTOF_Pos (11U)
+#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos (12U)
+#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos (14U)
+#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos (15U)
+#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos (16U)
+#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
+#define USART_ISR_CMF_Pos (17U)
+#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos (18U)
+#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos (19U)
+#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos (20U)
+#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
+#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos (21U)
+#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos (22U)
+#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
+#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF_Pos (0U)
+#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos (1U)
+#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos (2U)
+#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */
+#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos (3U)
+#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos (4U)
+#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos (6U)
+#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF_Pos (8U)
+#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos (9U)
+#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos (11U)
+#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos (12U)
+#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos (17U)
+#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos (20U)
+#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
+#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
+
+/* Compatibility defines with other series */
+#define USART_ICR_NECF USART_ICR_NCF
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR_Pos (0U)
+#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR_Pos (0U)
+#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* USB Device General registers */
+/* */
+/******************************************************************************/
+#define USB_BASE (0x40005C00U) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR_Pos (13U)
+#define USB_PMAADDR_Msk (0x20003UL << USB_PMAADDR_Pos) /*!< 0x40006000 */
+#define USB_PMAADDR USB_PMAADDR_Msk /*!< USB_IP Packet Memory Area base address */
+
+#define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
+#define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
+#define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
+#define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
+#define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
+#define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
+#define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
+
+/**************************** ISTR interrupt events *************************/
+#define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
+#define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
+#define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
+#define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
+#define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
+#define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
+#define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
+#define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
+#define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
+
+#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
+#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
+#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
+#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
+#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
+#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
+#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
+#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
+#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
+/************************* CNTR control register bits definitions ***********/
+#define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
+#define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
+#define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
+#define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
+#define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
+#define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
+#define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
+#define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
+#define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
+#define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
+#define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
+#define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
+#define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
+#define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
+/************************* BCDR control register bits definitions ***********/
+#define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
+#define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
+#define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
+#define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
+#define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
+#define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
+#define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
+#define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
+#define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
+/*************************** LPM register bits definitions ******************/
+#define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
+#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
+#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
+/******************** FNR Frame Number Register bit definitions ************/
+#define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
+#define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
+#define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
+#define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
+#define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
+/******************** DADDR Device ADDRess bit definitions ****************/
+#define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */
+#define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */
+/****************************** Endpoint register *************************/
+#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
+#define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
+#define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
+#define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
+#define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
+#define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
+#define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
+#define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
+/* bit positions */
+#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
+#define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
+#define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
+#define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
+#define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+ /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
+#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+/******************************* COMP Instances *******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+ ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances *********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOH))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
+
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SMBUS Instances *****************************/
+#define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/************* LPTIM instances supporting the encoder mode feature ************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM6))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM21) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM22) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/******************* TIM Instances : output(s) OCXEC register *****************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** USART Instances : Auto Baud Rate detection ****************/
+
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/******************************* USB Instances *******************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32L0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32L0 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+
+#define LPUART1_IRQn RNG_LPUART1_IRQn
+#define AES_LPUART1_IRQn RNG_LPUART1_IRQn
+#define AES_RNG_LPUART1_IRQn RNG_LPUART1_IRQn
+#define TIM6_IRQn TIM6_DAC_IRQn
+#define RCC_IRQn RCC_CRS_IRQn
+#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
+#define ADC1_IRQn ADC1_COMP_IRQn
+
+/* Aliases for __IRQHandler */
+#define LPUART1_IRQHandler RNG_LPUART1_IRQHandler
+#define AES_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
+#define AES_RNG_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
+#define TIM6_IRQHandler TIM6_DAC_IRQHandler
+#define RCC_IRQHandler RCC_CRS_IRQHandler
+#define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
+#define ADC1_IRQHandler ADC1_COMP_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L052xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/CMSIS/device/stm32l053xx.h b/CMSIS/device/stm32l053xx.h
new file mode 100644
index 0000000..91f0f2e
--- /dev/null
+++ b/CMSIS/device/stm32l053xx.h
@@ -0,0 +1,7509 @@
+/**
+ ******************************************************************************
+ * @file stm32l053xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for stm32l053xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright(c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l053xx
+ * @{
+ */
+
+#ifndef __STM32L053xx_H
+#define __STM32L053xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 1U /*!< STM32L0xx provides an MPU */
+#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
+#define __NVIC_PRIO_BITS 2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief stm32l053xx Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+/*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
+
+/****** STM32L-0 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */
+ RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ TSC_IRQn = 8, /*!< TSC Interrupt */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
+ ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
+ LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 Interrupt */
+ TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
+ TIM21_IRQn = 20, /*!< TIM21 Interrupt */
+ TIM22_IRQn = 22, /*!< TIM22 Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */
+ I2C2_IRQn = 24, /*!< I2C2 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ SPI2_IRQn = 26, /*!< SPI2 Interrupt */
+ USART1_IRQn = 27, /*!< USART1 Interrupt */
+ USART2_IRQn = 28, /*!< USART2 Interrupt */
+ RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */
+ LCD_IRQn = 30, /*!< LCD Interrupt */
+ USB_IRQn = 31, /*!< USB global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0plus.h"
+#include "system_stm32l0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+ uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Comparator
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
+} COMP_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+
+/**
+* @brief CRC calculation unit
+*/
+
+typedef struct
+{
+__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+uint8_t RESERVED0; /*!< Reserved, 0x05 */
+uint16_t RESERVED1; /*!< Reserved, 0x06 */
+__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+uint32_t RESERVED2; /*!< Reserved, 0x0C */
+__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Clock Recovery System
+ */
+
+typedef struct
+{
+__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
+__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
+__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
+__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
+} CRS_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ uint32_t RESERVED0[6]; /*!< 0x14-0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ uint32_t RESERVED1; /*!< 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
+} DMA_Request_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
+ __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
+ __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
+ __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
+ __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
+ __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
+ __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
+ __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
+ __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
+ __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
+} OB_TypeDef;
+
+
+/**
+ * @brief General Purpose IO
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief LPTIMIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+} LPTIM_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+ * @brief Independent WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief LCD
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
+ __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
+ __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
+ __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
+} LCD_TypeDef;
+
+/**
+ * @brief MIFARE Firewall
+ */
+typedef struct
+{
+ __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
+ __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
+ __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
+ __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
+ __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
+ __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
+ __IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x18 */
+ __IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */
+ __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
+
+} FIREWALL_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
+ __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
+ __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
+ __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
+ __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
+ __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
+ __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
+ __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
+ __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
+ __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
+ __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
+} RCC_TypeDef;
+
+/**
+ * @brief Random numbers generator
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Touch Sensing Controller (TSC)
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
+ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
+ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
+ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
+ __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief Universal Serial Bus Full Speed Device
+ */
+typedef struct
+{
+ __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
+ __IO uint16_t RESERVED0; /*!< Reserved */
+ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
+ __IO uint16_t RESERVED1; /*!< Reserved */
+ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
+ __IO uint16_t RESERVED2; /*!< Reserved */
+ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
+ __IO uint16_t RESERVED3; /*!< Reserved */
+ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
+ __IO uint16_t RESERVED4; /*!< Reserved */
+ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
+ __IO uint16_t RESERVED5; /*!< Reserved */
+ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
+ __IO uint16_t RESERVED6; /*!< Reserved */
+ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
+ __IO uint16_t RESERVED7[17]; /*!< Reserved */
+ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
+ __IO uint16_t RESERVED8; /*!< Reserved */
+ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
+ __IO uint16_t RESERVED9; /*!< Reserved */
+ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
+ __IO uint16_t RESERVEDA; /*!< Reserved */
+ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
+ __IO uint16_t RESERVEDB; /*!< Reserved */
+ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
+ __IO uint16_t RESERVEDC; /*!< Reserved */
+ __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
+ __IO uint16_t RESERVEDD; /*!< Reserved */
+ __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
+ __IO uint16_t RESERVEDE; /*!< Reserved */
+} USB_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */
+
+#define DATA_EEPROM_BASE (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
+#define DATA_EEPROM_END (0x080807FFUL) /*!< DATA EEPROM end address in the alias region */
+#define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */
+#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8KBytes) */
+
+#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000UL)
+
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL)
+#define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL)
+#define LCD_BASE (APBPERIPH_BASE + 0x00002400UL)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
+#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
+#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800UL)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
+#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL)
+#define CRS_BASE (APBPERIPH_BASE + 0x00006C00UL)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
+#define DAC_BASE (APBPERIPH_BASE + 0x00007400UL)
+#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL)
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
+#define COMP1_BASE (APBPERIPH_BASE + 0x00010018UL)
+#define COMP2_BASE (APBPERIPH_BASE + 0x0001001CUL)
+#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL)
+#define TIM21_BASE (APBPERIPH_BASE + 0x00010800UL)
+#define TIM22_BASE (APBPERIPH_BASE + 0x00011400UL)
+#define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00UL)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708UL)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
+#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
+#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL)
+
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
+#define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */
+#define FLASHSIZE_BASE (0x1FF8007CUL) /*!< FLASH Size register base address */
+#define UID_BASE (0x1FF80050UL) /*!< Unique device ID register base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
+#define TSC_BASE (AHBPERIPH_BASE + 0x00004000UL)
+#define RNG_BASE (AHBPERIPH_BASE + 0x00005000UL)
+
+#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL)
+#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL)
+#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL)
+#define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00UL)
+#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00UL)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define CRS ((CRS_TypeDef *) CRS_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define LCD ((LCD_TypeDef *) LCD_BASE)
+
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
+#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
+#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
+/* Legacy defines */
+#define ADC ADC1_COMMON
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define TSC ((TSC_TypeDef *) TSC_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+
+#define USB ((USB_TypeDef *) USB_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_EOCAL_Pos (11U)
+#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
+#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
+#define ADC_ISR_AWD_Pos (7U)
+#define ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
+#define ADC_ISR_EOSEQ_Pos (3U)
+#define ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_EOCALIE_Pos (11U)
+#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
+#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
+#define ADC_IER_AWDIE_Pos (7U)
+#define ADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE_Pos (3U)
+#define ADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH_Pos (26U)
+#define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
+#define ADC_CFGR1_AWDEN_Pos (23U)
+#define ADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL_Pos (22U)
+#define ADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN_Pos (16U)
+#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF_Pos (15U)
+#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
+#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT_Pos (14U)
+#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
+#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT_Pos (13U)
+#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD_Pos (12U)
+#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN_Pos (10U)
+#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
+#define ADC_CFGR1_EXTSEL_Pos (6U)
+#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
+#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
+#define ADC_CFGR1_ALIGN_Pos (5U)
+#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
+#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
+#define ADC_CFGR1_RES_Pos (3U)
+#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
+#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
+#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
+#define ADC_CFGR1_SCANDIR_Pos (2U)
+#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG_Pos (1U)
+#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
+#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN_Pos (0U)
+#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
+#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_TOVS_Pos (9U)
+#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
+#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+#define ADC_CFGR2_OVSR_Pos (2U)
+#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
+#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+#define ADC_CFGR2_OVSE_Pos (0U)
+#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
+#define ADC_CFGR2_CKMODE_Pos (30U)
+#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
+#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
+#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
+#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
+
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP_Pos (0U)
+#define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
+#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
+#define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
+#define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define ADC_SMPR_SMPR ADC_SMPR_SMP
+#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
+#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
+#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT_Pos (16U)
+#define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
+#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
+#define ADC_TR_LT_Pos (0U)
+#define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL_Pos (0U)
+#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
+#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
+#define ADC_CHSELR_CHSEL18_Pos (18U)
+#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17_Pos (17U)
+#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
+#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL16_Pos (16U)
+#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */
+#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< Channel 16 selection */
+#define ADC_CHSELR_CHSEL15_Pos (15U)
+#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
+#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14_Pos (14U)
+#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
+#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13_Pos (13U)
+#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
+#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12_Pos (12U)
+#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
+#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11_Pos (11U)
+#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
+#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10_Pos (10U)
+#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
+#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9_Pos (9U)
+#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
+#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8_Pos (8U)
+#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
+#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7_Pos (7U)
+#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
+#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6_Pos (6U)
+#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
+#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5_Pos (5U)
+#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
+#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4_Pos (4U)
+#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
+#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3_Pos (3U)
+#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
+#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2_Pos (2U)
+#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
+#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1_Pos (1U)
+#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
+#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0_Pos (0U)
+#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
+#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_CALFACT_Pos (0U)
+#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_LFMEN_Pos (25U)
+#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
+#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
+#define ADC_CCR_VLCDEN_Pos (24U)
+#define ADC_CCR_VLCDEN_Msk (0x1UL << ADC_CCR_VLCDEN_Pos) /*!< 0x01000000 */
+#define ADC_CCR_VLCDEN ADC_CCR_VLCDEN_Msk /*!< Voltage LCD enable */
+#define ADC_CCR_TSEN_Pos (23U)
+#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+/************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN_Pos (0U)
+#define COMP_CSR_COMP1EN_Msk (0x1UL << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
+#define COMP_CSR_COMP1INNSEL_Pos (4U)
+#define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
+#define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP1WM_Pos (8U)
+#define COMP_CSR_COMP1WM_Msk (0x1UL << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */
+#define COMP_CSR_COMP1LPTIM1IN1_Pos (12U)
+#define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP1POLARITY_Pos (15U)
+#define COMP_CSR_COMP1POLARITY_Msk (0x1UL << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1VALUE_Pos (30U)
+#define COMP_CSR_COMP1VALUE_Msk (0x1UL << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK_Pos (31U)
+#define COMP_CSR_COMP1LOCK_Msk (0x1UL << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN_Pos (0U)
+#define COMP_CSR_COMP2EN_Msk (0x1UL << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
+#define COMP_CSR_COMP2SPEED_Pos (3U)
+#define COMP_CSR_COMP2SPEED_Msk (0x1UL << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */
+#define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */
+#define COMP_CSR_COMP2INNSEL_Pos (4U)
+#define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */
+#define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
+#define COMP_CSR_COMP2INPSEL_Pos (8U)
+#define COMP_CSR_COMP2INPSEL_Msk (0x7UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */
+#define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2INPSEL_0 (0x1UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP2INPSEL_1 (0x2UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */
+#define COMP_CSR_COMP2INPSEL_2 (0x4UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */
+#define COMP_CSR_COMP2LPTIM1IN2_Pos (12U)
+#define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */
+#define COMP_CSR_COMP2LPTIM1IN1_Pos (13U)
+#define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */
+#define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP2POLARITY_Pos (15U)
+#define COMP_CSR_COMP2POLARITY_Msk (0x1UL << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2VALUE_Pos (30U)
+#define COMP_CSR_COMP2VALUE_Msk (0x1UL << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK_Pos (31U)
+#define COMP_CSR_COMP2LOCK_Msk (0x1UL << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
+
+/********************** Bit definition for COMP_CSR register common ****************/
+#define COMP_CSR_COMPxEN_Pos (0U)
+#define COMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
+#define COMP_CSR_COMPxPOLARITY_Pos (15U)
+#define COMP_CSR_COMPxPOLARITY_Msk (0x1UL << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */
+#define COMP_CSR_COMPxOUTVALUE_Pos (30U)
+#define COMP_CSR_COMPxOUTVALUE_Msk (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK_Pos (31U)
+#define COMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
+
+/* Reference defines */
+#define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR (0xFFU) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos (3U)
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos (5U)
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos (7U)
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT_Pos (0U)
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL_Pos (0U)
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* CRS Clock Recovery System */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRS_CR register *********************/
+#define CRS_CR_SYNCOKIE_Pos (0U)
+#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
+#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /* SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE_Pos (1U)
+#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
+#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /* SYNC warning interrupt enable */
+#define CRS_CR_ERRIE_Pos (2U)
+#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
+#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /* SYNC error interrupt enable */
+#define CRS_CR_ESYNCIE_Pos (3U)
+#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
+#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /* Expected SYNC(ESYNCF) interrupt Enable*/
+#define CRS_CR_CEN_Pos (5U)
+#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
+#define CRS_CR_CEN CRS_CR_CEN_Msk /* Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN_Pos (6U)
+#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
+#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /* Automatic trimming enable */
+#define CRS_CR_SWSYNC_Pos (7U)
+#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
+#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /* A Software SYNC event is generated */
+#define CRS_CR_TRIM_Pos (8U)
+#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
+#define CRS_CR_TRIM CRS_CR_TRIM_Msk /* HSI48 oscillator smooth trimming */
+
+/******************* Bit definition for CRS_CFGR register *********************/
+#define CRS_CFGR_RELOAD_Pos (0U)
+#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
+#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /* Counter reload value */
+#define CRS_CFGR_FELIM_Pos (16U)
+#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
+#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /* Frequency error limit */
+
+#define CRS_CFGR_SYNCDIV_Pos (24U)
+#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
+#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /* SYNC divider */
+#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
+#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
+#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
+
+#define CRS_CFGR_SYNCSRC_Pos (28U)
+#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
+#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /* SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
+#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
+
+#define CRS_CFGR_SYNCPOL_Pos (31U)
+#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
+#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /* SYNC polarity selection */
+
+/******************* Bit definition for CRS_ISR register *********************/
+#define CRS_ISR_SYNCOKF_Pos (0U)
+#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
+#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /* SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF_Pos (1U)
+#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
+#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /* SYNC warning */
+#define CRS_ISR_ERRF_Pos (2U)
+#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
+#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /* SYNC error flag */
+#define CRS_ISR_ESYNCF_Pos (3U)
+#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
+#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /* Expected SYNC flag */
+#define CRS_ISR_SYNCERR_Pos (8U)
+#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
+#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /* SYNC error */
+#define CRS_ISR_SYNCMISS_Pos (9U)
+#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
+#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /* SYNC missed */
+#define CRS_ISR_TRIMOVF_Pos (10U)
+#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
+#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /* Trimming overflow or underflow */
+#define CRS_ISR_FEDIR_Pos (15U)
+#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
+#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /* Frequency error direction */
+#define CRS_ISR_FECAP_Pos (16U)
+#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
+#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /* Frequency error capture */
+
+/******************* Bit definition for CRS_ICR register *********************/
+#define CRS_ICR_SYNCOKC_Pos (0U)
+#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
+#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /* SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC_Pos (1U)
+#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
+#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /* SYNC warning clear flag */
+#define CRS_ICR_ERRC_Pos (2U)
+#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
+#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /* Error clear flag */
+#define CRS_ICR_ESYNCC_Pos (3U)
+#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
+#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /* Expected SYNC clear flag */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter (DAC) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos (1U)
+#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos (2U)
+#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (3U)
+#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos (13U)
+#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun interrupt enable */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1_Pos (13U)
+#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_Pos (0U)
+#define DBGMCU_CR_DBG_Msk (0x7UL << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
+#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+
+/******************* Bit definition for DMA_CSELR register *******************/
+#define DMA_CSELR_C1S_Pos (0U)
+#define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
+#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos (4U)
+#define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
+#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos (8U)
+#define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
+#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos (12U)
+#define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
+#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos (16U)
+#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
+#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S_Pos (20U)
+#define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
+#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S_Pos (24U)
+#define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
+#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_IM0_Pos (0U)
+#define EXTI_IMR_IM0_Msk (0x1UL << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_IM1_Pos (1U)
+#define EXTI_IMR_IM1_Msk (0x1UL << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_IM2_Pos (2U)
+#define EXTI_IMR_IM2_Msk (0x1UL << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_IM3_Pos (3U)
+#define EXTI_IMR_IM3_Msk (0x1UL << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_IM4_Pos (4U)
+#define EXTI_IMR_IM4_Msk (0x1UL << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_IM5_Pos (5U)
+#define EXTI_IMR_IM5_Msk (0x1UL << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_IM6_Pos (6U)
+#define EXTI_IMR_IM6_Msk (0x1UL << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_IM7_Pos (7U)
+#define EXTI_IMR_IM7_Msk (0x1UL << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_IM8_Pos (8U)
+#define EXTI_IMR_IM8_Msk (0x1UL << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_IM9_Pos (9U)
+#define EXTI_IMR_IM9_Msk (0x1UL << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_IM10_Pos (10U)
+#define EXTI_IMR_IM10_Msk (0x1UL << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_IM11_Pos (11U)
+#define EXTI_IMR_IM11_Msk (0x1UL << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_IM12_Pos (12U)
+#define EXTI_IMR_IM12_Msk (0x1UL << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_IM13_Pos (13U)
+#define EXTI_IMR_IM13_Msk (0x1UL << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_IM14_Pos (14U)
+#define EXTI_IMR_IM14_Msk (0x1UL << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_IM15_Pos (15U)
+#define EXTI_IMR_IM15_Msk (0x1UL << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_IM16_Pos (16U)
+#define EXTI_IMR_IM16_Msk (0x1UL << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_IM17_Pos (17U)
+#define EXTI_IMR_IM17_Msk (0x1UL << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_IM18_Pos (18U)
+#define EXTI_IMR_IM18_Msk (0x1UL << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_IM19_Pos (19U)
+#define EXTI_IMR_IM19_Msk (0x1UL << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_IM20_Pos (20U)
+#define EXTI_IMR_IM20_Msk (0x1UL << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_IM21_Pos (21U)
+#define EXTI_IMR_IM21_Msk (0x1UL << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_IM22_Pos (22U)
+#define EXTI_IMR_IM22_Msk (0x1UL << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_IM23_Pos (23U)
+#define EXTI_IMR_IM23_Msk (0x1UL << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
+#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_IM25_Pos (25U)
+#define EXTI_IMR_IM25_Msk (0x1UL << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */
+#define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_IM26_Pos (26U)
+#define EXTI_IMR_IM26_Msk (0x1UL << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
+#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_IM28_Pos (28U)
+#define EXTI_IMR_IM28_Msk (0x1UL << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
+#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_IM29_Pos (29U)
+#define EXTI_IMR_IM29_Msk (0x1UL << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
+#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
+
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x36FFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x36FFFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_EM0_Pos (0U)
+#define EXTI_EMR_EM0_Msk (0x1UL << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_EM1_Pos (1U)
+#define EXTI_EMR_EM1_Msk (0x1UL << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_EM2_Pos (2U)
+#define EXTI_EMR_EM2_Msk (0x1UL << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_EM3_Pos (3U)
+#define EXTI_EMR_EM3_Msk (0x1UL << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_EM4_Pos (4U)
+#define EXTI_EMR_EM4_Msk (0x1UL << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_EM5_Pos (5U)
+#define EXTI_EMR_EM5_Msk (0x1UL << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_EM6_Pos (6U)
+#define EXTI_EMR_EM6_Msk (0x1UL << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_EM7_Pos (7U)
+#define EXTI_EMR_EM7_Msk (0x1UL << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_EM8_Pos (8U)
+#define EXTI_EMR_EM8_Msk (0x1UL << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_EM9_Pos (9U)
+#define EXTI_EMR_EM9_Msk (0x1UL << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_EM10_Pos (10U)
+#define EXTI_EMR_EM10_Msk (0x1UL << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_EM11_Pos (11U)
+#define EXTI_EMR_EM11_Msk (0x1UL << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_EM12_Pos (12U)
+#define EXTI_EMR_EM12_Msk (0x1UL << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_EM13_Pos (13U)
+#define EXTI_EMR_EM13_Msk (0x1UL << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_EM14_Pos (14U)
+#define EXTI_EMR_EM14_Msk (0x1UL << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_EM15_Pos (15U)
+#define EXTI_EMR_EM15_Msk (0x1UL << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_EM16_Pos (16U)
+#define EXTI_EMR_EM16_Msk (0x1UL << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_EM17_Pos (17U)
+#define EXTI_EMR_EM17_Msk (0x1UL << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_EM18_Pos (18U)
+#define EXTI_EMR_EM18_Msk (0x1UL << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_EM19_Pos (19U)
+#define EXTI_EMR_EM19_Msk (0x1UL << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_EM20_Pos (20U)
+#define EXTI_EMR_EM20_Msk (0x1UL << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_EM21_Pos (21U)
+#define EXTI_EMR_EM21_Msk (0x1UL << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_EM22_Pos (22U)
+#define EXTI_EMR_EM22_Msk (0x1UL << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */
+#define EXTI_EMR_EM23_Pos (23U)
+#define EXTI_EMR_EM23_Msk (0x1UL << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
+#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
+#define EXTI_EMR_EM25_Pos (25U)
+#define EXTI_EMR_EM25_Msk (0x1UL << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */
+#define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */
+#define EXTI_EMR_EM26_Pos (26U)
+#define EXTI_EMR_EM26_Msk (0x1UL << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
+#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
+#define EXTI_EMR_EM28_Pos (28U)
+#define EXTI_EMR_EM28_Msk (0x1UL << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
+#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
+#define EXTI_EMR_EM29_Pos (29U)
+#define EXTI_EMR_EM29_Msk (0x1UL << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
+#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_RT0_Pos (0U)
+#define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_RT1_Pos (1U)
+#define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_RT2_Pos (2U)
+#define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_RT3_Pos (3U)
+#define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_RT4_Pos (4U)
+#define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_RT5_Pos (5U)
+#define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_RT6_Pos (6U)
+#define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_RT7_Pos (7U)
+#define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_RT8_Pos (8U)
+#define EXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_RT9_Pos (9U)
+#define EXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_RT10_Pos (10U)
+#define EXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_RT11_Pos (11U)
+#define EXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_RT12_Pos (12U)
+#define EXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_RT13_Pos (13U)
+#define EXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_RT14_Pos (14U)
+#define EXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_RT15_Pos (15U)
+#define EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_RT16_Pos (16U)
+#define EXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_RT17_Pos (17U)
+#define EXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_RT19_Pos (19U)
+#define EXTI_RTSR_RT19_Msk (0x1UL << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_RT20_Pos (20U)
+#define EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_RT21_Pos (21U)
+#define EXTI_RTSR_RT21_Msk (0x1UL << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_RT22_Pos (22U)
+#define EXTI_RTSR_RT22_Msk (0x1UL << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
+#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
+#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
+#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
+#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
+#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
+#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
+#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
+#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
+#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
+#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
+#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
+#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
+#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
+#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
+#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
+#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
+#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
+#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
+#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
+#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
+#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_FT0_Pos (0U)
+#define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_FT1_Pos (1U)
+#define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_FT2_Pos (2U)
+#define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_FT3_Pos (3U)
+#define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_FT4_Pos (4U)
+#define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_FT5_Pos (5U)
+#define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_FT6_Pos (6U)
+#define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_FT7_Pos (7U)
+#define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_FT8_Pos (8U)
+#define EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_FT9_Pos (9U)
+#define EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_FT10_Pos (10U)
+#define EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_FT11_Pos (11U)
+#define EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_FT12_Pos (12U)
+#define EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_FT13_Pos (13U)
+#define EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_FT14_Pos (14U)
+#define EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_FT15_Pos (15U)
+#define EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_FT16_Pos (16U)
+#define EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_FT17_Pos (17U)
+#define EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_FT19_Pos (19U)
+#define EXTI_FTSR_FT19_Msk (0x1UL << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_FT20_Pos (20U)
+#define EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_FT21_Pos (21U)
+#define EXTI_FTSR_FT21_Msk (0x1UL << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_FT22_Pos (22U)
+#define EXTI_FTSR_FT22_Msk (0x1UL << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
+#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
+#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
+#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
+#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
+#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
+#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
+#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
+#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
+#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
+#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
+#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
+#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
+#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
+#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
+#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
+#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
+#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
+#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
+#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
+#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
+#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWI0_Pos (0U)
+#define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWI1_Pos (1U)
+#define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWI2_Pos (2U)
+#define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWI3_Pos (3U)
+#define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWI4_Pos (4U)
+#define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWI5_Pos (5U)
+#define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWI6_Pos (6U)
+#define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWI7_Pos (7U)
+#define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWI8_Pos (8U)
+#define EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWI9_Pos (9U)
+#define EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWI10_Pos (10U)
+#define EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWI11_Pos (11U)
+#define EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWI12_Pos (12U)
+#define EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWI13_Pos (13U)
+#define EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWI14_Pos (14U)
+#define EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWI15_Pos (15U)
+#define EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWI16_Pos (16U)
+#define EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWI17_Pos (17U)
+#define EXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWI19_Pos (19U)
+#define EXTI_SWIER_SWI19_Msk (0x1UL << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWI20_Pos (20U)
+#define EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWI21_Pos (21U)
+#define EXTI_SWIER_SWI21_Msk (0x1UL << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWI22_Pos (22U)
+#define EXTI_SWIER_SWI22_Msk (0x1UL << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
+
+/* Legacy defines */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PIF0_Pos (0U)
+#define EXTI_PR_PIF0_Msk (0x1UL << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
+#define EXTI_PR_PIF1_Pos (1U)
+#define EXTI_PR_PIF1_Msk (0x1UL << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
+#define EXTI_PR_PIF2_Pos (2U)
+#define EXTI_PR_PIF2_Msk (0x1UL << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
+#define EXTI_PR_PIF3_Pos (3U)
+#define EXTI_PR_PIF3_Msk (0x1UL << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
+#define EXTI_PR_PIF4_Pos (4U)
+#define EXTI_PR_PIF4_Msk (0x1UL << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
+#define EXTI_PR_PIF5_Pos (5U)
+#define EXTI_PR_PIF5_Msk (0x1UL << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
+#define EXTI_PR_PIF6_Pos (6U)
+#define EXTI_PR_PIF6_Msk (0x1UL << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
+#define EXTI_PR_PIF7_Pos (7U)
+#define EXTI_PR_PIF7_Msk (0x1UL << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
+#define EXTI_PR_PIF8_Pos (8U)
+#define EXTI_PR_PIF8_Msk (0x1UL << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
+#define EXTI_PR_PIF9_Pos (9U)
+#define EXTI_PR_PIF9_Msk (0x1UL << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
+#define EXTI_PR_PIF10_Pos (10U)
+#define EXTI_PR_PIF10_Msk (0x1UL << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
+#define EXTI_PR_PIF11_Pos (11U)
+#define EXTI_PR_PIF11_Msk (0x1UL << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
+#define EXTI_PR_PIF12_Pos (12U)
+#define EXTI_PR_PIF12_Msk (0x1UL << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
+#define EXTI_PR_PIF13_Pos (13U)
+#define EXTI_PR_PIF13_Msk (0x1UL << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
+#define EXTI_PR_PIF14_Pos (14U)
+#define EXTI_PR_PIF14_Msk (0x1UL << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
+#define EXTI_PR_PIF15_Pos (15U)
+#define EXTI_PR_PIF15_Msk (0x1UL << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
+#define EXTI_PR_PIF16_Pos (16U)
+#define EXTI_PR_PIF16_Msk (0x1UL << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
+#define EXTI_PR_PIF17_Pos (17U)
+#define EXTI_PR_PIF17_Msk (0x1UL << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
+#define EXTI_PR_PIF19_Pos (19U)
+#define EXTI_PR_PIF19_Msk (0x1UL << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
+#define EXTI_PR_PIF20_Pos (20U)
+#define EXTI_PR_PIF20_Msk (0x1UL << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
+#define EXTI_PR_PIF21_Pos (21U)
+#define EXTI_PR_PIF21_Msk (0x1UL << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
+#define EXTI_PR_PIF22_Pos (22U)
+#define EXTI_PR_PIF22_Msk (0x1UL << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
+
+/* Legacy defines */
+#define EXTI_PR_PR0 EXTI_PR_PIF0
+#define EXTI_PR_PR1 EXTI_PR_PIF1
+#define EXTI_PR_PR2 EXTI_PR_PIF2
+#define EXTI_PR_PR3 EXTI_PR_PIF3
+#define EXTI_PR_PR4 EXTI_PR_PIF4
+#define EXTI_PR_PR5 EXTI_PR_PIF5
+#define EXTI_PR_PR6 EXTI_PR_PIF6
+#define EXTI_PR_PR7 EXTI_PR_PIF7
+#define EXTI_PR_PR8 EXTI_PR_PIF8
+#define EXTI_PR_PR9 EXTI_PR_PIF9
+#define EXTI_PR_PR10 EXTI_PR_PIF10
+#define EXTI_PR_PR11 EXTI_PR_PIF11
+#define EXTI_PR_PR12 EXTI_PR_PIF12
+#define EXTI_PR_PR13 EXTI_PR_PIF13
+#define EXTI_PR_PR14 EXTI_PR_PIF14
+#define EXTI_PR_PR15 EXTI_PR_PIF15
+#define EXTI_PR_PR16 EXTI_PR_PIF16
+#define EXTI_PR_PR17 EXTI_PR_PIF17
+#define EXTI_PR_PR19 EXTI_PR_PIF19
+#define EXTI_PR_PR20 EXTI_PR_PIF20
+#define EXTI_PR_PR21 EXTI_PR_PIF21
+#define EXTI_PR_PR22 EXTI_PR_PIF22
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
+#define FLASH_ACR_PRFTEN_Pos (1U)
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_SLEEP_PD_Pos (3U)
+#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD_Pos (4U)
+#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
+#define FLASH_ACR_DISAB_BUF_Pos (5U)
+#define FLASH_ACR_DISAB_BUF_Msk (0x1UL << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
+#define FLASH_ACR_PRE_READ_Pos (6U)
+#define FLASH_ACR_PRE_READ_Msk (0x1UL << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
+#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
+
+/******************* Bit definition for FLASH_PECR register ******************/
+#define FLASH_PECR_PELOCK_Pos (0U)
+#define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
+#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK_Pos (1U)
+#define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
+#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK_Pos (2U)
+#define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
+#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG_Pos (3U)
+#define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
+#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
+#define FLASH_PECR_DATA_Pos (4U)
+#define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
+#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
+#define FLASH_PECR_FIX_Pos (8U)
+#define FLASH_PECR_FIX_Msk (0x1UL << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
+#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE_Pos (9U)
+#define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
+#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
+#define FLASH_PECR_FPRG_Pos (10U)
+#define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
+#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_EOPIE_Pos (16U)
+#define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
+#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
+#define FLASH_PECR_ERRIE_Pos (17U)
+#define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
+#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
+#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
+#define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
+#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
+#define FLASH_PECR_HALF_ARRAY_Pos (19U)
+#define FLASH_PECR_HALF_ARRAY_Msk (0x1UL << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
+#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
+
+/****************** Bit definition for FLASH_PDKEYR register ******************/
+#define FLASH_PDKEYR_PDKEYR_Pos (0U)
+#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PEKEYR register ******************/
+#define FLASH_PEKEYR_PEKEYR_Pos (0U)
+#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PRGKEYR register ******************/
+#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
+#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
+
+/****************** Bit definition for FLASH_OPTKEYR register ******************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_EOP_Pos (1U)
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
+#define FLASH_SR_HVOFF_Pos (2U)
+#define FLASH_SR_HVOFF_Msk (0x1UL << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
+#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
+#define FLASH_SR_READY_Pos (3U)
+#define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */
+#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR_Pos (8U)
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
+#define FLASH_SR_PGAERR_Pos (9U)
+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR_Pos (10U)
+#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
+#define FLASH_SR_OPTVERR_Pos (11U)
+#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
+#define FLASH_SR_RDERR_Pos (13U)
+#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
+#define FLASH_SR_NOTZEROERR_Pos (16U)
+#define FLASH_SR_NOTZEROERR_Msk (0x1UL << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
+#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
+#define FLASH_SR_FWWERR_Pos (17U)
+#define FLASH_SR_FWWERR_Msk (0x1UL << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
+#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
+
+/* Legacy defines */
+#define FLASH_SR_FWWER FLASH_SR_FWWERR
+#define FLASH_SR_ENHV FLASH_SR_HVOFF
+#define FLASH_SR_ENDHV FLASH_SR_HVOFF
+
+/****************** Bit definition for FLASH_OPTR register *******************/
+#define FLASH_OPTR_RDPROT_Pos (0U)
+#define FLASH_OPTR_RDPROT_Msk (0xFFUL << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
+#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
+#define FLASH_OPTR_WPRMOD_Pos (8U)
+#define FLASH_OPTR_WPRMOD_Msk (0x1UL << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
+#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
+#define FLASH_OPTR_BOR_LEV_Pos (16U)
+#define FLASH_OPTR_BOR_LEV_Msk (0xFUL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
+#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OPTR_IWDG_SW_Pos (20U)
+#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
+#define FLASH_OPTR_nRST_STOP_Pos (21U)
+#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OPTR_nRST_STDBY_Pos (22U)
+#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OPTR_USER_Pos (20U)
+#define FLASH_OPTR_USER_Msk (0x7UL << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
+#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OPTR_BOOT1_Pos (31U)
+#define FLASH_OPTR_BOOT1_Msk (0x1UL << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
+#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 (0x00000001U)
+#define GPIO_OTYPER_OT_1 (0x00000002U)
+#define GPIO_OTYPER_OT_2 (0x00000004U)
+#define GPIO_OTYPER_OT_3 (0x00000008U)
+#define GPIO_OTYPER_OT_4 (0x00000010U)
+#define GPIO_OTYPER_OT_5 (0x00000020U)
+#define GPIO_OTYPER_OT_6 (0x00000040U)
+#define GPIO_OTYPER_OT_7 (0x00000080U)
+#define GPIO_OTYPER_OT_8 (0x00000100U)
+#define GPIO_OTYPER_OT_9 (0x00000200U)
+#define GPIO_OTYPER_OT_10 (0x00000400U)
+#define GPIO_OTYPER_OT_11 (0x00000800U)
+#define GPIO_OTYPER_OT_12 (0x00001000U)
+#define GPIO_OTYPER_OT_13 (0x00002000U)
+#define GPIO_OTYPER_OT_14 (0x00004000U)
+#define GPIO_OTYPER_OT_15 (0x00008000U)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDER_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
+#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDER_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
+#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDER_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
+#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDER_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
+#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDER_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
+#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDER_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
+#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDER_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
+#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDER_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
+#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDER_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
+#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDER_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
+#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDER_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
+#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDER_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
+#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDER_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
+#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDER_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
+#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDER_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
+#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDER_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
+#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 (0x00000001U)
+#define GPIO_BSRR_BS_1 (0x00000002U)
+#define GPIO_BSRR_BS_2 (0x00000004U)
+#define GPIO_BSRR_BS_3 (0x00000008U)
+#define GPIO_BSRR_BS_4 (0x00000010U)
+#define GPIO_BSRR_BS_5 (0x00000020U)
+#define GPIO_BSRR_BS_6 (0x00000040U)
+#define GPIO_BSRR_BS_7 (0x00000080U)
+#define GPIO_BSRR_BS_8 (0x00000100U)
+#define GPIO_BSRR_BS_9 (0x00000200U)
+#define GPIO_BSRR_BS_10 (0x00000400U)
+#define GPIO_BSRR_BS_11 (0x00000800U)
+#define GPIO_BSRR_BS_12 (0x00001000U)
+#define GPIO_BSRR_BS_13 (0x00002000U)
+#define GPIO_BSRR_BS_14 (0x00004000U)
+#define GPIO_BSRR_BS_15 (0x00008000U)
+#define GPIO_BSRR_BR_0 (0x00010000U)
+#define GPIO_BSRR_BR_1 (0x00020000U)
+#define GPIO_BSRR_BR_2 (0x00040000U)
+#define GPIO_BSRR_BR_3 (0x00080000U)
+#define GPIO_BSRR_BR_4 (0x00100000U)
+#define GPIO_BSRR_BR_5 (0x00200000U)
+#define GPIO_BSRR_BR_6 (0x00400000U)
+#define GPIO_BSRR_BR_7 (0x00800000U)
+#define GPIO_BSRR_BR_8 (0x01000000U)
+#define GPIO_BSRR_BR_9 (0x02000000U)
+#define GPIO_BSRR_BR_10 (0x04000000U)
+#define GPIO_BSRR_BR_11 (0x08000000U)
+#define GPIO_BSRR_BR_12 (0x10000000U)
+#define GPIO_BSRR_BR_13 (0x20000000U)
+#define GPIO_BSRR_BR_14 (0x40000000U)
+#define GPIO_BSRR_BR_15 (0x80000000U)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 (0x00000001U)
+#define GPIO_BRR_BR_1 (0x00000002U)
+#define GPIO_BRR_BR_2 (0x00000004U)
+#define GPIO_BRR_BR_3 (0x00000008U)
+#define GPIO_BRR_BR_4 (0x00000010U)
+#define GPIO_BRR_BR_5 (0x00000020U)
+#define GPIO_BRR_BR_6 (0x00000040U)
+#define GPIO_BRR_BR_7 (0x00000080U)
+#define GPIO_BRR_BR_8 (0x00000100U)
+#define GPIO_BRR_BR_9 (0x00000200U)
+#define GPIO_BRR_BR_10 (0x00000400U)
+#define GPIO_BRR_BR_11 (0x00000800U)
+#define GPIO_BRR_BR_12 (0x00001000U)
+#define GPIO_BRR_BR_13 (0x00002000U)
+#define GPIO_BRR_BR_14 (0x00004000U)
+#define GPIO_BRR_BR_15 (0x00008000U)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos (1U)
+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos (2U)
+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos (3U)
+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos (4U)
+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos (5U)
+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos (6U)
+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos (7U)
+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos (8U)
+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos (12U)
+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos (14U)
+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos (15U)
+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos (16U)
+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos (17U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos (18U)
+#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos (19U)
+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos (20U)
+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos (21U)
+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos (22U)
+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos (23U)
+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD_Pos (0U)
+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos (10U)
+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos (11U)
+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos (12U)
+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos (13U)
+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
+#define I2C_CR2_STOP_Pos (14U)
+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos (15U)
+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos (16U)
+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos (24U)
+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos (25U)
+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos (26U)
+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1_Pos (0U)
+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos (10U)
+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos (15U)
+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2_Pos (1U)
+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos (8U)
+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos (8U)
+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos (9U)
+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos (8U)
+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos (10U)
+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos (8U)
+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos (9U)
+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos (8U)
+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos (15U)
+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos (0U)
+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos (8U)
+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos (16U)
+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos (20U)
+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos (28U)
+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE_Pos (0U)
+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos (1U)
+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos (2U)
+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos (3U)
+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos (4U)
+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos (5U)
+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos (6U)
+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos (7U)
+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos (8U)
+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
+#define I2C_ISR_ARLO_Pos (9U)
+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos (10U)
+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos (11U)
+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos (12U)
+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos (13U)
+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos (15U)
+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
+#define I2C_ISR_DIR_Pos (16U)
+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos (17U)
+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF_Pos (3U)
+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos (4U)
+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos (5U)
+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos (8U)
+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos (9U)
+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos (10U)
+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos (11U)
+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos (12U)
+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos (13U)
+#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define I2C_PECR_PEC_Pos (0U)
+#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA_Pos (0U)
+#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA_Pos (0U)
+#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos (2U)
+#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN_Pos (0U)
+#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* LCD Controller (LCD) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for LCD_CR register *********************/
+#define LCD_CR_LCDEN_Pos (0U)
+#define LCD_CR_LCDEN_Msk (0x1UL << LCD_CR_LCDEN_Pos) /*!< 0x00000001 */
+#define LCD_CR_LCDEN LCD_CR_LCDEN_Msk /*!< LCD Enable Bit */
+#define LCD_CR_VSEL_Pos (1U)
+#define LCD_CR_VSEL_Msk (0x1UL << LCD_CR_VSEL_Pos) /*!< 0x00000002 */
+#define LCD_CR_VSEL LCD_CR_VSEL_Msk /*!< Voltage source selector Bit */
+
+#define LCD_CR_DUTY_Pos (2U)
+#define LCD_CR_DUTY_Msk (0x7UL << LCD_CR_DUTY_Pos) /*!< 0x0000001C */
+#define LCD_CR_DUTY LCD_CR_DUTY_Msk /*!< DUTY[2:0] bits (Duty selector) */
+#define LCD_CR_DUTY_0 (0x1UL << LCD_CR_DUTY_Pos) /*!< 0x00000004 */
+#define LCD_CR_DUTY_1 (0x2UL << LCD_CR_DUTY_Pos) /*!< 0x00000008 */
+#define LCD_CR_DUTY_2 (0x4UL << LCD_CR_DUTY_Pos) /*!< 0x00000010 */
+
+#define LCD_CR_BIAS_Pos (5U)
+#define LCD_CR_BIAS_Msk (0x3UL << LCD_CR_BIAS_Pos) /*!< 0x00000060 */
+#define LCD_CR_BIAS LCD_CR_BIAS_Msk /*!< BIAS[1:0] bits (Bias selector) */
+#define LCD_CR_BIAS_0 (0x1UL << LCD_CR_BIAS_Pos) /*!< 0x00000020 */
+#define LCD_CR_BIAS_1 (0x2UL << LCD_CR_BIAS_Pos) /*!< 0x00000040 */
+
+#define LCD_CR_MUX_SEG_Pos (7U)
+#define LCD_CR_MUX_SEG_Msk (0x1UL << LCD_CR_MUX_SEG_Pos) /*!< 0x00000080 */
+#define LCD_CR_MUX_SEG LCD_CR_MUX_SEG_Msk /*!< Mux Segment Enable Bit */
+
+#define LCD_CR_BUFEN_Pos (8U)
+#define LCD_CR_BUFEN_Msk (0x1UL << LCD_CR_BUFEN_Pos) /*!< 0x00000100 */
+#define LCD_CR_BUFEN LCD_CR_BUFEN_Msk /*!< Voltage output buffer enable Bit */
+
+/******************* Bit definition for LCD_FCR register ********************/
+#define LCD_FCR_HD_Pos (0U)
+#define LCD_FCR_HD_Msk (0x1UL << LCD_FCR_HD_Pos) /*!< 0x00000001 */
+#define LCD_FCR_HD LCD_FCR_HD_Msk /*!< High Drive Enable Bit */
+#define LCD_FCR_SOFIE_Pos (1U)
+#define LCD_FCR_SOFIE_Msk (0x1UL << LCD_FCR_SOFIE_Pos) /*!< 0x00000002 */
+#define LCD_FCR_SOFIE LCD_FCR_SOFIE_Msk /*!< Start of Frame Interrupt Enable Bit */
+#define LCD_FCR_UDDIE_Pos (3U)
+#define LCD_FCR_UDDIE_Msk (0x1UL << LCD_FCR_UDDIE_Pos) /*!< 0x00000008 */
+#define LCD_FCR_UDDIE LCD_FCR_UDDIE_Msk /*!< Update Display Done Interrupt Enable Bit */
+
+#define LCD_FCR_PON_Pos (4U)
+#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */
+#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */
+#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */
+#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */
+
+#define LCD_FCR_DEAD_Pos (7U)
+#define LCD_FCR_DEAD_Msk (0x7UL << LCD_FCR_DEAD_Pos) /*!< 0x00000380 */
+#define LCD_FCR_DEAD LCD_FCR_DEAD_Msk /*!< DEAD[2:0] bits (DEAD Time) */
+#define LCD_FCR_DEAD_0 (0x1UL << LCD_FCR_DEAD_Pos) /*!< 0x00000080 */
+#define LCD_FCR_DEAD_1 (0x2UL << LCD_FCR_DEAD_Pos) /*!< 0x00000100 */
+#define LCD_FCR_DEAD_2 (0x4UL << LCD_FCR_DEAD_Pos) /*!< 0x00000200 */
+
+#define LCD_FCR_CC_Pos (10U)
+#define LCD_FCR_CC_Msk (0x7UL << LCD_FCR_CC_Pos) /*!< 0x00001C00 */
+#define LCD_FCR_CC LCD_FCR_CC_Msk /*!< CC[2:0] bits (Contrast Control) */
+#define LCD_FCR_CC_0 (0x1UL << LCD_FCR_CC_Pos) /*!< 0x00000400 */
+#define LCD_FCR_CC_1 (0x2UL << LCD_FCR_CC_Pos) /*!< 0x00000800 */
+#define LCD_FCR_CC_2 (0x4UL << LCD_FCR_CC_Pos) /*!< 0x00001000 */
+
+#define LCD_FCR_BLINKF_Pos (13U)
+#define LCD_FCR_BLINKF_Msk (0x7UL << LCD_FCR_BLINKF_Pos) /*!< 0x0000E000 */
+#define LCD_FCR_BLINKF LCD_FCR_BLINKF_Msk /*!< BLINKF[2:0] bits (Blink Frequency) */
+#define LCD_FCR_BLINKF_0 (0x1UL << LCD_FCR_BLINKF_Pos) /*!< 0x00002000 */
+#define LCD_FCR_BLINKF_1 (0x2UL << LCD_FCR_BLINKF_Pos) /*!< 0x00004000 */
+#define LCD_FCR_BLINKF_2 (0x4UL << LCD_FCR_BLINKF_Pos) /*!< 0x00008000 */
+
+#define LCD_FCR_BLINK_Pos (16U)
+#define LCD_FCR_BLINK_Msk (0x3UL << LCD_FCR_BLINK_Pos) /*!< 0x00030000 */
+#define LCD_FCR_BLINK LCD_FCR_BLINK_Msk /*!< BLINK[1:0] bits (Blink Enable) */
+#define LCD_FCR_BLINK_0 (0x1UL << LCD_FCR_BLINK_Pos) /*!< 0x00010000 */
+#define LCD_FCR_BLINK_1 (0x2UL << LCD_FCR_BLINK_Pos) /*!< 0x00020000 */
+
+#define LCD_FCR_DIV_Pos (18U)
+#define LCD_FCR_DIV_Msk (0xFUL << LCD_FCR_DIV_Pos) /*!< 0x003C0000 */
+#define LCD_FCR_DIV LCD_FCR_DIV_Msk /*!< DIV[3:0] bits (Divider) */
+#define LCD_FCR_PS_Pos (22U)
+#define LCD_FCR_PS_Msk (0xFUL << LCD_FCR_PS_Pos) /*!< 0x03C00000 */
+#define LCD_FCR_PS LCD_FCR_PS_Msk /*!< PS[3:0] bits (Prescaler) */
+
+/******************* Bit definition for LCD_SR register *********************/
+#define LCD_SR_ENS_Pos (0U)
+#define LCD_SR_ENS_Msk (0x1UL << LCD_SR_ENS_Pos) /*!< 0x00000001 */
+#define LCD_SR_ENS LCD_SR_ENS_Msk /*!< LCD Enabled Bit */
+#define LCD_SR_SOF_Pos (1U)
+#define LCD_SR_SOF_Msk (0x1UL << LCD_SR_SOF_Pos) /*!< 0x00000002 */
+#define LCD_SR_SOF LCD_SR_SOF_Msk /*!< Start Of Frame Flag Bit */
+#define LCD_SR_UDR_Pos (2U)
+#define LCD_SR_UDR_Msk (0x1UL << LCD_SR_UDR_Pos) /*!< 0x00000004 */
+#define LCD_SR_UDR LCD_SR_UDR_Msk /*!< Update Display Request Bit */
+#define LCD_SR_UDD_Pos (3U)
+#define LCD_SR_UDD_Msk (0x1UL << LCD_SR_UDD_Pos) /*!< 0x00000008 */
+#define LCD_SR_UDD LCD_SR_UDD_Msk /*!< Update Display Done Flag Bit */
+#define LCD_SR_RDY_Pos (4U)
+#define LCD_SR_RDY_Msk (0x1UL << LCD_SR_RDY_Pos) /*!< 0x00000010 */
+#define LCD_SR_RDY LCD_SR_RDY_Msk /*!< Ready Flag Bit */
+#define LCD_SR_FCRSR_Pos (5U)
+#define LCD_SR_FCRSR_Msk (0x1UL << LCD_SR_FCRSR_Pos) /*!< 0x00000020 */
+#define LCD_SR_FCRSR LCD_SR_FCRSR_Msk /*!< LCD FCR Register Synchronization Flag Bit */
+
+/******************* Bit definition for LCD_CLR register ********************/
+#define LCD_CLR_SOFC_Pos (1U)
+#define LCD_CLR_SOFC_Msk (0x1UL << LCD_CLR_SOFC_Pos) /*!< 0x00000002 */
+#define LCD_CLR_SOFC LCD_CLR_SOFC_Msk /*!< Start Of Frame Flag Clear Bit */
+#define LCD_CLR_UDDC_Pos (3U)
+#define LCD_CLR_UDDC_Msk (0x1UL << LCD_CLR_UDDC_Pos) /*!< 0x00000008 */
+#define LCD_CLR_UDDC LCD_CLR_UDDC_Msk /*!< Update Display Done Flag Clear Bit */
+
+/******************* Bit definition for LCD_RAM register ********************/
+#define LCD_RAM_SEGMENT_DATA_Pos (0U)
+#define LCD_RAM_SEGMENT_DATA_Msk (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos) /*!< 0xFFFFFFFF */
+#define LCD_RAM_SEGMENT_DATA LCD_RAM_SEGMENT_DATA_Msk /*!< Segment Data Bits */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM_Pos (0U)
+#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos (1U)
+#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos (2U)
+#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos (3U)
+#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos (4U)
+#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos (5U)
+#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos (6U)
+#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF_Pos (0U)
+#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos (1U)
+#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos (3U)
+#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos (4U)
+#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos (5U)
+#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos (6U)
+#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos (0U)
+#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos (1U)
+#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos (3U)
+#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos (4U)
+#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos (5U)
+#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos (6U)
+#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos (0U)
+#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos (1U)
+#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos (3U)
+#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos (6U)
+#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos (9U)
+#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos (17U)
+#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos (19U)
+#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos (20U)
+#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos (21U)
+#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos (22U)
+#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos (24U)
+#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE_Pos (0U)
+#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos (1U)
+#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos (2U)
+#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP_Pos (0U)
+#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR_Pos (0U)
+#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT_Pos (0U)
+#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
+
+/******************************************************************************/
+/* */
+/* MIFARE Firewall */
+/* */
+/******************************************************************************/
+
+/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
+#define FW_CSSA_ADD_Pos (8U)
+#define FW_CSSA_ADD_Msk (0xFFFFUL << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
+#define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
+#define FW_CSL_LENG_Pos (8U)
+#define FW_CSL_LENG_Msk (0x3FFFUL << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
+#define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
+#define FW_NVDSSA_ADD_Pos (8U)
+#define FW_NVDSSA_ADD_Msk (0xFFFFUL << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
+#define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
+#define FW_NVDSL_LENG_Pos (8U)
+#define FW_NVDSL_LENG_Msk (0x3FFFUL << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
+#define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
+#define FW_VDSSA_ADD_Pos (6U)
+#define FW_VDSSA_ADD_Msk (0x3FFUL << FW_VDSSA_ADD_Pos) /*!< 0x0000FFC0 */
+#define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
+#define FW_VDSL_LENG_Pos (6U)
+#define FW_VDSL_LENG_Msk (0x3FFUL << FW_VDSL_LENG_Pos) /*!< 0x0000FFC0 */
+#define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
+
+/**************************Bit definition for CR register *********************/
+#define FW_CR_FPA_Pos (0U)
+#define FW_CR_FPA_Msk (0x1UL << FW_CR_FPA_Pos) /*!< 0x00000001 */
+#define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
+#define FW_CR_VDS_Pos (1U)
+#define FW_CR_VDS_Msk (0x1UL << FW_CR_VDS_Pos) /*!< 0x00000002 */
+#define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
+#define FW_CR_VDE_Pos (2U)
+#define FW_CR_VDE_Msk (0x1UL << FW_CR_VDE_Pos) /*!< 0x00000004 */
+#define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
+
+/******************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/******************************************************************************/
+
+#define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPSDSR_Pos (0U)
+#define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP_Pos (9U)
+#define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /*!< 0x00000200 */
+#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
+#define PWR_CR_FWU_Pos (10U)
+#define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /*!< 0x00000400 */
+#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
+
+#define PWR_CR_VOS_Pos (11U)
+#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x00001800 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /*!< 0x00000800 */
+#define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /*!< 0x00001000 */
+#define PWR_CR_DSEEKOFF_Pos (13U)
+#define PWR_CR_DSEEKOFF_Msk (0x1UL << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */
+#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */
+#define PWR_CR_LPRUN_Pos (14U)
+#define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
+#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF_Pos (3U)
+#define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
+#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF_Pos (4U)
+#define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
+#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF_Pos (5U)
+#define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
+#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1_Pos (8U)
+#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2_Pos (9U)
+#define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
+#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+#define RCC_HSI48_SUPPORT /*!< HSI48 feature support */
+#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos (1U)
+#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos (2U)
+#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIVEN_Pos (3U)
+#define RCC_CR_HSIDIVEN_Msk (0x1UL << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */
+#define RCC_CR_HSIDIVF_Pos (4U)
+#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */
+#define RCC_CR_MSION_Pos (8U)
+#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000100 */
+#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY_Pos (9U)
+#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
+#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON_Pos (19U)
+#define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */
+#define RCC_CR_RTCPRE_Pos (20U)
+#define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
+#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC/LCD prescaler [1:0] bits */
+#define RCC_CR_RTCPRE_0 (0x1UL << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */
+#define RCC_CR_RTCPRE_1 (0x2UL << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+/* Reference defines */
+#define RCC_CR_CSSON RCC_CR_CSSHSEON
+
+/******************** Bit definition for RCC_ICSCR register *****************/
+#define RCC_ICSCR_HSICAL_Pos (0U)
+#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
+#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM_Pos (8U)
+#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
+#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE_Pos (13U)
+#define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
+#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
+#define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
+#define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
+#define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
+#define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
+#define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
+#define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
+#define RCC_ICSCR_MSICAL_Pos (16U)
+#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
+#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM_Pos (24U)
+#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
+#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
+
+/******************** Bit definition for RCC_CRRCR register *****************/
+#define RCC_CRRCR_HSI48ON_Pos (0U)
+#define RCC_CRRCR_HSI48ON_Msk (0x1UL << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
+#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk /*!< HSI 48MHz clock enable */
+#define RCC_CRRCR_HSI48RDY_Pos (1U)
+#define RCC_CRRCR_HSI48RDY_Msk (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
+#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk /*!< HSI 48MHz clock ready flag */
+#define RCC_CRRCR_HSI48CAL_Pos (8U)
+#define RCC_CRRCR_HSI48CAL_Msk (0xFFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI 48MHz clock Calibration */
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos (15U)
+#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */
+
+/*!< PLL entry clock source*/
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
+
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL_Pos (18U)
+#define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV_Pos (22U)
+#define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
+
+#define RCC_CFGR_PLLDIV2_Pos (22U)
+#define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3_Pos (23U)
+#define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4_Pos (22U)
+#define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCOSEL_Pos (24U)
+#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
+#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
+
+#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
+#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCOSEL_HSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_MSI_Pos (24U)
+#define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
+#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_HSE_Pos (26U)
+#define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCOSEL_PLL_Pos (24U)
+#define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
+#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
+#define RCC_CFGR_MCOSEL_LSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
+#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
+#define RCC_CFGR_MCOSEL_LSE_Pos (24U)
+#define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
+#define RCC_CFGR_MCOSEL_HSI48_Pos (27U)
+#define RCC_CFGR_MCOSEL_HSI48_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */
+#define RCC_CFGR_MCOSEL_HSI48 RCC_CFGR_MCOSEL_HSI48_Msk /*!< HSI48 clock selected as MCO source */
+
+#define RCC_CFGR_MCOPRE_Pos (28U)
+#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
+
+#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
+
+/* Legacy defines */
+#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
+#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
+#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
+#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
+#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
+#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
+#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
+#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
+#ifdef RCC_CFGR_MCOSEL_HSI48
+#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48
+#endif
+
+#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
+#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
+
+/*!<****************** Bit definition for RCC_CIER register ********************/
+#define RCC_CIER_LSIRDYIE_Pos (0U)
+#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIER_LSERDYIE_Pos (1U)
+#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIER_HSIRDYIE_Pos (2U)
+#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIER_HSERDYIE_Pos (3U)
+#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIER_PLLRDYIE_Pos (4U)
+#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIER_MSIRDYIE_Pos (5U)
+#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
+#define RCC_CIER_HSI48RDYIE_Pos (6U)
+#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000040 */
+#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk /*!< HSI48 Ready Interrupt Enable */
+#define RCC_CIER_CSSLSE_Pos (7U)
+#define RCC_CIER_CSSLSE_Msk (0x1UL << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */
+
+/* Reference defines */
+#define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
+
+/*!<****************** Bit definition for RCC_CIFR register ********************/
+#define RCC_CIFR_LSIRDYF_Pos (0U)
+#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIFR_LSERDYF_Pos (1U)
+#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIFR_HSIRDYF_Pos (2U)
+#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIFR_HSERDYF_Pos (3U)
+#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIFR_PLLRDYF_Pos (4U)
+#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIFR_MSIRDYF_Pos (5U)
+#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
+#define RCC_CIFR_HSI48RDYF_Pos (6U)
+#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk /*!< HSI48 Ready Interrupt flag */
+#define RCC_CIFR_CSSLSEF_Pos (7U)
+#define RCC_CIFR_CSSLSEF_Msk (0x1UL << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */
+#define RCC_CIFR_CSSHSEF_Pos (8U)
+#define RCC_CIFR_CSSHSEF_Msk (0x1UL << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */
+#define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */
+
+/* Reference defines */
+#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
+#define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
+
+/*!<****************** Bit definition for RCC_CICR register ********************/
+#define RCC_CICR_LSIRDYC_Pos (0U)
+#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CICR_LSERDYC_Pos (1U)
+#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CICR_HSIRDYC_Pos (2U)
+#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CICR_HSERDYC_Pos (3U)
+#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CICR_PLLRDYC_Pos (4U)
+#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CICR_MSIRDYC_Pos (5U)
+#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
+#define RCC_CICR_HSI48RDYC_Pos (6U)
+#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000040 */
+#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk /*!< HSI48 Ready Interrupt Clear */
+#define RCC_CICR_CSSLSEC_Pos (7U)
+#define RCC_CICR_CSSLSEC_Msk (0x1UL << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */
+#define RCC_CICR_CSSHSEC_Pos (8U)
+#define RCC_CICR_CSSHSEC_Msk (0x1UL << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */
+#define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */
+
+/* Reference defines */
+#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
+#define RCC_CICR_CSSC RCC_CICR_CSSHSEC
+/***************** Bit definition for RCC_IOPRSTR register ******************/
+#define RCC_IOPRSTR_IOPARST_Pos (0U)
+#define RCC_IOPRSTR_IOPARST_Msk (0x1UL << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */
+#define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */
+#define RCC_IOPRSTR_IOPBRST_Pos (1U)
+#define RCC_IOPRSTR_IOPBRST_Msk (0x1UL << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */
+#define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */
+#define RCC_IOPRSTR_IOPCRST_Pos (2U)
+#define RCC_IOPRSTR_IOPCRST_Msk (0x1UL << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */
+#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */
+#define RCC_IOPRSTR_IOPDRST_Pos (3U)
+#define RCC_IOPRSTR_IOPDRST_Msk (0x1UL << RCC_IOPRSTR_IOPDRST_Pos) /*!< 0x00000008 */
+#define RCC_IOPRSTR_IOPDRST RCC_IOPRSTR_IOPDRST_Msk /*!< GPIO port D reset */
+#define RCC_IOPRSTR_IOPHRST_Pos (7U)
+#define RCC_IOPRSTR_IOPHRST_Msk (0x1UL << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */
+#define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */
+
+/* Reference defines */
+#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
+#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
+#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
+#define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_IOPDRST /*!< GPIO port D reset */
+#define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
+
+
+/****************** Bit definition for RCC_AHBRST register ******************/
+#define RCC_AHBRSTR_DMARST_Pos (0U)
+#define RCC_AHBRSTR_DMARST_Msk (0x1UL << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */
+#define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */
+#define RCC_AHBRSTR_MIFRST_Pos (8U)
+#define RCC_AHBRSTR_MIFRST_Msk (0x1UL << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */
+#define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset */
+#define RCC_AHBRSTR_CRCRST_Pos (12U)
+#define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */
+#define RCC_AHBRSTR_TSCRST_Pos (16U)
+#define RCC_AHBRSTR_TSCRST_Msk (0x1UL << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x00010000 */
+#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TSC reset */
+#define RCC_AHBRSTR_RNGRST_Pos (20U)
+#define RCC_AHBRSTR_RNGRST_Msk (0x1UL << RCC_AHBRSTR_RNGRST_Pos) /*!< 0x00100000 */
+#define RCC_AHBRSTR_RNGRST RCC_AHBRSTR_RNGRST_Msk /*!< RNG reset */
+
+/* Reference defines */
+#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
+#define RCC_APB2RSTR_TIM21RST_Pos (2U)
+#define RCC_APB2RSTR_TIM21RST_Msk (0x1UL << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 reset */
+#define RCC_APB2RSTR_TIM22RST_Pos (5U)
+#define RCC_APB2RSTR_TIM22RST_Msk (0x1UL << RCC_APB2RSTR_TIM22RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk /*!< TIM22 reset */
+#define RCC_APB2RSTR_ADCRST_Pos (9U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
+#define RCC_APB2RSTR_DBGRST_Pos (22U)
+#define RCC_APB2RSTR_DBGRST_Msk (0x1UL << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU reset */
+
+/* Reference defines */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 reset */
+#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU reset */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
+#define RCC_APB1RSTR_LCDRST_Pos (9U)
+#define RCC_APB1RSTR_LCDRST_Msk (0x1UL << RCC_APB1RSTR_LCDRST_Pos) /*!< 0x00000200 */
+#define RCC_APB1RSTR_LCDRST RCC_APB1RSTR_LCDRST_Msk /*!< LCD reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_LPUART1RST_Pos (18U)
+#define RCC_APB1RSTR_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
+#define RCC_APB1RSTR_USBRST_Pos (23U)
+#define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */
+#define RCC_APB1RSTR_CRSRST_Pos (27U)
+#define RCC_APB1RSTR_CRSRST_Msk (0x1UL << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
+#define RCC_APB1RSTR_DACRST_Pos (29U)
+#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC reset */
+#define RCC_APB1RSTR_LPTIM1RST_Pos (31U)
+#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 reset */
+
+/***************** Bit definition for RCC_IOPENR register ******************/
+#define RCC_IOPENR_IOPAEN_Pos (0U)
+#define RCC_IOPENR_IOPAEN_Msk (0x1UL << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */
+#define RCC_IOPENR_IOPBEN_Pos (1U)
+#define RCC_IOPENR_IOPBEN_Msk (0x1UL << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */
+#define RCC_IOPENR_IOPCEN_Pos (2U)
+#define RCC_IOPENR_IOPCEN_Msk (0x1UL << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */
+#define RCC_IOPENR_IOPDEN_Pos (3U)
+#define RCC_IOPENR_IOPDEN_Msk (0x1UL << RCC_IOPENR_IOPDEN_Pos) /*!< 0x00000008 */
+#define RCC_IOPENR_IOPDEN RCC_IOPENR_IOPDEN_Msk /*!< GPIO port D clock enable */
+#define RCC_IOPENR_IOPHEN_Pos (7U)
+#define RCC_IOPENR_IOPHEN_Msk (0x1UL << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */
+
+/* Reference defines */
+#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
+#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
+#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
+#define RCC_IOPENR_GPIODEN RCC_IOPENR_IOPDEN /*!< GPIO port D clock enable */
+#define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
+
+/***************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMAEN_Pos (0U)
+#define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_MIFEN_Pos (8U)
+#define RCC_AHBENR_MIFEN_Msk (0x1UL << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */
+#define RCC_AHBENR_CRCEN_Pos (12U)
+#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+#define RCC_AHBENR_TSCEN_Pos (16U)
+#define RCC_AHBENR_TSCEN_Msk (0x1UL << RCC_AHBENR_TSCEN_Pos) /*!< 0x00010000 */
+#define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TSC clock enable */
+#define RCC_AHBENR_RNGEN_Pos (20U)
+#define RCC_AHBENR_RNGEN_Msk (0x1UL << RCC_AHBENR_RNGEN_Pos) /*!< 0x00100000 */
+#define RCC_AHBENR_RNGEN RCC_AHBENR_RNGEN_Msk /*!< RNG clock enable */
+
+/* Reference defines */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register ******************/
+#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM21EN_Pos (2U)
+#define RCC_APB2ENR_TIM21EN_Msk (0x1UL << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */
+#define RCC_APB2ENR_TIM22EN_Pos (5U)
+#define RCC_APB2ENR_TIM22EN_Msk (0x1UL << RCC_APB2ENR_TIM22EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk /*!< TIM22 clock enable */
+#define RCC_APB2ENR_FWEN_Pos (7U)
+#define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADCEN_Pos (9U)
+#define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
+#define RCC_APB2ENR_DBGEN_Pos (22U)
+#define RCC_APB2ENR_DBGEN_Msk (0x1UL << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */
+
+/* Reference defines */
+
+#define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_LCDEN_Pos (9U)
+#define RCC_APB1ENR_LCDEN_Msk (0x1UL << RCC_APB1ENR_LCDEN_Pos) /*!< 0x00000200 */
+#define RCC_APB1ENR_LCDEN RCC_APB1ENR_LCDEN_Msk /*!< LCD clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
+#define RCC_APB1ENR_LPUART1EN_Pos (18U)
+#define RCC_APB1ENR_LPUART1EN_Msk (0x1UL << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */
+#define RCC_APB1ENR_USBEN_Pos (23U)
+#define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */
+#define RCC_APB1ENR_CRSEN_Pos (27U)
+#define RCC_APB1ENR_CRSEN_Msk (0x1UL << RCC_APB1ENR_CRSEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
+#define RCC_APB1ENR_DACEN_Pos (29U)
+#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC clock enable */
+#define RCC_APB1ENR_LPTIM1EN_Pos (31U)
+#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */
+
+/****************** Bit definition for RCC_IOPSMENR register ****************/
+#define RCC_IOPSMENR_IOPASMEN_Pos (0U)
+#define RCC_IOPSMENR_IOPASMEN_Msk (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPBSMEN_Pos (1U)
+#define RCC_IOPSMENR_IOPBSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPCSMEN_Pos (2U)
+#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPDSMEN_Pos (3U)
+#define RCC_IOPSMENR_IOPDSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos) /*!< 0x00000008 */
+#define RCC_IOPSMENR_IOPDSMEN RCC_IOPSMENR_IOPDSMEN_Msk /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPHSMEN_Pos (7U)
+#define RCC_IOPSMENR_IOPHSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_IOPDSMEN /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_AHBSMENR register ******************/
+#define RCC_AHBSMENR_DMASMEN_Pos (0U)
+#define RCC_AHBSMENR_DMASMEN_Msk (0x1UL << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */
+#define RCC_AHBSMENR_MIFSMEN_Pos (8U)
+#define RCC_AHBSMENR_MIFSMEN_Msk (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */
+#define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
+#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRCSMEN_Pos (12U)
+#define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */
+#define RCC_AHBSMENR_TSCSMEN_Pos (16U)
+#define RCC_AHBSMENR_TSCSMEN_Msk (0x1UL << RCC_AHBSMENR_TSCSMEN_Pos) /*!< 0x00010000 */
+#define RCC_AHBSMENR_TSCSMEN RCC_AHBSMENR_TSCSMEN_Msk /*!< TSC clock enabled in sleep mode */
+#define RCC_AHBSMENR_RNGSMEN_Pos (20U)
+#define RCC_AHBSMENR_RNGSMEN_Msk (0x1UL << RCC_AHBSMENR_RNGSMEN_Pos) /*!< 0x00100000 */
+#define RCC_AHBSMENR_RNGSMEN RCC_AHBSMENR_RNGSMEN_Msk /*!< RNG clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB2SMENR register ******************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM21SMEN_Pos (2U)
+#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM22SMEN_Pos (5U)
+#define RCC_APB2SMENR_TIM22SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk /*!< TIM22 clock enabled in sleep mode */
+#define RCC_APB2SMENR_ADCSMEN_Pos (9U)
+#define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
+#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
+#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk /*!< USART1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGSMEN_Pos (22U)
+#define RCC_APB2SMENR_DBGSMEN_Msk (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB1SMENR register ******************/
+#define RCC_APB1SMENR_TIM2SMEN_Pos (0U)
+#define RCC_APB1SMENR_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_TIM6SMEN_Pos (4U)
+#define RCC_APB1SMENR_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM6SMEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1SMENR_TIM6SMEN RCC_APB1SMENR_TIM6SMEN_Msk /*!< Timer 6 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LCDSMEN_Pos (9U)
+#define RCC_APB1SMENR_LCDSMEN_Msk (0x1UL << RCC_APB1SMENR_LCDSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB1SMENR_LCDSMEN RCC_APB1SMENR_LCDSMEN_Msk /*!< LCD clock enabled in sleep mode */
+#define RCC_APB1SMENR_WWDGSMEN_Pos (11U)
+#define RCC_APB1SMENR_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */
+#define RCC_APB1SMENR_SPI2SMEN_Pos (14U)
+#define RCC_APB1SMENR_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR_SPI2SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1SMENR_SPI2SMEN RCC_APB1SMENR_SPI2SMEN_Msk /*!< SPI2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART2SMEN_Pos (17U)
+#define RCC_APB1SMENR_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPUART1SMEN_Pos (18U)
+#define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C1SMEN_Pos (21U)
+#define RCC_APB1SMENR_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C2SMEN_Pos (22U)
+#define RCC_APB1SMENR_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1SMENR_I2C2SMEN RCC_APB1SMENR_I2C2SMEN_Msk /*!< I2C2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USBSMEN_Pos (23U)
+#define RCC_APB1SMENR_USBSMEN_Msk (0x1UL << RCC_APB1SMENR_USBSMEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1SMENR_USBSMEN RCC_APB1SMENR_USBSMEN_Msk /*!< USB clock enabled in sleep mode */
+#define RCC_APB1SMENR_CRSSMEN_Pos (27U)
+#define RCC_APB1SMENR_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR_CRSSMEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1SMENR_CRSSMEN RCC_APB1SMENR_CRSSMEN_Msk /*!< CRS clock enabled in sleep mode */
+#define RCC_APB1SMENR_PWRSMEN_Pos (28U)
+#define RCC_APB1SMENR_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */
+#define RCC_APB1SMENR_DACSMEN_Pos (29U)
+#define RCC_APB1SMENR_DACSMEN_Msk (0x1UL << RCC_APB1SMENR_DACSMEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1SMENR_DACSMEN RCC_APB1SMENR_DACSMEN_Msk /*!< DAC clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U)
+#define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */
+
+/******************* Bit definition for RCC_CCIPR register *******************/
+/*!< USART1 Clock source selection */
+#define RCC_CCIPR_USART1SEL_Pos (0U)
+#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
+#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk /*!< USART1SEL[1:0] bits */
+#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
+
+/*!< USART2 Clock source selection */
+#define RCC_CCIPR_USART2SEL_Pos (2U)
+#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */
+#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+/*!< LPUART1 Clock source selection */
+#define RCC_CCIPR_LPUART1SEL_Pos (10U)
+#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */
+#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */
+#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CCIPR_I2C1SEL_Pos (12U)
+#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */
+#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
+
+
+/*!< LPTIM1 Clock source selection */
+#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
+#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */
+#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+/*!< HSI48 Clock source selection */
+#define RCC_CCIPR_HSI48SEL_Pos (26U)
+#define RCC_CCIPR_HSI48SEL_Msk (0x1UL << RCC_CCIPR_HSI48SEL_Pos) /*!< 0x04000000 */
+#define RCC_CCIPR_HSI48SEL RCC_CCIPR_HSI48SEL_Msk /*!< HSI48 RC clock source selection bit for USB and RNG*/
+
+/* Legacy defines */
+#define RCC_CCIPR_HSI48MSEL RCC_CCIPR_HSI48SEL
+
+/******************* Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSEON_Pos (8U)
+#define RCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */
+#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_CSR_LSERDY_Pos (9U)
+#define RCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */
+#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP_Pos (10U)
+#define RCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */
+#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_CSR_LSEDRV_Pos (11U)
+#define RCC_CSR_LSEDRV_Msk (0x3UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */
+#define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_CSR_LSEDRV_0 (0x1UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */
+#define RCC_CSR_LSEDRV_1 (0x2UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */
+
+#define RCC_CSR_LSECSSON_Pos (13U)
+#define RCC_CSR_LSECSSON_Msk (0x1UL << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */
+#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */
+#define RCC_CSR_LSECSSD_Pos (14U)
+#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
+#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
+
+/*!< RTC congiguration */
+#define RCC_CSR_RTCSEL_Pos (16U)
+#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
+
+#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CSR_RTCSEL_LSE_Pos (16U)
+#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_LSI_Pos (17U)
+#define RCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */
+#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_HSE_Pos (16U)
+#define RCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */
+
+#define RCC_CSR_RTCEN_Pos (18U)
+#define RCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */
+#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_CSR_RTCRST_Pos (19U)
+#define RCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */
+#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */
+
+#define RCC_CSR_RMVF_Pos (23U)
+#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_FWRSTF_Pos (24U)
+#define RCC_CSR_FWRSTF_Msk (0x1UL << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk /*!< Mifare Firewall reset flag */
+#define RCC_CSR_OBLRSTF_Pos (25U)
+#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+/* Reference defines */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN_Pos (2U)
+#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
+#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos (3U)
+#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
+#define RNG_CR_IE RNG_CR_IE_Msk
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY_Pos (0U)
+#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
+#define RNG_SR_DRDY RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos (1U)
+#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
+#define RNG_SR_CECS RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos (2U)
+#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
+#define RNG_SR_SECS RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos (5U)
+#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
+#define RNG_SR_CEIS RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos (6U)
+#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
+#define RNG_SR_SEIS RNG_SR_SEIS_Msk
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER1_SUPPORT
+#define RTC_TAMPER2_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk /*!< */
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk /*!< */
+#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk /*!< */
+#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */
+#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */
+#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk /*!< */
+#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk /*!< */
+#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk /*!< */
+#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk /*!< */
+#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */
+#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk /*!< */
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk /*!< */
+#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk /*!< */
+#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk /*!< */
+#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk /*!< */
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */
+#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk /*!< */
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< */
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */
+#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */
+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */
+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */
+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */
+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */
+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */
+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */
+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */
+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */
+#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */
+#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */
+#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */
+#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */
+#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */
+#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */
+#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */
+#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */
+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */
+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */
+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */
+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */
+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */
+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */
+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */
+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */
+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */
+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CALR register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */
+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define RTC_CAL_CALP RTC_CALR_CALP
+#define RTC_CAL_CALW8 RTC_CALR_CALW8
+#define RTC_CAL_CALW16 RTC_CALR_CALW16
+#define RTC_CAL_CALM RTC_CALR_CALM
+#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
+
+/******************** Bits definition for RTC_TAMPCR register ****************/
+#define RTC_TAMPCR_TAMP2MF_Pos (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2IE_Pos (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1MF_Pos (18U)
+#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
+#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1IE_Pos (16U)
+#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */
+#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */
+#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */
+#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos (7U)
+#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */
+#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP2E_Pos (3U)
+#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */
+#define RTC_TAMPCR_TAMPIE_Pos (2U)
+#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
+#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP1E_Pos (0U)
+#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_OR register ****************/
+#define RTC_OR_OUT_RMP_Pos (1U)
+#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */
+#define RTC_OR_ALARMOUTTYPE_Pos (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */
+
+/* Legacy defines */
+#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk /*!< */
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER (0x00000005U) /*!< */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+#define SPI_I2S_SUPPORT /*!< I2S support */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
+#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR1_BOOT_MODE_Pos (8U)
+#define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
+#define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */
+#define SYSCFG_CFGR1_BOOT_MODE_0 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOT_MODE_1 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_FWDISEN_Pos (0U)
+#define SYSCFG_CFGR2_FWDISEN_Msk (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */
+#define SYSCFG_CFGR2_CAPA_Pos (1U)
+#define SYSCFG_CFGR2_CAPA_Msk (0x7UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x0000000E */
+#define SYSCFG_CFGR2_CAPA SYSCFG_CFGR2_CAPA_Msk /*!< Connection of internal Vlcd rail to external capacitors */
+#define SYSCFG_CFGR2_CAPA_0 (0x1UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR2_CAPA_1 (0x2UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000004 */
+#define SYSCFG_CFGR2_CAPA_2 (0x4UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000008 */
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos (8U)
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR2_I2C_PB6_FMP SYSCFG_CFGR2_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos (9U)
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR2_I2C_PB7_FMP SYSCFG_CFGR2_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos (10U)
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
+#define SYSCFG_CFGR2_I2C_PB8_FMP SYSCFG_CFGR2_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos (11U)
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
+#define SYSCFG_CFGR2_I2C_PB9_FMP SYSCFG_CFGR2_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR2_I2C1_FMP_Pos (12U)
+#define SYSCFG_CFGR2_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR2_I2C1_FMP SYSCFG_CFGR2_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR2_I2C2_FMP_Pos (13U)
+#define SYSCFG_CFGR2_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
+#define SYSCFG_CFGR2_I2C2_FMP SYSCFG_CFGR2_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
+
+
+/***************** Bit definition for SYSCFG_CFGR3 register ****************/
+#define SYSCFG_CFGR3_EN_VREFINT_Pos (0U)
+#define SYSCFG_CFGR3_EN_VREFINT_Msk (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_EN_VREFINT SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
+#define SYSCFG_CFGR3_VREF_OUT_Pos (4U)
+#define SYSCFG_CFGR3_VREF_OUT_Msk (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
+#define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */
+#define SYSCFG_CFGR3_VREF_OUT_0 (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
+#define SYSCFG_CFGR3_VREF_OUT_1 (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U)
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U)
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U)
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
+#define SYSCFG_CFGR3_ENREF_HSI48_Pos (13U)
+#define SYSCFG_CFGR3_ENREF_HSI48_Msk (0x1UL << SYSCFG_CFGR3_ENREF_HSI48_Pos) /*!< 0x00002000 */
+#define SYSCFG_CFGR3_ENREF_HSI48 SYSCFG_CFGR3_ENREF_HSI48_Msk /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
+#define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U)
+#define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
+#define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
+#define SYSCFG_CFGR3_REF_LOCK_Pos (31U)
+#define SYSCFG_CFGR3_REF_LOCK_Msk (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
+#define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */
+
+/* Legacy defines */
+
+#define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
+#define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
+#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
+#define SYSCFG_CFGR3_ENREF_RC48MHz SYSCFG_CFGR3_ENREF_HSI48
+#define SYSCFG_CFGR3_REF_RC48MHz_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_REF_HSI48_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+
+/******************************************************************************/
+/* */
+/* Timers (TIM)*/
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
+#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
+ || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#else
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#endif
+
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFUL << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFUL << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM2_OR_ETR_RMP_Pos (0U)
+#define TIM2_OR_ETR_RMP_Msk (0x7UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000007 */
+#define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
+#define TIM2_OR_ETR_RMP_0 (0x1UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM2_OR_ETR_RMP_1 (0x2UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM2_OR_ETR_RMP_2 (0x4UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000004 */
+#define TIM2_OR_TI4_RMP_Pos (3U)
+#define TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000018 */
+#define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
+#define TIM2_OR_TI4_RMP_0 (0x1UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */
+#define TIM2_OR_TI4_RMP_1 (0x2UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000010 */
+
+#define TIM21_OR_ETR_RMP_Pos (0U)
+#define TIM21_OR_ETR_RMP_Msk (0x3UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
+#define TIM21_OR_ETR_RMP_0 (0x1UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM21_OR_ETR_RMP_1 (0x2UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM21_OR_TI1_RMP_Pos (2U)
+#define TIM21_OR_TI1_RMP_Msk (0x7UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x0000001C */
+#define TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
+#define TIM21_OR_TI1_RMP_0 (0x1UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM21_OR_TI1_RMP_1 (0x2UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+#define TIM21_OR_TI1_RMP_2 (0x4UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000010 */
+#define TIM21_OR_TI2_RMP_Pos (5U)
+#define TIM21_OR_TI2_RMP_Msk (0x1UL << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */
+#define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */
+
+#define TIM22_OR_ETR_RMP_Pos (0U)
+#define TIM22_OR_ETR_RMP_Msk (0x3UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM22_OR_ETR_RMP TIM22_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
+#define TIM22_OR_ETR_RMP_0 (0x1UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM22_OR_ETR_RMP_1 (0x2UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM22_OR_TI1_RMP_Pos (2U)
+#define TIM22_OR_TI1_RMP_Msk (0x3UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x0000000C */
+#define TIM22_OR_TI1_RMP TIM22_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
+#define TIM22_OR_TI1_RMP_0 (0x1UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM22_OR_TI1_RMP_1 (0x2UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+
+
+/******************************************************************************/
+/* */
+/* Touch Sensing Controller (TSC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TSC_CR register *********************/
+#define TSC_CR_TSCE_Pos (0U)
+#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
+#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
+#define TSC_CR_START_Pos (1U)
+#define TSC_CR_START_Msk (0x1UL << TSC_CR_START_Pos) /*!< 0x00000002 */
+#define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
+#define TSC_CR_AM_Pos (2U)
+#define TSC_CR_AM_Msk (0x1UL << TSC_CR_AM_Pos) /*!< 0x00000004 */
+#define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL_Pos (3U)
+#define TSC_CR_SYNCPOL_Msk (0x1UL << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
+#define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF_Pos (4U)
+#define TSC_CR_IODEF_Msk (0x1UL << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
+#define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
+
+#define TSC_CR_MCV_Pos (5U)
+#define TSC_CR_MCV_Msk (0x7UL << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
+#define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0 (0x1UL << TSC_CR_MCV_Pos) /*!< 0x00000020 */
+#define TSC_CR_MCV_1 (0x2UL << TSC_CR_MCV_Pos) /*!< 0x00000040 */
+#define TSC_CR_MCV_2 (0x4UL << TSC_CR_MCV_Pos) /*!< 0x00000080 */
+
+#define TSC_CR_PGPSC_Pos (12U)
+#define TSC_CR_PGPSC_Msk (0x7UL << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
+#define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0 (0x1UL << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
+#define TSC_CR_PGPSC_1 (0x2UL << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
+#define TSC_CR_PGPSC_2 (0x4UL << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
+
+#define TSC_CR_SSPSC_Pos (15U)
+#define TSC_CR_SSPSC_Msk (0x1UL << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
+#define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE_Pos (16U)
+#define TSC_CR_SSE_Msk (0x1UL << TSC_CR_SSE_Pos) /*!< 0x00010000 */
+#define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD_Pos (17U)
+#define TSC_CR_SSD_Msk (0x7FUL << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
+#define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0 (0x01UL << TSC_CR_SSD_Pos) /*!< 0x00020000 */
+#define TSC_CR_SSD_1 (0x02UL << TSC_CR_SSD_Pos) /*!< 0x00040000 */
+#define TSC_CR_SSD_2 (0x04UL << TSC_CR_SSD_Pos) /*!< 0x00080000 */
+#define TSC_CR_SSD_3 (0x08UL << TSC_CR_SSD_Pos) /*!< 0x00100000 */
+#define TSC_CR_SSD_4 (0x10UL << TSC_CR_SSD_Pos) /*!< 0x00200000 */
+#define TSC_CR_SSD_5 (0x20UL << TSC_CR_SSD_Pos) /*!< 0x00400000 */
+#define TSC_CR_SSD_6 (0x40UL << TSC_CR_SSD_Pos) /*!< 0x00800000 */
+
+#define TSC_CR_CTPL_Pos (24U)
+#define TSC_CR_CTPL_Msk (0xFUL << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
+#define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0 (0x1UL << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
+#define TSC_CR_CTPL_1 (0x2UL << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
+#define TSC_CR_CTPL_2 (0x4UL << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
+#define TSC_CR_CTPL_3 (0x8UL << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
+
+#define TSC_CR_CTPH_Pos (28U)
+#define TSC_CR_CTPH_Msk (0xFUL << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
+#define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0 (0x1UL << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
+#define TSC_CR_CTPH_1 (0x2UL << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
+#define TSC_CR_CTPH_2 (0x4UL << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
+#define TSC_CR_CTPH_3 (0x8UL << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for TSC_IER register ********************/
+#define TSC_IER_EOAIE_Pos (0U)
+#define TSC_IER_EOAIE_Msk (0x1UL << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
+#define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE_Pos (1U)
+#define TSC_IER_MCEIE_Msk (0x1UL << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
+#define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
+
+/******************* Bit definition for TSC_ICR register ********************/
+#define TSC_ICR_EOAIC_Pos (0U)
+#define TSC_ICR_EOAIC_Msk (0x1UL << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
+#define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC_Pos (1U)
+#define TSC_ICR_MCEIC_Msk (0x1UL << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
+#define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
+
+/******************* Bit definition for TSC_ISR register ********************/
+#define TSC_ISR_EOAF_Pos (0U)
+#define TSC_ISR_EOAF_Msk (0x1UL << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
+#define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
+#define TSC_ISR_MCEF_Pos (1U)
+#define TSC_ISR_MCEF_Msk (0x1UL << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
+#define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
+
+/******************* Bit definition for TSC_IOHCR register ******************/
+#define TSC_IOHCR_G1_IO1_Pos (0U)
+#define TSC_IOHCR_G1_IO1_Msk (0x1UL << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2_Pos (1U)
+#define TSC_IOHCR_G1_IO2_Msk (0x1UL << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3_Pos (2U)
+#define TSC_IOHCR_G1_IO3_Msk (0x1UL << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4_Pos (3U)
+#define TSC_IOHCR_G1_IO4_Msk (0x1UL << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1_Pos (4U)
+#define TSC_IOHCR_G2_IO1_Msk (0x1UL << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2_Pos (5U)
+#define TSC_IOHCR_G2_IO2_Msk (0x1UL << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3_Pos (6U)
+#define TSC_IOHCR_G2_IO3_Msk (0x1UL << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4_Pos (7U)
+#define TSC_IOHCR_G2_IO4_Msk (0x1UL << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1_Pos (8U)
+#define TSC_IOHCR_G3_IO1_Msk (0x1UL << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2_Pos (9U)
+#define TSC_IOHCR_G3_IO2_Msk (0x1UL << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3_Pos (10U)
+#define TSC_IOHCR_G3_IO3_Msk (0x1UL << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4_Pos (11U)
+#define TSC_IOHCR_G3_IO4_Msk (0x1UL << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1_Pos (12U)
+#define TSC_IOHCR_G4_IO1_Msk (0x1UL << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2_Pos (13U)
+#define TSC_IOHCR_G4_IO2_Msk (0x1UL << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3_Pos (14U)
+#define TSC_IOHCR_G4_IO3_Msk (0x1UL << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4_Pos (15U)
+#define TSC_IOHCR_G4_IO4_Msk (0x1UL << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1_Pos (16U)
+#define TSC_IOHCR_G5_IO1_Msk (0x1UL << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2_Pos (17U)
+#define TSC_IOHCR_G5_IO2_Msk (0x1UL << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3_Pos (18U)
+#define TSC_IOHCR_G5_IO3_Msk (0x1UL << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4_Pos (19U)
+#define TSC_IOHCR_G5_IO4_Msk (0x1UL << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1_Pos (20U)
+#define TSC_IOHCR_G6_IO1_Msk (0x1UL << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2_Pos (21U)
+#define TSC_IOHCR_G6_IO2_Msk (0x1UL << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3_Pos (22U)
+#define TSC_IOHCR_G6_IO3_Msk (0x1UL << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4_Pos (23U)
+#define TSC_IOHCR_G6_IO4_Msk (0x1UL << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1_Pos (24U)
+#define TSC_IOHCR_G7_IO1_Msk (0x1UL << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2_Pos (25U)
+#define TSC_IOHCR_G7_IO2_Msk (0x1UL << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3_Pos (26U)
+#define TSC_IOHCR_G7_IO3_Msk (0x1UL << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4_Pos (27U)
+#define TSC_IOHCR_G7_IO4_Msk (0x1UL << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1_Pos (28U)
+#define TSC_IOHCR_G8_IO1_Msk (0x1UL << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2_Pos (29U)
+#define TSC_IOHCR_G8_IO2_Msk (0x1UL << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3_Pos (30U)
+#define TSC_IOHCR_G8_IO3_Msk (0x1UL << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4_Pos (31U)
+#define TSC_IOHCR_G8_IO4_Msk (0x1UL << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+
+/******************* Bit definition for TSC_IOASCR register *****************/
+#define TSC_IOASCR_G1_IO1_Pos (0U)
+#define TSC_IOASCR_G1_IO1_Msk (0x1UL << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2_Pos (1U)
+#define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3_Pos (2U)
+#define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4_Pos (3U)
+#define TSC_IOASCR_G1_IO4_Msk (0x1UL << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1_Pos (4U)
+#define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2_Pos (5U)
+#define TSC_IOASCR_G2_IO2_Msk (0x1UL << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3_Pos (6U)
+#define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4_Pos (7U)
+#define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1_Pos (8U)
+#define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2_Pos (9U)
+#define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3_Pos (10U)
+#define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4_Pos (11U)
+#define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1_Pos (12U)
+#define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2_Pos (13U)
+#define TSC_IOASCR_G4_IO2_Msk (0x1UL << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3_Pos (14U)
+#define TSC_IOASCR_G4_IO3_Msk (0x1UL << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4_Pos (15U)
+#define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1_Pos (16U)
+#define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2_Pos (17U)
+#define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3_Pos (18U)
+#define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4_Pos (19U)
+#define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1_Pos (20U)
+#define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2_Pos (21U)
+#define TSC_IOASCR_G6_IO2_Msk (0x1UL << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3_Pos (22U)
+#define TSC_IOASCR_G6_IO3_Msk (0x1UL << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4_Pos (23U)
+#define TSC_IOASCR_G6_IO4_Msk (0x1UL << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1_Pos (24U)
+#define TSC_IOASCR_G7_IO1_Msk (0x1UL << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2_Pos (25U)
+#define TSC_IOASCR_G7_IO2_Msk (0x1UL << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3_Pos (26U)
+#define TSC_IOASCR_G7_IO3_Msk (0x1UL << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4_Pos (27U)
+#define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1_Pos (28U)
+#define TSC_IOASCR_G8_IO1_Msk (0x1UL << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2_Pos (29U)
+#define TSC_IOASCR_G8_IO2_Msk (0x1UL << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3_Pos (30U)
+#define TSC_IOASCR_G8_IO3_Msk (0x1UL << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4_Pos (31U)
+#define TSC_IOASCR_G8_IO4_Msk (0x1UL << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */
+
+/******************* Bit definition for TSC_IOSCR register ******************/
+#define TSC_IOSCR_G1_IO1_Pos (0U)
+#define TSC_IOSCR_G1_IO1_Msk (0x1UL << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2_Pos (1U)
+#define TSC_IOSCR_G1_IO2_Msk (0x1UL << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3_Pos (2U)
+#define TSC_IOSCR_G1_IO3_Msk (0x1UL << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4_Pos (3U)
+#define TSC_IOSCR_G1_IO4_Msk (0x1UL << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1_Pos (4U)
+#define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2_Pos (5U)
+#define TSC_IOSCR_G2_IO2_Msk (0x1UL << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3_Pos (6U)
+#define TSC_IOSCR_G2_IO3_Msk (0x1UL << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4_Pos (7U)
+#define TSC_IOSCR_G2_IO4_Msk (0x1UL << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1_Pos (8U)
+#define TSC_IOSCR_G3_IO1_Msk (0x1UL << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2_Pos (9U)
+#define TSC_IOSCR_G3_IO2_Msk (0x1UL << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3_Pos (10U)
+#define TSC_IOSCR_G3_IO3_Msk (0x1UL << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4_Pos (11U)
+#define TSC_IOSCR_G3_IO4_Msk (0x1UL << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1_Pos (12U)
+#define TSC_IOSCR_G4_IO1_Msk (0x1UL << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2_Pos (13U)
+#define TSC_IOSCR_G4_IO2_Msk (0x1UL << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3_Pos (14U)
+#define TSC_IOSCR_G4_IO3_Msk (0x1UL << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4_Pos (15U)
+#define TSC_IOSCR_G4_IO4_Msk (0x1UL << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1_Pos (16U)
+#define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2_Pos (17U)
+#define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3_Pos (18U)
+#define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4_Pos (19U)
+#define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1_Pos (20U)
+#define TSC_IOSCR_G6_IO1_Msk (0x1UL << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2_Pos (21U)
+#define TSC_IOSCR_G6_IO2_Msk (0x1UL << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3_Pos (22U)
+#define TSC_IOSCR_G6_IO3_Msk (0x1UL << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4_Pos (23U)
+#define TSC_IOSCR_G6_IO4_Msk (0x1UL << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1_Pos (24U)
+#define TSC_IOSCR_G7_IO1_Msk (0x1UL << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2_Pos (25U)
+#define TSC_IOSCR_G7_IO2_Msk (0x1UL << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3_Pos (26U)
+#define TSC_IOSCR_G7_IO3_Msk (0x1UL << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4_Pos (27U)
+#define TSC_IOSCR_G7_IO4_Msk (0x1UL << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1_Pos (28U)
+#define TSC_IOSCR_G8_IO1_Msk (0x1UL << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2_Pos (29U)
+#define TSC_IOSCR_G8_IO2_Msk (0x1UL << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3_Pos (30U)
+#define TSC_IOSCR_G8_IO3_Msk (0x1UL << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4_Pos (31U)
+#define TSC_IOSCR_G8_IO4_Msk (0x1UL << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */
+
+/******************* Bit definition for TSC_IOCCR register ******************/
+#define TSC_IOCCR_G1_IO1_Pos (0U)
+#define TSC_IOCCR_G1_IO1_Msk (0x1UL << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2_Pos (1U)
+#define TSC_IOCCR_G1_IO2_Msk (0x1UL << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3_Pos (2U)
+#define TSC_IOCCR_G1_IO3_Msk (0x1UL << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4_Pos (3U)
+#define TSC_IOCCR_G1_IO4_Msk (0x1UL << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1_Pos (4U)
+#define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2_Pos (5U)
+#define TSC_IOCCR_G2_IO2_Msk (0x1UL << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3_Pos (6U)
+#define TSC_IOCCR_G2_IO3_Msk (0x1UL << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4_Pos (7U)
+#define TSC_IOCCR_G2_IO4_Msk (0x1UL << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1_Pos (8U)
+#define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2_Pos (9U)
+#define TSC_IOCCR_G3_IO2_Msk (0x1UL << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3_Pos (10U)
+#define TSC_IOCCR_G3_IO3_Msk (0x1UL << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4_Pos (11U)
+#define TSC_IOCCR_G3_IO4_Msk (0x1UL << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1_Pos (12U)
+#define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2_Pos (13U)
+#define TSC_IOCCR_G4_IO2_Msk (0x1UL << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3_Pos (14U)
+#define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4_Pos (15U)
+#define TSC_IOCCR_G4_IO4_Msk (0x1UL << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1_Pos (16U)
+#define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2_Pos (17U)
+#define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3_Pos (18U)
+#define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4_Pos (19U)
+#define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1_Pos (20U)
+#define TSC_IOCCR_G6_IO1_Msk (0x1UL << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2_Pos (21U)
+#define TSC_IOCCR_G6_IO2_Msk (0x1UL << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3_Pos (22U)
+#define TSC_IOCCR_G6_IO3_Msk (0x1UL << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4_Pos (23U)
+#define TSC_IOCCR_G6_IO4_Msk (0x1UL << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1_Pos (24U)
+#define TSC_IOCCR_G7_IO1_Msk (0x1UL << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2_Pos (25U)
+#define TSC_IOCCR_G7_IO2_Msk (0x1UL << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3_Pos (26U)
+#define TSC_IOCCR_G7_IO3_Msk (0x1UL << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4_Pos (27U)
+#define TSC_IOCCR_G7_IO4_Msk (0x1UL << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1_Pos (28U)
+#define TSC_IOCCR_G8_IO1_Msk (0x1UL << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2_Pos (29U)
+#define TSC_IOCCR_G8_IO2_Msk (0x1UL << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3_Pos (30U)
+#define TSC_IOCCR_G8_IO3_Msk (0x1UL << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4_Pos (31U)
+#define TSC_IOCCR_G8_IO4_Msk (0x1UL << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */
+
+/******************* Bit definition for TSC_IOGCSR register *****************/
+#define TSC_IOGCSR_G1E_Pos (0U)
+#define TSC_IOGCSR_G1E_Msk (0x1UL << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
+#define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E_Pos (1U)
+#define TSC_IOGCSR_G2E_Msk (0x1UL << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
+#define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E_Pos (2U)
+#define TSC_IOGCSR_G3E_Msk (0x1UL << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
+#define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E_Pos (3U)
+#define TSC_IOGCSR_G4E_Msk (0x1UL << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
+#define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E_Pos (4U)
+#define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
+#define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E_Pos (5U)
+#define TSC_IOGCSR_G6E_Msk (0x1UL << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
+#define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E_Pos (6U)
+#define TSC_IOGCSR_G7E_Msk (0x1UL << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
+#define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E_Pos (7U)
+#define TSC_IOGCSR_G8E_Msk (0x1UL << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */
+#define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S_Pos (16U)
+#define TSC_IOGCSR_G1S_Msk (0x1UL << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
+#define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S_Pos (17U)
+#define TSC_IOGCSR_G2S_Msk (0x1UL << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
+#define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S_Pos (18U)
+#define TSC_IOGCSR_G3S_Msk (0x1UL << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
+#define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S_Pos (19U)
+#define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
+#define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S_Pos (20U)
+#define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
+#define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S_Pos (21U)
+#define TSC_IOGCSR_G6S_Msk (0x1UL << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
+#define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S_Pos (22U)
+#define TSC_IOGCSR_G7S_Msk (0x1UL << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
+#define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S_Pos (23U)
+#define TSC_IOGCSR_G8S_Msk (0x1UL << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */
+#define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */
+
+/******************* Bit definition for TSC_IOGXCR register *****************/
+#define TSC_IOGXCR_CNT_Pos (0U)
+#define TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
+#define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE_Pos (0U)
+#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+#define USART_CR1_UESM_Pos (1U)
+#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
+#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_M0_Pos (12U)
+#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
+#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos (13U)
+#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos (14U)
+#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos (16U)
+#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
+#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
+#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
+#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
+#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos (21U)
+#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
+#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
+#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
+#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
+#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos (26U)
+#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos (27U)
+#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos (28U)
+#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
+#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7_Pos (4U)
+#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos (15U)
+#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos (16U)
+#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos (17U)
+#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos (18U)
+#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos (19U)
+#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos (20U)
+#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos (21U)
+#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos (23U)
+#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos (24U)
+#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos (12U)
+#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos (13U)
+#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos (14U)
+#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos (15U)
+#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos (17U)
+#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos (20U)
+#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
+#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
+#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos (22U)
+#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
+#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
+#define USART_CR3_UCESM_Pos (23U)
+#define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
+#define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION_Pos (0U)
+#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos (4U)
+#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO_Pos (0U)
+#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos (24U)
+#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ_Pos (0U)
+#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
+#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos (1U)
+#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
+#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos (2U)
+#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
+#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos (3U)
+#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
+#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos (4U)
+#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
+#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE_Pos (0U)
+#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
+#define USART_ISR_FE_Pos (1U)
+#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
+#define USART_ISR_NE_Pos (2U)
+#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos (3U)
+#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos (4U)
+#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos (5U)
+#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos (6U)
+#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos (7U)
+#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
+#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos (8U)
+#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos (9U)
+#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos (10U)
+#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
+#define USART_ISR_RTOF_Pos (11U)
+#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos (12U)
+#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos (14U)
+#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos (15U)
+#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos (16U)
+#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
+#define USART_ISR_CMF_Pos (17U)
+#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos (18U)
+#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos (19U)
+#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos (20U)
+#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
+#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos (21U)
+#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos (22U)
+#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
+#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF_Pos (0U)
+#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos (1U)
+#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos (2U)
+#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */
+#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos (3U)
+#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos (4U)
+#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos (6U)
+#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF_Pos (8U)
+#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos (9U)
+#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos (11U)
+#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos (12U)
+#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos (17U)
+#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos (20U)
+#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
+#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
+
+/* Compatibility defines with other series */
+#define USART_ICR_NECF USART_ICR_NCF
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR_Pos (0U)
+#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR_Pos (0U)
+#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* USB Device General registers */
+/* */
+/******************************************************************************/
+#define USB_BASE (0x40005C00U) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR_Pos (13U)
+#define USB_PMAADDR_Msk (0x20003UL << USB_PMAADDR_Pos) /*!< 0x40006000 */
+#define USB_PMAADDR USB_PMAADDR_Msk /*!< USB_IP Packet Memory Area base address */
+
+#define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
+#define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
+#define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
+#define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
+#define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
+#define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
+#define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
+
+/**************************** ISTR interrupt events *************************/
+#define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
+#define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
+#define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
+#define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
+#define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
+#define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
+#define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
+#define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
+#define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
+
+#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
+#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
+#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
+#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
+#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
+#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
+#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
+#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
+#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
+/************************* CNTR control register bits definitions ***********/
+#define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
+#define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
+#define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
+#define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
+#define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
+#define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
+#define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
+#define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
+#define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
+#define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
+#define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
+#define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
+#define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
+#define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
+/************************* BCDR control register bits definitions ***********/
+#define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
+#define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
+#define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
+#define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
+#define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
+#define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
+#define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
+#define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
+#define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
+/*************************** LPM register bits definitions ******************/
+#define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
+#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
+#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
+/******************** FNR Frame Number Register bit definitions ************/
+#define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
+#define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
+#define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
+#define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
+#define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
+/******************** DADDR Device ADDRess bit definitions ****************/
+#define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */
+#define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */
+/****************************** Endpoint register *************************/
+#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
+#define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
+#define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
+#define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
+#define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
+#define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
+#define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
+#define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
+/* bit positions */
+#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
+#define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
+#define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
+#define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
+#define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+ /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
+#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+/******************************* COMP Instances *******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+ ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances *********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOH))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
+
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SMBUS Instances *****************************/
+#define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/************* LPTIM instances supporting the encoder mode feature ************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM6))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM21) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM22) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/******************* TIM Instances : output(s) OCXEC register *****************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** USART Instances : Auto Baud Rate detection ****************/
+
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/******************************* USB Instances *******************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** LCD Instances ********************************/
+#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32L0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32L0 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+
+#define LPUART1_IRQn RNG_LPUART1_IRQn
+#define AES_LPUART1_IRQn RNG_LPUART1_IRQn
+#define AES_RNG_LPUART1_IRQn RNG_LPUART1_IRQn
+#define TIM6_IRQn TIM6_DAC_IRQn
+#define RCC_IRQn RCC_CRS_IRQn
+#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
+#define ADC1_IRQn ADC1_COMP_IRQn
+
+/* Aliases for __IRQHandler */
+#define LPUART1_IRQHandler RNG_LPUART1_IRQHandler
+#define AES_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
+#define AES_RNG_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
+#define TIM6_IRQHandler TIM6_DAC_IRQHandler
+#define RCC_IRQHandler RCC_CRS_IRQHandler
+#define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
+#define ADC1_IRQHandler ADC1_COMP_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L053xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/CMSIS/device/stm32l061xx.h b/CMSIS/device/stm32l061xx.h
new file mode 100644
index 0000000..36cb96c
--- /dev/null
+++ b/CMSIS/device/stm32l061xx.h
@@ -0,0 +1,6405 @@
+/**
+ ******************************************************************************
+ * @file stm32l061xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for stm32l061xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright(c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l061xx
+ * @{
+ */
+
+#ifndef __STM32L061xx_H
+#define __STM32L061xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 1U /*!< STM32L0xx provides an MPU */
+#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
+#define __NVIC_PRIO_BITS 2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief stm32l061xx Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+/*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
+
+/****** STM32L-0 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */
+ RCC_IRQn = 4, /*!< RCC Interrupt */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
+ ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
+ LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 Interrupt */
+ TIM6_IRQn = 17, /*!< TIM6 Interrupt */
+ TIM21_IRQn = 20, /*!< TIM21 Interrupt */
+ TIM22_IRQn = 22, /*!< TIM22 Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */
+ I2C2_IRQn = 24, /*!< I2C2 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ SPI2_IRQn = 26, /*!< SPI2 Interrupt */
+ USART1_IRQn = 27, /*!< USART1 Interrupt */
+ USART2_IRQn = 28, /*!< USART2 Interrupt */
+ AES_LPUART1_IRQn = 29, /*!< AES and LPUART1 Interrupts */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0plus.h"
+#include "system_stm32l0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+ uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+} ADC_Common_TypeDef;
+
+/**
+ * @brief AES hardware accelerator
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
+ __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
+ __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
+ __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
+ __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
+ __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
+ __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
+ __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
+ __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
+ __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
+ __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
+} AES_TypeDef;
+
+/**
+ * @brief Comparator
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
+} COMP_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+
+/**
+* @brief CRC calculation unit
+*/
+
+typedef struct
+{
+__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+uint8_t RESERVED0; /*!< Reserved, 0x05 */
+uint16_t RESERVED1; /*!< Reserved, 0x06 */
+__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+uint32_t RESERVED2; /*!< Reserved, 0x0C */
+__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
+} DMA_Request_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
+ __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
+ __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
+ __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
+ __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
+ __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
+ __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
+ __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
+ __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
+ __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
+} OB_TypeDef;
+
+
+/**
+ * @brief General Purpose IO
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief LPTIMIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+} LPTIM_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+ * @brief Independent WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief MIFARE Firewall
+ */
+typedef struct
+{
+ __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
+ __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
+ __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
+ __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
+ __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
+ __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
+ __IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x18 */
+ __IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */
+ __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
+
+} FIREWALL_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
+ __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
+ __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
+ __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
+ __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
+ __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
+ __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
+ __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
+ __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
+ __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
+ __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */
+
+#define DATA_EEPROM_BASE (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
+#define DATA_EEPROM_END (0x080807FFUL) /*!< DATA EEPROM end address in the alias region */
+#define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */
+#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8KBytes) */
+
+#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000UL)
+
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL)
+#define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
+#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
+#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800UL)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
+#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
+#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL)
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
+#define COMP1_BASE (APBPERIPH_BASE + 0x00010018UL)
+#define COMP2_BASE (APBPERIPH_BASE + 0x0001001CUL)
+#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL)
+#define TIM21_BASE (APBPERIPH_BASE + 0x00010800UL)
+#define TIM22_BASE (APBPERIPH_BASE + 0x00011400UL)
+#define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00UL)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708UL)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
+#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
+#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL)
+
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
+#define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */
+#define FLASHSIZE_BASE (0x1FF8007CUL) /*!< FLASH Size register base address */
+#define UID_BASE (0x1FF80050UL) /*!< Unique device ID register base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
+#define AES_BASE (AHBPERIPH_BASE + 0x00006000UL)
+
+#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL)
+#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL)
+#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL)
+#define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00UL)
+#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00UL)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
+#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
+#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
+/* Legacy defines */
+#define ADC ADC1_COMMON
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define AES ((AES_TypeDef *) AES_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_EOCAL_Pos (11U)
+#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
+#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
+#define ADC_ISR_AWD_Pos (7U)
+#define ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
+#define ADC_ISR_EOSEQ_Pos (3U)
+#define ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_EOCALIE_Pos (11U)
+#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
+#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
+#define ADC_IER_AWDIE_Pos (7U)
+#define ADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE_Pos (3U)
+#define ADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH_Pos (26U)
+#define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
+#define ADC_CFGR1_AWDEN_Pos (23U)
+#define ADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL_Pos (22U)
+#define ADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN_Pos (16U)
+#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF_Pos (15U)
+#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
+#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT_Pos (14U)
+#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
+#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT_Pos (13U)
+#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD_Pos (12U)
+#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN_Pos (10U)
+#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
+#define ADC_CFGR1_EXTSEL_Pos (6U)
+#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
+#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
+#define ADC_CFGR1_ALIGN_Pos (5U)
+#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
+#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
+#define ADC_CFGR1_RES_Pos (3U)
+#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
+#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
+#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
+#define ADC_CFGR1_SCANDIR_Pos (2U)
+#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG_Pos (1U)
+#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
+#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN_Pos (0U)
+#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
+#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_TOVS_Pos (9U)
+#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
+#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+#define ADC_CFGR2_OVSR_Pos (2U)
+#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
+#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+#define ADC_CFGR2_OVSE_Pos (0U)
+#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
+#define ADC_CFGR2_CKMODE_Pos (30U)
+#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
+#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
+#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
+#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
+
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP_Pos (0U)
+#define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
+#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
+#define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
+#define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define ADC_SMPR_SMPR ADC_SMPR_SMP
+#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
+#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
+#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT_Pos (16U)
+#define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
+#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
+#define ADC_TR_LT_Pos (0U)
+#define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL_Pos (0U)
+#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
+#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
+#define ADC_CHSELR_CHSEL18_Pos (18U)
+#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17_Pos (17U)
+#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
+#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL15_Pos (15U)
+#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
+#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14_Pos (14U)
+#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
+#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13_Pos (13U)
+#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
+#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12_Pos (12U)
+#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
+#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11_Pos (11U)
+#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
+#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10_Pos (10U)
+#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
+#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9_Pos (9U)
+#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
+#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8_Pos (8U)
+#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
+#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7_Pos (7U)
+#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
+#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6_Pos (6U)
+#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
+#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5_Pos (5U)
+#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
+#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4_Pos (4U)
+#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
+#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3_Pos (3U)
+#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
+#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2_Pos (2U)
+#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
+#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1_Pos (1U)
+#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
+#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0_Pos (0U)
+#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
+#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_CALFACT_Pos (0U)
+#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_LFMEN_Pos (25U)
+#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
+#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
+#define ADC_CCR_TSEN_Pos (23U)
+#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+/******************************************************************************/
+/* */
+/* Advanced Encryption Standard (AES) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for AES_CR register *********************/
+#define AES_CR_EN_Pos (0U)
+#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */
+#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */
+#define AES_CR_DATATYPE_Pos (1U)
+#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */
+#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */
+#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */
+#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */
+
+#define AES_CR_MODE_Pos (3U)
+#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */
+#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */
+#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */
+#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */
+
+#define AES_CR_CHMOD_Pos (5U)
+#define AES_CR_CHMOD_Msk (0x3UL << AES_CR_CHMOD_Pos) /*!< 0x00000060 */
+#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */
+#define AES_CR_CHMOD_0 (0x1UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */
+#define AES_CR_CHMOD_1 (0x2UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */
+
+#define AES_CR_CCFC_Pos (7U)
+#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */
+#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */
+#define AES_CR_ERRC_Pos (8U)
+#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */
+#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */
+#define AES_CR_CCIE_Pos (9U)
+#define AES_CR_CCIE_Msk (0x1UL << AES_CR_CCIE_Pos) /*!< 0x00000200 */
+#define AES_CR_CCIE AES_CR_CCIE_Msk /*!< Computation Complete Interrupt Enable */
+#define AES_CR_ERRIE_Pos (10U)
+#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */
+#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */
+#define AES_CR_DMAINEN_Pos (11U)
+#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */
+#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< DMA ENable managing the data input phase */
+#define AES_CR_DMAOUTEN_Pos (12U)
+#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */
+#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< DMA Enable managing the data output phase */
+
+/******************* Bit definition for AES_SR register *********************/
+#define AES_SR_CCF_Pos (0U)
+#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */
+#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */
+#define AES_SR_RDERR_Pos (1U)
+#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */
+#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */
+#define AES_SR_WRERR_Pos (2U)
+#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */
+#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */
+
+/******************* Bit definition for AES_DINR register *******************/
+#define AES_DINR_Pos (0U)
+#define AES_DINR_Msk (0xFFFFUL << AES_DINR_Pos) /*!< 0x0000FFFF */
+#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */
+
+/******************* Bit definition for AES_DOUTR register ******************/
+#define AES_DOUTR_Pos (0U)
+#define AES_DOUTR_Msk (0xFFFFUL << AES_DOUTR_Pos) /*!< 0x0000FFFF */
+#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */
+
+/******************* Bit definition for AES_KEYR0 register ******************/
+#define AES_KEYR0_Pos (0U)
+#define AES_KEYR0_Msk (0xFFFFUL << AES_KEYR0_Pos) /*!< 0x0000FFFF */
+#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */
+
+/******************* Bit definition for AES_KEYR1 register ******************/
+#define AES_KEYR1_Pos (0U)
+#define AES_KEYR1_Msk (0xFFFFUL << AES_KEYR1_Pos) /*!< 0x0000FFFF */
+#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */
+
+/******************* Bit definition for AES_KEYR2 register ******************/
+#define AES_KEYR2_Pos (0U)
+#define AES_KEYR2_Msk (0xFFFFUL << AES_KEYR2_Pos) /*!< 0x0000FFFF */
+#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */
+
+/******************* Bit definition for AES_KEYR3 register ******************/
+#define AES_KEYR3_Pos (0U)
+#define AES_KEYR3_Msk (0xFFFFUL << AES_KEYR3_Pos) /*!< 0x0000FFFF */
+#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */
+
+/******************* Bit definition for AES_IVR0 register *******************/
+#define AES_IVR0_Pos (0U)
+#define AES_IVR0_Msk (0xFFFFUL << AES_IVR0_Pos) /*!< 0x0000FFFF */
+#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */
+
+/******************* Bit definition for AES_IVR1 register *******************/
+#define AES_IVR1_Pos (0U)
+#define AES_IVR1_Msk (0xFFFFUL << AES_IVR1_Pos) /*!< 0x0000FFFF */
+#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */
+
+/******************* Bit definition for AES_IVR2 register *******************/
+#define AES_IVR2_Pos (0U)
+#define AES_IVR2_Msk (0xFFFFUL << AES_IVR2_Pos) /*!< 0x0000FFFF */
+#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */
+
+/******************* Bit definition for AES_IVR3 register *******************/
+#define AES_IVR3_Pos (0U)
+#define AES_IVR3_Msk (0xFFFFUL << AES_IVR3_Pos) /*!< 0x0000FFFF */
+#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+/************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN_Pos (0U)
+#define COMP_CSR_COMP1EN_Msk (0x1UL << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
+#define COMP_CSR_COMP1INNSEL_Pos (4U)
+#define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
+#define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP1WM_Pos (8U)
+#define COMP_CSR_COMP1WM_Msk (0x1UL << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */
+#define COMP_CSR_COMP1LPTIM1IN1_Pos (12U)
+#define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP1POLARITY_Pos (15U)
+#define COMP_CSR_COMP1POLARITY_Msk (0x1UL << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1VALUE_Pos (30U)
+#define COMP_CSR_COMP1VALUE_Msk (0x1UL << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK_Pos (31U)
+#define COMP_CSR_COMP1LOCK_Msk (0x1UL << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN_Pos (0U)
+#define COMP_CSR_COMP2EN_Msk (0x1UL << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
+#define COMP_CSR_COMP2SPEED_Pos (3U)
+#define COMP_CSR_COMP2SPEED_Msk (0x1UL << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */
+#define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */
+#define COMP_CSR_COMP2INNSEL_Pos (4U)
+#define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */
+#define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
+#define COMP_CSR_COMP2INPSEL_Pos (8U)
+#define COMP_CSR_COMP2INPSEL_Msk (0x7UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */
+#define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2INPSEL_0 (0x1UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP2INPSEL_1 (0x2UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */
+#define COMP_CSR_COMP2INPSEL_2 (0x4UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */
+#define COMP_CSR_COMP2LPTIM1IN2_Pos (12U)
+#define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */
+#define COMP_CSR_COMP2LPTIM1IN1_Pos (13U)
+#define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */
+#define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP2POLARITY_Pos (15U)
+#define COMP_CSR_COMP2POLARITY_Msk (0x1UL << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2VALUE_Pos (30U)
+#define COMP_CSR_COMP2VALUE_Msk (0x1UL << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK_Pos (31U)
+#define COMP_CSR_COMP2LOCK_Msk (0x1UL << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
+
+/********************** Bit definition for COMP_CSR register common ****************/
+#define COMP_CSR_COMPxEN_Pos (0U)
+#define COMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
+#define COMP_CSR_COMPxPOLARITY_Pos (15U)
+#define COMP_CSR_COMPxPOLARITY_Msk (0x1UL << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */
+#define COMP_CSR_COMPxOUTVALUE_Pos (30U)
+#define COMP_CSR_COMPxOUTVALUE_Msk (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK_Pos (31U)
+#define COMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
+
+/* Reference defines */
+#define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR (0xFFU) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos (3U)
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos (5U)
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos (7U)
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT_Pos (0U)
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL_Pos (0U)
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_Pos (0U)
+#define DBGMCU_CR_DBG_Msk (0x7UL << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
+#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+
+/******************* Bit definition for DMA_CSELR register *******************/
+#define DMA_CSELR_C1S_Pos (0U)
+#define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
+#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos (4U)
+#define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
+#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos (8U)
+#define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
+#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos (12U)
+#define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
+#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos (16U)
+#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
+#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S_Pos (20U)
+#define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
+#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S_Pos (24U)
+#define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
+#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_IM0_Pos (0U)
+#define EXTI_IMR_IM0_Msk (0x1UL << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_IM1_Pos (1U)
+#define EXTI_IMR_IM1_Msk (0x1UL << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_IM2_Pos (2U)
+#define EXTI_IMR_IM2_Msk (0x1UL << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_IM3_Pos (3U)
+#define EXTI_IMR_IM3_Msk (0x1UL << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_IM4_Pos (4U)
+#define EXTI_IMR_IM4_Msk (0x1UL << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_IM5_Pos (5U)
+#define EXTI_IMR_IM5_Msk (0x1UL << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_IM6_Pos (6U)
+#define EXTI_IMR_IM6_Msk (0x1UL << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_IM7_Pos (7U)
+#define EXTI_IMR_IM7_Msk (0x1UL << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_IM8_Pos (8U)
+#define EXTI_IMR_IM8_Msk (0x1UL << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_IM9_Pos (9U)
+#define EXTI_IMR_IM9_Msk (0x1UL << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_IM10_Pos (10U)
+#define EXTI_IMR_IM10_Msk (0x1UL << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_IM11_Pos (11U)
+#define EXTI_IMR_IM11_Msk (0x1UL << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_IM12_Pos (12U)
+#define EXTI_IMR_IM12_Msk (0x1UL << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_IM13_Pos (13U)
+#define EXTI_IMR_IM13_Msk (0x1UL << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_IM14_Pos (14U)
+#define EXTI_IMR_IM14_Msk (0x1UL << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_IM15_Pos (15U)
+#define EXTI_IMR_IM15_Msk (0x1UL << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_IM16_Pos (16U)
+#define EXTI_IMR_IM16_Msk (0x1UL << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_IM17_Pos (17U)
+#define EXTI_IMR_IM17_Msk (0x1UL << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_IM18_Pos (18U)
+#define EXTI_IMR_IM18_Msk (0x1UL << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_IM19_Pos (19U)
+#define EXTI_IMR_IM19_Msk (0x1UL << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_IM20_Pos (20U)
+#define EXTI_IMR_IM20_Msk (0x1UL << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_IM21_Pos (21U)
+#define EXTI_IMR_IM21_Msk (0x1UL << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_IM22_Pos (22U)
+#define EXTI_IMR_IM22_Msk (0x1UL << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_IM23_Pos (23U)
+#define EXTI_IMR_IM23_Msk (0x1UL << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
+#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_IM25_Pos (25U)
+#define EXTI_IMR_IM25_Msk (0x1UL << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */
+#define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_IM26_Pos (26U)
+#define EXTI_IMR_IM26_Msk (0x1UL << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
+#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_IM28_Pos (28U)
+#define EXTI_IMR_IM28_Msk (0x1UL << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
+#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_IM29_Pos (29U)
+#define EXTI_IMR_IM29_Msk (0x1UL << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
+#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
+
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x36FFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x36FFFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_EM0_Pos (0U)
+#define EXTI_EMR_EM0_Msk (0x1UL << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_EM1_Pos (1U)
+#define EXTI_EMR_EM1_Msk (0x1UL << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_EM2_Pos (2U)
+#define EXTI_EMR_EM2_Msk (0x1UL << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_EM3_Pos (3U)
+#define EXTI_EMR_EM3_Msk (0x1UL << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_EM4_Pos (4U)
+#define EXTI_EMR_EM4_Msk (0x1UL << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_EM5_Pos (5U)
+#define EXTI_EMR_EM5_Msk (0x1UL << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_EM6_Pos (6U)
+#define EXTI_EMR_EM6_Msk (0x1UL << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_EM7_Pos (7U)
+#define EXTI_EMR_EM7_Msk (0x1UL << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_EM8_Pos (8U)
+#define EXTI_EMR_EM8_Msk (0x1UL << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_EM9_Pos (9U)
+#define EXTI_EMR_EM9_Msk (0x1UL << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_EM10_Pos (10U)
+#define EXTI_EMR_EM10_Msk (0x1UL << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_EM11_Pos (11U)
+#define EXTI_EMR_EM11_Msk (0x1UL << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_EM12_Pos (12U)
+#define EXTI_EMR_EM12_Msk (0x1UL << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_EM13_Pos (13U)
+#define EXTI_EMR_EM13_Msk (0x1UL << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_EM14_Pos (14U)
+#define EXTI_EMR_EM14_Msk (0x1UL << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_EM15_Pos (15U)
+#define EXTI_EMR_EM15_Msk (0x1UL << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_EM16_Pos (16U)
+#define EXTI_EMR_EM16_Msk (0x1UL << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_EM17_Pos (17U)
+#define EXTI_EMR_EM17_Msk (0x1UL << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_EM18_Pos (18U)
+#define EXTI_EMR_EM18_Msk (0x1UL << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_EM19_Pos (19U)
+#define EXTI_EMR_EM19_Msk (0x1UL << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_EM20_Pos (20U)
+#define EXTI_EMR_EM20_Msk (0x1UL << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_EM21_Pos (21U)
+#define EXTI_EMR_EM21_Msk (0x1UL << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_EM22_Pos (22U)
+#define EXTI_EMR_EM22_Msk (0x1UL << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */
+#define EXTI_EMR_EM23_Pos (23U)
+#define EXTI_EMR_EM23_Msk (0x1UL << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
+#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
+#define EXTI_EMR_EM25_Pos (25U)
+#define EXTI_EMR_EM25_Msk (0x1UL << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */
+#define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */
+#define EXTI_EMR_EM26_Pos (26U)
+#define EXTI_EMR_EM26_Msk (0x1UL << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
+#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
+#define EXTI_EMR_EM28_Pos (28U)
+#define EXTI_EMR_EM28_Msk (0x1UL << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
+#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
+#define EXTI_EMR_EM29_Pos (29U)
+#define EXTI_EMR_EM29_Msk (0x1UL << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
+#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_RT0_Pos (0U)
+#define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_RT1_Pos (1U)
+#define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_RT2_Pos (2U)
+#define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_RT3_Pos (3U)
+#define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_RT4_Pos (4U)
+#define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_RT5_Pos (5U)
+#define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_RT6_Pos (6U)
+#define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_RT7_Pos (7U)
+#define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_RT8_Pos (8U)
+#define EXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_RT9_Pos (9U)
+#define EXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_RT10_Pos (10U)
+#define EXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_RT11_Pos (11U)
+#define EXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_RT12_Pos (12U)
+#define EXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_RT13_Pos (13U)
+#define EXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_RT14_Pos (14U)
+#define EXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_RT15_Pos (15U)
+#define EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_RT16_Pos (16U)
+#define EXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_RT17_Pos (17U)
+#define EXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_RT19_Pos (19U)
+#define EXTI_RTSR_RT19_Msk (0x1UL << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_RT20_Pos (20U)
+#define EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_RT21_Pos (21U)
+#define EXTI_RTSR_RT21_Msk (0x1UL << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_RT22_Pos (22U)
+#define EXTI_RTSR_RT22_Msk (0x1UL << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
+#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
+#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
+#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
+#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
+#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
+#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
+#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
+#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
+#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
+#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
+#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
+#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
+#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
+#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
+#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
+#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
+#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
+#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
+#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
+#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
+#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_FT0_Pos (0U)
+#define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_FT1_Pos (1U)
+#define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_FT2_Pos (2U)
+#define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_FT3_Pos (3U)
+#define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_FT4_Pos (4U)
+#define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_FT5_Pos (5U)
+#define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_FT6_Pos (6U)
+#define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_FT7_Pos (7U)
+#define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_FT8_Pos (8U)
+#define EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_FT9_Pos (9U)
+#define EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_FT10_Pos (10U)
+#define EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_FT11_Pos (11U)
+#define EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_FT12_Pos (12U)
+#define EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_FT13_Pos (13U)
+#define EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_FT14_Pos (14U)
+#define EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_FT15_Pos (15U)
+#define EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_FT16_Pos (16U)
+#define EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_FT17_Pos (17U)
+#define EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_FT19_Pos (19U)
+#define EXTI_FTSR_FT19_Msk (0x1UL << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_FT20_Pos (20U)
+#define EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_FT21_Pos (21U)
+#define EXTI_FTSR_FT21_Msk (0x1UL << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_FT22_Pos (22U)
+#define EXTI_FTSR_FT22_Msk (0x1UL << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
+#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
+#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
+#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
+#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
+#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
+#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
+#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
+#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
+#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
+#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
+#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
+#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
+#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
+#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
+#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
+#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
+#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
+#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
+#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
+#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
+#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWI0_Pos (0U)
+#define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWI1_Pos (1U)
+#define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWI2_Pos (2U)
+#define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWI3_Pos (3U)
+#define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWI4_Pos (4U)
+#define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWI5_Pos (5U)
+#define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWI6_Pos (6U)
+#define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWI7_Pos (7U)
+#define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWI8_Pos (8U)
+#define EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWI9_Pos (9U)
+#define EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWI10_Pos (10U)
+#define EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWI11_Pos (11U)
+#define EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWI12_Pos (12U)
+#define EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWI13_Pos (13U)
+#define EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWI14_Pos (14U)
+#define EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWI15_Pos (15U)
+#define EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWI16_Pos (16U)
+#define EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWI17_Pos (17U)
+#define EXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWI19_Pos (19U)
+#define EXTI_SWIER_SWI19_Msk (0x1UL << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWI20_Pos (20U)
+#define EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWI21_Pos (21U)
+#define EXTI_SWIER_SWI21_Msk (0x1UL << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWI22_Pos (22U)
+#define EXTI_SWIER_SWI22_Msk (0x1UL << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
+
+/* Legacy defines */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PIF0_Pos (0U)
+#define EXTI_PR_PIF0_Msk (0x1UL << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
+#define EXTI_PR_PIF1_Pos (1U)
+#define EXTI_PR_PIF1_Msk (0x1UL << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
+#define EXTI_PR_PIF2_Pos (2U)
+#define EXTI_PR_PIF2_Msk (0x1UL << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
+#define EXTI_PR_PIF3_Pos (3U)
+#define EXTI_PR_PIF3_Msk (0x1UL << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
+#define EXTI_PR_PIF4_Pos (4U)
+#define EXTI_PR_PIF4_Msk (0x1UL << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
+#define EXTI_PR_PIF5_Pos (5U)
+#define EXTI_PR_PIF5_Msk (0x1UL << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
+#define EXTI_PR_PIF6_Pos (6U)
+#define EXTI_PR_PIF6_Msk (0x1UL << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
+#define EXTI_PR_PIF7_Pos (7U)
+#define EXTI_PR_PIF7_Msk (0x1UL << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
+#define EXTI_PR_PIF8_Pos (8U)
+#define EXTI_PR_PIF8_Msk (0x1UL << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
+#define EXTI_PR_PIF9_Pos (9U)
+#define EXTI_PR_PIF9_Msk (0x1UL << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
+#define EXTI_PR_PIF10_Pos (10U)
+#define EXTI_PR_PIF10_Msk (0x1UL << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
+#define EXTI_PR_PIF11_Pos (11U)
+#define EXTI_PR_PIF11_Msk (0x1UL << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
+#define EXTI_PR_PIF12_Pos (12U)
+#define EXTI_PR_PIF12_Msk (0x1UL << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
+#define EXTI_PR_PIF13_Pos (13U)
+#define EXTI_PR_PIF13_Msk (0x1UL << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
+#define EXTI_PR_PIF14_Pos (14U)
+#define EXTI_PR_PIF14_Msk (0x1UL << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
+#define EXTI_PR_PIF15_Pos (15U)
+#define EXTI_PR_PIF15_Msk (0x1UL << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
+#define EXTI_PR_PIF16_Pos (16U)
+#define EXTI_PR_PIF16_Msk (0x1UL << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
+#define EXTI_PR_PIF17_Pos (17U)
+#define EXTI_PR_PIF17_Msk (0x1UL << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
+#define EXTI_PR_PIF19_Pos (19U)
+#define EXTI_PR_PIF19_Msk (0x1UL << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
+#define EXTI_PR_PIF20_Pos (20U)
+#define EXTI_PR_PIF20_Msk (0x1UL << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
+#define EXTI_PR_PIF21_Pos (21U)
+#define EXTI_PR_PIF21_Msk (0x1UL << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
+#define EXTI_PR_PIF22_Pos (22U)
+#define EXTI_PR_PIF22_Msk (0x1UL << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
+
+/* Legacy defines */
+#define EXTI_PR_PR0 EXTI_PR_PIF0
+#define EXTI_PR_PR1 EXTI_PR_PIF1
+#define EXTI_PR_PR2 EXTI_PR_PIF2
+#define EXTI_PR_PR3 EXTI_PR_PIF3
+#define EXTI_PR_PR4 EXTI_PR_PIF4
+#define EXTI_PR_PR5 EXTI_PR_PIF5
+#define EXTI_PR_PR6 EXTI_PR_PIF6
+#define EXTI_PR_PR7 EXTI_PR_PIF7
+#define EXTI_PR_PR8 EXTI_PR_PIF8
+#define EXTI_PR_PR9 EXTI_PR_PIF9
+#define EXTI_PR_PR10 EXTI_PR_PIF10
+#define EXTI_PR_PR11 EXTI_PR_PIF11
+#define EXTI_PR_PR12 EXTI_PR_PIF12
+#define EXTI_PR_PR13 EXTI_PR_PIF13
+#define EXTI_PR_PR14 EXTI_PR_PIF14
+#define EXTI_PR_PR15 EXTI_PR_PIF15
+#define EXTI_PR_PR16 EXTI_PR_PIF16
+#define EXTI_PR_PR17 EXTI_PR_PIF17
+#define EXTI_PR_PR19 EXTI_PR_PIF19
+#define EXTI_PR_PR20 EXTI_PR_PIF20
+#define EXTI_PR_PR21 EXTI_PR_PIF21
+#define EXTI_PR_PR22 EXTI_PR_PIF22
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
+#define FLASH_ACR_PRFTEN_Pos (1U)
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_SLEEP_PD_Pos (3U)
+#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD_Pos (4U)
+#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
+#define FLASH_ACR_DISAB_BUF_Pos (5U)
+#define FLASH_ACR_DISAB_BUF_Msk (0x1UL << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
+#define FLASH_ACR_PRE_READ_Pos (6U)
+#define FLASH_ACR_PRE_READ_Msk (0x1UL << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
+#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
+
+/******************* Bit definition for FLASH_PECR register ******************/
+#define FLASH_PECR_PELOCK_Pos (0U)
+#define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
+#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK_Pos (1U)
+#define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
+#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK_Pos (2U)
+#define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
+#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG_Pos (3U)
+#define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
+#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
+#define FLASH_PECR_DATA_Pos (4U)
+#define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
+#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
+#define FLASH_PECR_FIX_Pos (8U)
+#define FLASH_PECR_FIX_Msk (0x1UL << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
+#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE_Pos (9U)
+#define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
+#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
+#define FLASH_PECR_FPRG_Pos (10U)
+#define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
+#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_EOPIE_Pos (16U)
+#define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
+#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
+#define FLASH_PECR_ERRIE_Pos (17U)
+#define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
+#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
+#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
+#define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
+#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
+#define FLASH_PECR_HALF_ARRAY_Pos (19U)
+#define FLASH_PECR_HALF_ARRAY_Msk (0x1UL << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
+#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
+
+/****************** Bit definition for FLASH_PDKEYR register ******************/
+#define FLASH_PDKEYR_PDKEYR_Pos (0U)
+#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PEKEYR register ******************/
+#define FLASH_PEKEYR_PEKEYR_Pos (0U)
+#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PRGKEYR register ******************/
+#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
+#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
+
+/****************** Bit definition for FLASH_OPTKEYR register ******************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_EOP_Pos (1U)
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
+#define FLASH_SR_HVOFF_Pos (2U)
+#define FLASH_SR_HVOFF_Msk (0x1UL << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
+#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
+#define FLASH_SR_READY_Pos (3U)
+#define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */
+#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR_Pos (8U)
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
+#define FLASH_SR_PGAERR_Pos (9U)
+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR_Pos (10U)
+#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
+#define FLASH_SR_OPTVERR_Pos (11U)
+#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
+#define FLASH_SR_RDERR_Pos (13U)
+#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
+#define FLASH_SR_NOTZEROERR_Pos (16U)
+#define FLASH_SR_NOTZEROERR_Msk (0x1UL << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
+#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
+#define FLASH_SR_FWWERR_Pos (17U)
+#define FLASH_SR_FWWERR_Msk (0x1UL << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
+#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
+
+/* Legacy defines */
+#define FLASH_SR_FWWER FLASH_SR_FWWERR
+#define FLASH_SR_ENHV FLASH_SR_HVOFF
+#define FLASH_SR_ENDHV FLASH_SR_HVOFF
+
+/****************** Bit definition for FLASH_OPTR register *******************/
+#define FLASH_OPTR_RDPROT_Pos (0U)
+#define FLASH_OPTR_RDPROT_Msk (0xFFUL << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
+#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
+#define FLASH_OPTR_WPRMOD_Pos (8U)
+#define FLASH_OPTR_WPRMOD_Msk (0x1UL << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
+#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
+#define FLASH_OPTR_BOR_LEV_Pos (16U)
+#define FLASH_OPTR_BOR_LEV_Msk (0xFUL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
+#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OPTR_IWDG_SW_Pos (20U)
+#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
+#define FLASH_OPTR_nRST_STOP_Pos (21U)
+#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OPTR_nRST_STDBY_Pos (22U)
+#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OPTR_USER_Pos (20U)
+#define FLASH_OPTR_USER_Msk (0x7UL << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
+#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OPTR_BOOT1_Pos (31U)
+#define FLASH_OPTR_BOOT1_Msk (0x1UL << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
+#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 (0x00000001U)
+#define GPIO_OTYPER_OT_1 (0x00000002U)
+#define GPIO_OTYPER_OT_2 (0x00000004U)
+#define GPIO_OTYPER_OT_3 (0x00000008U)
+#define GPIO_OTYPER_OT_4 (0x00000010U)
+#define GPIO_OTYPER_OT_5 (0x00000020U)
+#define GPIO_OTYPER_OT_6 (0x00000040U)
+#define GPIO_OTYPER_OT_7 (0x00000080U)
+#define GPIO_OTYPER_OT_8 (0x00000100U)
+#define GPIO_OTYPER_OT_9 (0x00000200U)
+#define GPIO_OTYPER_OT_10 (0x00000400U)
+#define GPIO_OTYPER_OT_11 (0x00000800U)
+#define GPIO_OTYPER_OT_12 (0x00001000U)
+#define GPIO_OTYPER_OT_13 (0x00002000U)
+#define GPIO_OTYPER_OT_14 (0x00004000U)
+#define GPIO_OTYPER_OT_15 (0x00008000U)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDER_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
+#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDER_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
+#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDER_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
+#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDER_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
+#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDER_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
+#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDER_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
+#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDER_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
+#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDER_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
+#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDER_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
+#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDER_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
+#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDER_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
+#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDER_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
+#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDER_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
+#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDER_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
+#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDER_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
+#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDER_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
+#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 (0x00000001U)
+#define GPIO_BSRR_BS_1 (0x00000002U)
+#define GPIO_BSRR_BS_2 (0x00000004U)
+#define GPIO_BSRR_BS_3 (0x00000008U)
+#define GPIO_BSRR_BS_4 (0x00000010U)
+#define GPIO_BSRR_BS_5 (0x00000020U)
+#define GPIO_BSRR_BS_6 (0x00000040U)
+#define GPIO_BSRR_BS_7 (0x00000080U)
+#define GPIO_BSRR_BS_8 (0x00000100U)
+#define GPIO_BSRR_BS_9 (0x00000200U)
+#define GPIO_BSRR_BS_10 (0x00000400U)
+#define GPIO_BSRR_BS_11 (0x00000800U)
+#define GPIO_BSRR_BS_12 (0x00001000U)
+#define GPIO_BSRR_BS_13 (0x00002000U)
+#define GPIO_BSRR_BS_14 (0x00004000U)
+#define GPIO_BSRR_BS_15 (0x00008000U)
+#define GPIO_BSRR_BR_0 (0x00010000U)
+#define GPIO_BSRR_BR_1 (0x00020000U)
+#define GPIO_BSRR_BR_2 (0x00040000U)
+#define GPIO_BSRR_BR_3 (0x00080000U)
+#define GPIO_BSRR_BR_4 (0x00100000U)
+#define GPIO_BSRR_BR_5 (0x00200000U)
+#define GPIO_BSRR_BR_6 (0x00400000U)
+#define GPIO_BSRR_BR_7 (0x00800000U)
+#define GPIO_BSRR_BR_8 (0x01000000U)
+#define GPIO_BSRR_BR_9 (0x02000000U)
+#define GPIO_BSRR_BR_10 (0x04000000U)
+#define GPIO_BSRR_BR_11 (0x08000000U)
+#define GPIO_BSRR_BR_12 (0x10000000U)
+#define GPIO_BSRR_BR_13 (0x20000000U)
+#define GPIO_BSRR_BR_14 (0x40000000U)
+#define GPIO_BSRR_BR_15 (0x80000000U)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 (0x00000001U)
+#define GPIO_BRR_BR_1 (0x00000002U)
+#define GPIO_BRR_BR_2 (0x00000004U)
+#define GPIO_BRR_BR_3 (0x00000008U)
+#define GPIO_BRR_BR_4 (0x00000010U)
+#define GPIO_BRR_BR_5 (0x00000020U)
+#define GPIO_BRR_BR_6 (0x00000040U)
+#define GPIO_BRR_BR_7 (0x00000080U)
+#define GPIO_BRR_BR_8 (0x00000100U)
+#define GPIO_BRR_BR_9 (0x00000200U)
+#define GPIO_BRR_BR_10 (0x00000400U)
+#define GPIO_BRR_BR_11 (0x00000800U)
+#define GPIO_BRR_BR_12 (0x00001000U)
+#define GPIO_BRR_BR_13 (0x00002000U)
+#define GPIO_BRR_BR_14 (0x00004000U)
+#define GPIO_BRR_BR_15 (0x00008000U)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos (1U)
+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos (2U)
+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos (3U)
+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos (4U)
+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos (5U)
+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos (6U)
+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos (7U)
+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos (8U)
+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos (12U)
+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos (14U)
+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos (15U)
+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos (16U)
+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos (17U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos (18U)
+#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos (19U)
+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos (20U)
+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos (21U)
+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos (22U)
+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos (23U)
+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD_Pos (0U)
+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos (10U)
+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos (11U)
+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos (12U)
+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos (13U)
+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
+#define I2C_CR2_STOP_Pos (14U)
+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos (15U)
+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos (16U)
+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos (24U)
+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos (25U)
+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos (26U)
+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1_Pos (0U)
+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos (10U)
+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos (15U)
+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2_Pos (1U)
+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos (8U)
+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos (8U)
+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos (9U)
+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos (8U)
+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos (10U)
+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos (8U)
+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos (9U)
+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos (8U)
+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos (15U)
+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos (0U)
+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos (8U)
+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos (16U)
+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos (20U)
+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos (28U)
+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE_Pos (0U)
+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos (1U)
+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos (2U)
+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos (3U)
+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos (4U)
+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos (5U)
+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos (6U)
+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos (7U)
+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos (8U)
+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
+#define I2C_ISR_ARLO_Pos (9U)
+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos (10U)
+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos (11U)
+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos (12U)
+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos (13U)
+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos (15U)
+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
+#define I2C_ISR_DIR_Pos (16U)
+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos (17U)
+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF_Pos (3U)
+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos (4U)
+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos (5U)
+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos (8U)
+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos (9U)
+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos (10U)
+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos (11U)
+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos (12U)
+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos (13U)
+#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define I2C_PECR_PEC_Pos (0U)
+#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA_Pos (0U)
+#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA_Pos (0U)
+#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos (2U)
+#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN_Pos (0U)
+#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM_Pos (0U)
+#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos (1U)
+#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos (2U)
+#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos (3U)
+#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos (4U)
+#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos (5U)
+#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos (6U)
+#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF_Pos (0U)
+#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos (1U)
+#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos (3U)
+#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos (4U)
+#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos (5U)
+#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos (6U)
+#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos (0U)
+#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos (1U)
+#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos (3U)
+#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos (4U)
+#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos (5U)
+#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos (6U)
+#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos (0U)
+#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos (1U)
+#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos (3U)
+#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos (6U)
+#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos (9U)
+#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos (17U)
+#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos (19U)
+#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos (20U)
+#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos (21U)
+#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos (22U)
+#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos (24U)
+#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE_Pos (0U)
+#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos (1U)
+#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos (2U)
+#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP_Pos (0U)
+#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR_Pos (0U)
+#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT_Pos (0U)
+#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
+
+/******************************************************************************/
+/* */
+/* MIFARE Firewall */
+/* */
+/******************************************************************************/
+
+/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
+#define FW_CSSA_ADD_Pos (8U)
+#define FW_CSSA_ADD_Msk (0xFFFFUL << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
+#define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
+#define FW_CSL_LENG_Pos (8U)
+#define FW_CSL_LENG_Msk (0x3FFFUL << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
+#define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
+#define FW_NVDSSA_ADD_Pos (8U)
+#define FW_NVDSSA_ADD_Msk (0xFFFFUL << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
+#define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
+#define FW_NVDSL_LENG_Pos (8U)
+#define FW_NVDSL_LENG_Msk (0x3FFFUL << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
+#define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
+#define FW_VDSSA_ADD_Pos (6U)
+#define FW_VDSSA_ADD_Msk (0x3FFUL << FW_VDSSA_ADD_Pos) /*!< 0x0000FFC0 */
+#define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
+#define FW_VDSL_LENG_Pos (6U)
+#define FW_VDSL_LENG_Msk (0x3FFUL << FW_VDSL_LENG_Pos) /*!< 0x0000FFC0 */
+#define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
+
+/**************************Bit definition for CR register *********************/
+#define FW_CR_FPA_Pos (0U)
+#define FW_CR_FPA_Msk (0x1UL << FW_CR_FPA_Pos) /*!< 0x00000001 */
+#define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
+#define FW_CR_VDS_Pos (1U)
+#define FW_CR_VDS_Msk (0x1UL << FW_CR_VDS_Pos) /*!< 0x00000002 */
+#define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
+#define FW_CR_VDE_Pos (2U)
+#define FW_CR_VDE_Msk (0x1UL << FW_CR_VDE_Pos) /*!< 0x00000004 */
+#define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
+
+/******************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/******************************************************************************/
+
+#define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPSDSR_Pos (0U)
+#define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP_Pos (9U)
+#define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /*!< 0x00000200 */
+#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
+#define PWR_CR_FWU_Pos (10U)
+#define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /*!< 0x00000400 */
+#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
+
+#define PWR_CR_VOS_Pos (11U)
+#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x00001800 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /*!< 0x00000800 */
+#define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /*!< 0x00001000 */
+#define PWR_CR_DSEEKOFF_Pos (13U)
+#define PWR_CR_DSEEKOFF_Msk (0x1UL << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */
+#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */
+#define PWR_CR_LPRUN_Pos (14U)
+#define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
+#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF_Pos (3U)
+#define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
+#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF_Pos (4U)
+#define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
+#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF_Pos (5U)
+#define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
+#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1_Pos (8U)
+#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2_Pos (9U)
+#define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
+#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos (1U)
+#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos (2U)
+#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIVEN_Pos (3U)
+#define RCC_CR_HSIDIVEN_Msk (0x1UL << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */
+#define RCC_CR_HSIDIVF_Pos (4U)
+#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */
+#define RCC_CR_MSION_Pos (8U)
+#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000100 */
+#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY_Pos (9U)
+#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
+#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON_Pos (19U)
+#define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */
+#define RCC_CR_RTCPRE_Pos (20U)
+#define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
+#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */
+#define RCC_CR_RTCPRE_0 (0x1UL << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */
+#define RCC_CR_RTCPRE_1 (0x2UL << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+/* Reference defines */
+#define RCC_CR_CSSON RCC_CR_CSSHSEON
+
+/******************** Bit definition for RCC_ICSCR register *****************/
+#define RCC_ICSCR_HSICAL_Pos (0U)
+#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
+#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM_Pos (8U)
+#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
+#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE_Pos (13U)
+#define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
+#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
+#define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
+#define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
+#define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
+#define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
+#define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
+#define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
+#define RCC_ICSCR_MSICAL_Pos (16U)
+#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
+#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM_Pos (24U)
+#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
+#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos (15U)
+#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */
+
+/*!< PLL entry clock source*/
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
+
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL_Pos (18U)
+#define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV_Pos (22U)
+#define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
+
+#define RCC_CFGR_PLLDIV2_Pos (22U)
+#define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3_Pos (23U)
+#define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4_Pos (22U)
+#define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCOSEL_Pos (24U)
+#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
+#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
+
+#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
+#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCOSEL_HSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_MSI_Pos (24U)
+#define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
+#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_HSE_Pos (26U)
+#define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCOSEL_PLL_Pos (24U)
+#define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
+#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
+#define RCC_CFGR_MCOSEL_LSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
+#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
+#define RCC_CFGR_MCOSEL_LSE_Pos (24U)
+#define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
+
+#define RCC_CFGR_MCOPRE_Pos (28U)
+#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
+
+#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
+
+/* Legacy defines */
+#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
+#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
+#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
+#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
+#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
+#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
+#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
+#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
+#ifdef RCC_CFGR_MCOSEL_HSI48
+#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48
+#endif
+
+#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
+#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
+
+/*!<****************** Bit definition for RCC_CIER register ********************/
+#define RCC_CIER_LSIRDYIE_Pos (0U)
+#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIER_LSERDYIE_Pos (1U)
+#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIER_HSIRDYIE_Pos (2U)
+#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIER_HSERDYIE_Pos (3U)
+#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIER_PLLRDYIE_Pos (4U)
+#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIER_MSIRDYIE_Pos (5U)
+#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
+#define RCC_CIER_CSSLSE_Pos (7U)
+#define RCC_CIER_CSSLSE_Msk (0x1UL << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */
+
+/* Reference defines */
+#define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
+
+/*!<****************** Bit definition for RCC_CIFR register ********************/
+#define RCC_CIFR_LSIRDYF_Pos (0U)
+#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIFR_LSERDYF_Pos (1U)
+#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIFR_HSIRDYF_Pos (2U)
+#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIFR_HSERDYF_Pos (3U)
+#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIFR_PLLRDYF_Pos (4U)
+#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIFR_MSIRDYF_Pos (5U)
+#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
+#define RCC_CIFR_CSSLSEF_Pos (7U)
+#define RCC_CIFR_CSSLSEF_Msk (0x1UL << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */
+#define RCC_CIFR_CSSHSEF_Pos (8U)
+#define RCC_CIFR_CSSHSEF_Msk (0x1UL << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */
+#define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */
+
+/* Reference defines */
+#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
+#define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
+
+/*!<****************** Bit definition for RCC_CICR register ********************/
+#define RCC_CICR_LSIRDYC_Pos (0U)
+#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CICR_LSERDYC_Pos (1U)
+#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CICR_HSIRDYC_Pos (2U)
+#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CICR_HSERDYC_Pos (3U)
+#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CICR_PLLRDYC_Pos (4U)
+#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CICR_MSIRDYC_Pos (5U)
+#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
+#define RCC_CICR_CSSLSEC_Pos (7U)
+#define RCC_CICR_CSSLSEC_Msk (0x1UL << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */
+#define RCC_CICR_CSSHSEC_Pos (8U)
+#define RCC_CICR_CSSHSEC_Msk (0x1UL << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */
+#define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */
+
+/* Reference defines */
+#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
+#define RCC_CICR_CSSC RCC_CICR_CSSHSEC
+/***************** Bit definition for RCC_IOPRSTR register ******************/
+#define RCC_IOPRSTR_IOPARST_Pos (0U)
+#define RCC_IOPRSTR_IOPARST_Msk (0x1UL << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */
+#define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */
+#define RCC_IOPRSTR_IOPBRST_Pos (1U)
+#define RCC_IOPRSTR_IOPBRST_Msk (0x1UL << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */
+#define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */
+#define RCC_IOPRSTR_IOPCRST_Pos (2U)
+#define RCC_IOPRSTR_IOPCRST_Msk (0x1UL << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */
+#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */
+#define RCC_IOPRSTR_IOPDRST_Pos (3U)
+#define RCC_IOPRSTR_IOPDRST_Msk (0x1UL << RCC_IOPRSTR_IOPDRST_Pos) /*!< 0x00000008 */
+#define RCC_IOPRSTR_IOPDRST RCC_IOPRSTR_IOPDRST_Msk /*!< GPIO port D reset */
+#define RCC_IOPRSTR_IOPHRST_Pos (7U)
+#define RCC_IOPRSTR_IOPHRST_Msk (0x1UL << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */
+#define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */
+
+/* Reference defines */
+#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
+#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
+#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
+#define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_IOPDRST /*!< GPIO port D reset */
+#define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
+
+
+/****************** Bit definition for RCC_AHBRST register ******************/
+#define RCC_AHBRSTR_DMARST_Pos (0U)
+#define RCC_AHBRSTR_DMARST_Msk (0x1UL << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */
+#define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */
+#define RCC_AHBRSTR_MIFRST_Pos (8U)
+#define RCC_AHBRSTR_MIFRST_Msk (0x1UL << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */
+#define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset */
+#define RCC_AHBRSTR_CRCRST_Pos (12U)
+#define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */
+#define RCC_AHBRSTR_CRYPRST_Pos (24U)
+#define RCC_AHBRSTR_CRYPRST_Msk (0x1UL << RCC_AHBRSTR_CRYPRST_Pos) /*!< 0x01000000 */
+#define RCC_AHBRSTR_CRYPRST RCC_AHBRSTR_CRYPRST_Msk /*!< Crypto reset */
+
+/* Reference defines */
+#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
+#define RCC_APB2RSTR_TIM21RST_Pos (2U)
+#define RCC_APB2RSTR_TIM21RST_Msk (0x1UL << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 reset */
+#define RCC_APB2RSTR_TIM22RST_Pos (5U)
+#define RCC_APB2RSTR_TIM22RST_Msk (0x1UL << RCC_APB2RSTR_TIM22RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk /*!< TIM22 reset */
+#define RCC_APB2RSTR_ADCRST_Pos (9U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
+#define RCC_APB2RSTR_DBGRST_Pos (22U)
+#define RCC_APB2RSTR_DBGRST_Msk (0x1UL << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU reset */
+
+/* Reference defines */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 reset */
+#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU reset */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_LPUART1RST_Pos (18U)
+#define RCC_APB1RSTR_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
+#define RCC_APB1RSTR_LPTIM1RST_Pos (31U)
+#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 reset */
+
+/***************** Bit definition for RCC_IOPENR register ******************/
+#define RCC_IOPENR_IOPAEN_Pos (0U)
+#define RCC_IOPENR_IOPAEN_Msk (0x1UL << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */
+#define RCC_IOPENR_IOPBEN_Pos (1U)
+#define RCC_IOPENR_IOPBEN_Msk (0x1UL << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */
+#define RCC_IOPENR_IOPCEN_Pos (2U)
+#define RCC_IOPENR_IOPCEN_Msk (0x1UL << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */
+#define RCC_IOPENR_IOPDEN_Pos (3U)
+#define RCC_IOPENR_IOPDEN_Msk (0x1UL << RCC_IOPENR_IOPDEN_Pos) /*!< 0x00000008 */
+#define RCC_IOPENR_IOPDEN RCC_IOPENR_IOPDEN_Msk /*!< GPIO port D clock enable */
+#define RCC_IOPENR_IOPHEN_Pos (7U)
+#define RCC_IOPENR_IOPHEN_Msk (0x1UL << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */
+
+/* Reference defines */
+#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
+#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
+#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
+#define RCC_IOPENR_GPIODEN RCC_IOPENR_IOPDEN /*!< GPIO port D clock enable */
+#define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
+
+/***************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMAEN_Pos (0U)
+#define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_MIFEN_Pos (8U)
+#define RCC_AHBENR_MIFEN_Msk (0x1UL << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */
+#define RCC_AHBENR_CRCEN_Pos (12U)
+#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+#define RCC_AHBENR_CRYPEN_Pos (24U)
+#define RCC_AHBENR_CRYPEN_Msk (0x1UL << RCC_AHBENR_CRYPEN_Pos) /*!< 0x01000000 */
+#define RCC_AHBENR_CRYPEN RCC_AHBENR_CRYPEN_Msk /*!< Crypto clock enable*/
+
+/* Reference defines */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register ******************/
+#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM21EN_Pos (2U)
+#define RCC_APB2ENR_TIM21EN_Msk (0x1UL << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */
+#define RCC_APB2ENR_TIM22EN_Pos (5U)
+#define RCC_APB2ENR_TIM22EN_Msk (0x1UL << RCC_APB2ENR_TIM22EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk /*!< TIM22 clock enable */
+#define RCC_APB2ENR_FWEN_Pos (7U)
+#define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADCEN_Pos (9U)
+#define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
+#define RCC_APB2ENR_DBGEN_Pos (22U)
+#define RCC_APB2ENR_DBGEN_Msk (0x1UL << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */
+
+/* Reference defines */
+
+#define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
+#define RCC_APB1ENR_LPUART1EN_Pos (18U)
+#define RCC_APB1ENR_LPUART1EN_Msk (0x1UL << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
+#define RCC_APB1ENR_LPTIM1EN_Pos (31U)
+#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */
+
+/****************** Bit definition for RCC_IOPSMENR register ****************/
+#define RCC_IOPSMENR_IOPASMEN_Pos (0U)
+#define RCC_IOPSMENR_IOPASMEN_Msk (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPBSMEN_Pos (1U)
+#define RCC_IOPSMENR_IOPBSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPCSMEN_Pos (2U)
+#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPDSMEN_Pos (3U)
+#define RCC_IOPSMENR_IOPDSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos) /*!< 0x00000008 */
+#define RCC_IOPSMENR_IOPDSMEN RCC_IOPSMENR_IOPDSMEN_Msk /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPHSMEN_Pos (7U)
+#define RCC_IOPSMENR_IOPHSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_IOPDSMEN /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_AHBSMENR register ******************/
+#define RCC_AHBSMENR_DMASMEN_Pos (0U)
+#define RCC_AHBSMENR_DMASMEN_Msk (0x1UL << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */
+#define RCC_AHBSMENR_MIFSMEN_Pos (8U)
+#define RCC_AHBSMENR_MIFSMEN_Msk (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */
+#define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
+#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRCSMEN_Pos (12U)
+#define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRYPSMEN_Pos (24U)
+#define RCC_AHBSMENR_CRYPSMEN_Msk (0x1UL << RCC_AHBSMENR_CRYPSMEN_Pos) /*!< 0x01000000 */
+#define RCC_AHBSMENR_CRYPSMEN RCC_AHBSMENR_CRYPSMEN_Msk /*!< Crypto clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB2SMENR register ******************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM21SMEN_Pos (2U)
+#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM22SMEN_Pos (5U)
+#define RCC_APB2SMENR_TIM22SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk /*!< TIM22 clock enabled in sleep mode */
+#define RCC_APB2SMENR_ADCSMEN_Pos (9U)
+#define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
+#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
+#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk /*!< USART1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGSMEN_Pos (22U)
+#define RCC_APB2SMENR_DBGSMEN_Msk (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB1SMENR register ******************/
+#define RCC_APB1SMENR_TIM2SMEN_Pos (0U)
+#define RCC_APB1SMENR_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_TIM6SMEN_Pos (4U)
+#define RCC_APB1SMENR_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM6SMEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1SMENR_TIM6SMEN RCC_APB1SMENR_TIM6SMEN_Msk /*!< Timer 6 clock enabled in sleep mode */
+#define RCC_APB1SMENR_WWDGSMEN_Pos (11U)
+#define RCC_APB1SMENR_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */
+#define RCC_APB1SMENR_SPI2SMEN_Pos (14U)
+#define RCC_APB1SMENR_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR_SPI2SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1SMENR_SPI2SMEN RCC_APB1SMENR_SPI2SMEN_Msk /*!< SPI2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART2SMEN_Pos (17U)
+#define RCC_APB1SMENR_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPUART1SMEN_Pos (18U)
+#define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C1SMEN_Pos (21U)
+#define RCC_APB1SMENR_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C2SMEN_Pos (22U)
+#define RCC_APB1SMENR_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1SMENR_I2C2SMEN RCC_APB1SMENR_I2C2SMEN_Msk /*!< I2C2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_PWRSMEN_Pos (28U)
+#define RCC_APB1SMENR_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U)
+#define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */
+
+/******************* Bit definition for RCC_CCIPR register *******************/
+/*!< USART1 Clock source selection */
+#define RCC_CCIPR_USART1SEL_Pos (0U)
+#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
+#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk /*!< USART1SEL[1:0] bits */
+#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
+
+/*!< USART2 Clock source selection */
+#define RCC_CCIPR_USART2SEL_Pos (2U)
+#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */
+#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+/*!< LPUART1 Clock source selection */
+#define RCC_CCIPR_LPUART1SEL_Pos (10U)
+#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */
+#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */
+#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CCIPR_I2C1SEL_Pos (12U)
+#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */
+#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
+
+
+/*!< LPTIM1 Clock source selection */
+#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
+#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */
+#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+/******************* Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSEON_Pos (8U)
+#define RCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */
+#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_CSR_LSERDY_Pos (9U)
+#define RCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */
+#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP_Pos (10U)
+#define RCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */
+#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_CSR_LSEDRV_Pos (11U)
+#define RCC_CSR_LSEDRV_Msk (0x3UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */
+#define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_CSR_LSEDRV_0 (0x1UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */
+#define RCC_CSR_LSEDRV_1 (0x2UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */
+
+#define RCC_CSR_LSECSSON_Pos (13U)
+#define RCC_CSR_LSECSSON_Msk (0x1UL << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */
+#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */
+#define RCC_CSR_LSECSSD_Pos (14U)
+#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
+#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
+
+/*!< RTC congiguration */
+#define RCC_CSR_RTCSEL_Pos (16U)
+#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
+
+#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CSR_RTCSEL_LSE_Pos (16U)
+#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_LSI_Pos (17U)
+#define RCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */
+#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_HSE_Pos (16U)
+#define RCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */
+
+#define RCC_CSR_RTCEN_Pos (18U)
+#define RCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */
+#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_CSR_RTCRST_Pos (19U)
+#define RCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */
+#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */
+
+#define RCC_CSR_RMVF_Pos (23U)
+#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_FWRSTF_Pos (24U)
+#define RCC_CSR_FWRSTF_Msk (0x1UL << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk /*!< Mifare Firewall reset flag */
+#define RCC_CSR_OBLRSTF_Pos (25U)
+#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+/* Reference defines */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER1_SUPPORT
+#define RTC_TAMPER2_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk /*!< */
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk /*!< */
+#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk /*!< */
+#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */
+#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */
+#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk /*!< */
+#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk /*!< */
+#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk /*!< */
+#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk /*!< */
+#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */
+#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk /*!< */
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk /*!< */
+#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk /*!< */
+#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk /*!< */
+#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk /*!< */
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */
+#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk /*!< */
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< */
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */
+#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */
+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */
+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */
+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */
+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */
+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */
+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */
+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */
+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */
+#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */
+#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */
+#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */
+#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */
+#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */
+#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */
+#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */
+#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */
+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */
+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */
+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */
+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */
+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */
+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */
+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */
+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */
+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */
+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CALR register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */
+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define RTC_CAL_CALP RTC_CALR_CALP
+#define RTC_CAL_CALW8 RTC_CALR_CALW8
+#define RTC_CAL_CALW16 RTC_CALR_CALW16
+#define RTC_CAL_CALM RTC_CALR_CALM
+#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
+
+/******************** Bits definition for RTC_TAMPCR register ****************/
+#define RTC_TAMPCR_TAMP2MF_Pos (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2IE_Pos (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1MF_Pos (18U)
+#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
+#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1IE_Pos (16U)
+#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */
+#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */
+#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */
+#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos (7U)
+#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */
+#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP2E_Pos (3U)
+#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */
+#define RTC_TAMPCR_TAMPIE_Pos (2U)
+#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
+#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP1E_Pos (0U)
+#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_OR register ****************/
+#define RTC_OR_OUT_RMP_Pos (1U)
+#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */
+#define RTC_OR_ALARMOUTTYPE_Pos (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */
+
+/* Legacy defines */
+#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk /*!< */
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER (0x00000005U) /*!< */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+#define SPI_I2S_SUPPORT /*!< I2S support */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
+#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR1_BOOT_MODE_Pos (8U)
+#define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
+#define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */
+#define SYSCFG_CFGR1_BOOT_MODE_0 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOT_MODE_1 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_FWDISEN_Pos (0U)
+#define SYSCFG_CFGR2_FWDISEN_Msk (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos (8U)
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR2_I2C_PB6_FMP SYSCFG_CFGR2_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos (9U)
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR2_I2C_PB7_FMP SYSCFG_CFGR2_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos (10U)
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
+#define SYSCFG_CFGR2_I2C_PB8_FMP SYSCFG_CFGR2_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos (11U)
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
+#define SYSCFG_CFGR2_I2C_PB9_FMP SYSCFG_CFGR2_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR2_I2C1_FMP_Pos (12U)
+#define SYSCFG_CFGR2_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR2_I2C1_FMP SYSCFG_CFGR2_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR2_I2C2_FMP_Pos (13U)
+#define SYSCFG_CFGR2_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
+#define SYSCFG_CFGR2_I2C2_FMP SYSCFG_CFGR2_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
+
+
+/***************** Bit definition for SYSCFG_CFGR3 register ****************/
+#define SYSCFG_CFGR3_EN_VREFINT_Pos (0U)
+#define SYSCFG_CFGR3_EN_VREFINT_Msk (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_EN_VREFINT SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
+#define SYSCFG_CFGR3_VREF_OUT_Pos (4U)
+#define SYSCFG_CFGR3_VREF_OUT_Msk (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
+#define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */
+#define SYSCFG_CFGR3_VREF_OUT_0 (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
+#define SYSCFG_CFGR3_VREF_OUT_1 (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U)
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U)
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U)
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
+#define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U)
+#define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
+#define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
+#define SYSCFG_CFGR3_REF_LOCK_Pos (31U)
+#define SYSCFG_CFGR3_REF_LOCK_Msk (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
+#define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */
+
+/* Legacy defines */
+
+#define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
+#define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
+#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
+#define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+
+/******************************************************************************/
+/* */
+/* Timers (TIM)*/
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
+#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
+ || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#else
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#endif
+
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFUL << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFUL << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM2_OR_ETR_RMP_Pos (0U)
+#define TIM2_OR_ETR_RMP_Msk (0x7UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000007 */
+#define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
+#define TIM2_OR_ETR_RMP_0 (0x1UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM2_OR_ETR_RMP_1 (0x2UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM2_OR_ETR_RMP_2 (0x4UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000004 */
+#define TIM2_OR_TI4_RMP_Pos (3U)
+#define TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000018 */
+#define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
+#define TIM2_OR_TI4_RMP_0 (0x1UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */
+#define TIM2_OR_TI4_RMP_1 (0x2UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000010 */
+
+#define TIM21_OR_ETR_RMP_Pos (0U)
+#define TIM21_OR_ETR_RMP_Msk (0x3UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
+#define TIM21_OR_ETR_RMP_0 (0x1UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM21_OR_ETR_RMP_1 (0x2UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM21_OR_TI1_RMP_Pos (2U)
+#define TIM21_OR_TI1_RMP_Msk (0x7UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x0000001C */
+#define TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
+#define TIM21_OR_TI1_RMP_0 (0x1UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM21_OR_TI1_RMP_1 (0x2UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+#define TIM21_OR_TI1_RMP_2 (0x4UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000010 */
+#define TIM21_OR_TI2_RMP_Pos (5U)
+#define TIM21_OR_TI2_RMP_Msk (0x1UL << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */
+#define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */
+
+#define TIM22_OR_ETR_RMP_Pos (0U)
+#define TIM22_OR_ETR_RMP_Msk (0x3UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM22_OR_ETR_RMP TIM22_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
+#define TIM22_OR_ETR_RMP_0 (0x1UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM22_OR_ETR_RMP_1 (0x2UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM22_OR_TI1_RMP_Pos (2U)
+#define TIM22_OR_TI1_RMP_Msk (0x3UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x0000000C */
+#define TIM22_OR_TI1_RMP TIM22_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
+#define TIM22_OR_TI1_RMP_0 (0x1UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM22_OR_TI1_RMP_1 (0x2UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE_Pos (0U)
+#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+#define USART_CR1_UESM_Pos (1U)
+#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
+#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_M0_Pos (12U)
+#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
+#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos (13U)
+#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos (14U)
+#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos (16U)
+#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
+#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
+#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
+#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
+#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos (21U)
+#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
+#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
+#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
+#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
+#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos (26U)
+#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos (27U)
+#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos (28U)
+#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
+#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7_Pos (4U)
+#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos (15U)
+#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos (16U)
+#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos (17U)
+#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos (18U)
+#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos (19U)
+#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos (20U)
+#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos (21U)
+#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos (23U)
+#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos (24U)
+#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos (12U)
+#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos (13U)
+#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos (14U)
+#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos (15U)
+#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos (17U)
+#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos (20U)
+#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
+#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
+#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos (22U)
+#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
+#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
+#define USART_CR3_UCESM_Pos (23U)
+#define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
+#define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION_Pos (0U)
+#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos (4U)
+#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO_Pos (0U)
+#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos (24U)
+#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ_Pos (0U)
+#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
+#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos (1U)
+#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
+#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos (2U)
+#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
+#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos (3U)
+#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
+#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos (4U)
+#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
+#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE_Pos (0U)
+#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
+#define USART_ISR_FE_Pos (1U)
+#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
+#define USART_ISR_NE_Pos (2U)
+#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos (3U)
+#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos (4U)
+#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos (5U)
+#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos (6U)
+#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos (7U)
+#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
+#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos (8U)
+#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos (9U)
+#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos (10U)
+#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
+#define USART_ISR_RTOF_Pos (11U)
+#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos (12U)
+#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos (14U)
+#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos (15U)
+#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos (16U)
+#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
+#define USART_ISR_CMF_Pos (17U)
+#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos (18U)
+#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos (19U)
+#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos (20U)
+#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
+#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos (21U)
+#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos (22U)
+#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
+#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF_Pos (0U)
+#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos (1U)
+#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos (2U)
+#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */
+#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos (3U)
+#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos (4U)
+#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos (6U)
+#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF_Pos (8U)
+#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos (9U)
+#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos (11U)
+#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos (12U)
+#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos (17U)
+#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos (20U)
+#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
+#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
+
+/* Compatibility defines with other series */
+#define USART_ICR_NECF USART_ICR_NCF
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR_Pos (0U)
+#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR_Pos (0U)
+#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+/******************************* AES Instances ********************************/
+#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
+
+/******************************* COMP Instances *******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+ ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOH))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
+
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2)
+
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SMBUS Instances *****************************/
+#define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/************* LPTIM instances supporting the encoder mode feature ************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM6))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM21) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM22) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/******************* TIM Instances : output(s) OCXEC register *****************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** USART Instances : Auto Baud Rate detection ****************/
+
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32L0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32L0 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+
+#define RNG_LPUART1_IRQn AES_LPUART1_IRQn
+#define LPUART1_IRQn AES_LPUART1_IRQn
+#define AES_RNG_LPUART1_IRQn AES_LPUART1_IRQn
+#define TIM6_DAC_IRQn TIM6_IRQn
+#define RCC_CRS_IRQn RCC_IRQn
+#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
+#define ADC1_IRQn ADC1_COMP_IRQn
+
+/* Aliases for __IRQHandler */
+#define LPUART1_IRQHandler AES_LPUART1_IRQHandler
+#define RNG_LPUART1_IRQHandler AES_LPUART1_IRQHandler
+#define AES_RNG_LPUART1_IRQHandler AES_LPUART1_IRQHandler
+#define TIM6_DAC_IRQHandler TIM6_IRQHandler
+#define RCC_CRS_IRQHandler RCC_IRQHandler
+#define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
+#define ADC1_IRQHandler ADC1_COMP_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L061xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/CMSIS/device/stm32l062xx.h b/CMSIS/device/stm32l062xx.h
new file mode 100644
index 0000000..b4b5958
--- /dev/null
+++ b/CMSIS/device/stm32l062xx.h
@@ -0,0 +1,7489 @@
+/**
+ ******************************************************************************
+ * @file stm32l062xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for stm32l062xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright(c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l062xx
+ * @{
+ */
+
+#ifndef __STM32L062xx_H
+#define __STM32L062xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 1U /*!< STM32L0xx provides an MPU */
+#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
+#define __NVIC_PRIO_BITS 2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief stm32l062xx Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+/*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
+
+/****** STM32L-0 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */
+ RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ TSC_IRQn = 8, /*!< TSC Interrupt */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
+ ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
+ LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 Interrupt */
+ TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
+ TIM21_IRQn = 20, /*!< TIM21 Interrupt */
+ TIM22_IRQn = 22, /*!< TIM22 Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */
+ I2C2_IRQn = 24, /*!< I2C2 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ SPI2_IRQn = 26, /*!< SPI2 Interrupt */
+ USART1_IRQn = 27, /*!< USART1 Interrupt */
+ USART2_IRQn = 28, /*!< USART2 Interrupt */
+ AES_RNG_LPUART1_IRQn = 29, /*!< AES and RNG and LPUART1 Interrupts */
+ USB_IRQn = 31, /*!< USB global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0plus.h"
+#include "system_stm32l0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+ uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+} ADC_Common_TypeDef;
+
+/**
+ * @brief AES hardware accelerator
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
+ __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
+ __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
+ __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
+ __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
+ __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
+ __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
+ __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
+ __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
+ __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
+ __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
+} AES_TypeDef;
+
+/**
+ * @brief Comparator
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
+} COMP_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+
+/**
+* @brief CRC calculation unit
+*/
+
+typedef struct
+{
+__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+uint8_t RESERVED0; /*!< Reserved, 0x05 */
+uint16_t RESERVED1; /*!< Reserved, 0x06 */
+__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+uint32_t RESERVED2; /*!< Reserved, 0x0C */
+__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Clock Recovery System
+ */
+
+typedef struct
+{
+__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
+__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
+__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
+__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
+} CRS_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ uint32_t RESERVED0[6]; /*!< 0x14-0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ uint32_t RESERVED1; /*!< 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
+} DMA_Request_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
+ __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
+ __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
+ __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
+ __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
+ __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
+ __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
+ __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
+ __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
+ __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
+} OB_TypeDef;
+
+
+/**
+ * @brief General Purpose IO
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief LPTIMIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+} LPTIM_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+ * @brief Independent WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief MIFARE Firewall
+ */
+typedef struct
+{
+ __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
+ __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
+ __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
+ __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
+ __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
+ __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
+ __IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x18 */
+ __IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */
+ __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
+
+} FIREWALL_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
+ __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
+ __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
+ __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
+ __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
+ __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
+ __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
+ __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
+ __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
+ __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
+ __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
+} RCC_TypeDef;
+
+/**
+ * @brief Random numbers generator
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Touch Sensing Controller (TSC)
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
+ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
+ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
+ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
+ __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief Universal Serial Bus Full Speed Device
+ */
+typedef struct
+{
+ __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
+ __IO uint16_t RESERVED0; /*!< Reserved */
+ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
+ __IO uint16_t RESERVED1; /*!< Reserved */
+ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
+ __IO uint16_t RESERVED2; /*!< Reserved */
+ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
+ __IO uint16_t RESERVED3; /*!< Reserved */
+ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
+ __IO uint16_t RESERVED4; /*!< Reserved */
+ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
+ __IO uint16_t RESERVED5; /*!< Reserved */
+ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
+ __IO uint16_t RESERVED6; /*!< Reserved */
+ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
+ __IO uint16_t RESERVED7[17]; /*!< Reserved */
+ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
+ __IO uint16_t RESERVED8; /*!< Reserved */
+ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
+ __IO uint16_t RESERVED9; /*!< Reserved */
+ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
+ __IO uint16_t RESERVEDA; /*!< Reserved */
+ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
+ __IO uint16_t RESERVEDB; /*!< Reserved */
+ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
+ __IO uint16_t RESERVEDC; /*!< Reserved */
+ __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
+ __IO uint16_t RESERVEDD; /*!< Reserved */
+ __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
+ __IO uint16_t RESERVEDE; /*!< Reserved */
+} USB_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */
+
+#define DATA_EEPROM_BASE (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
+#define DATA_EEPROM_END (0x080807FFUL) /*!< DATA EEPROM end address in the alias region */
+#define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */
+#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8KBytes) */
+
+#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000UL)
+
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL)
+#define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
+#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
+#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800UL)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
+#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL)
+#define CRS_BASE (APBPERIPH_BASE + 0x00006C00UL)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
+#define DAC_BASE (APBPERIPH_BASE + 0x00007400UL)
+#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL)
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
+#define COMP1_BASE (APBPERIPH_BASE + 0x00010018UL)
+#define COMP2_BASE (APBPERIPH_BASE + 0x0001001CUL)
+#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL)
+#define TIM21_BASE (APBPERIPH_BASE + 0x00010800UL)
+#define TIM22_BASE (APBPERIPH_BASE + 0x00011400UL)
+#define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00UL)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708UL)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
+#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
+#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL)
+
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
+#define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */
+#define FLASHSIZE_BASE (0x1FF8007CUL) /*!< FLASH Size register base address */
+#define UID_BASE (0x1FF80050UL) /*!< Unique device ID register base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
+#define TSC_BASE (AHBPERIPH_BASE + 0x00004000UL)
+#define RNG_BASE (AHBPERIPH_BASE + 0x00005000UL)
+#define AES_BASE (AHBPERIPH_BASE + 0x00006000UL)
+
+#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL)
+#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL)
+#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL)
+#define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00UL)
+#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00UL)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define CRS ((CRS_TypeDef *) CRS_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
+#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
+#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
+/* Legacy defines */
+#define ADC ADC1_COMMON
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define TSC ((TSC_TypeDef *) TSC_BASE)
+#define AES ((AES_TypeDef *) AES_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+
+#define USB ((USB_TypeDef *) USB_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_EOCAL_Pos (11U)
+#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
+#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
+#define ADC_ISR_AWD_Pos (7U)
+#define ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
+#define ADC_ISR_EOSEQ_Pos (3U)
+#define ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_EOCALIE_Pos (11U)
+#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
+#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
+#define ADC_IER_AWDIE_Pos (7U)
+#define ADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE_Pos (3U)
+#define ADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH_Pos (26U)
+#define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
+#define ADC_CFGR1_AWDEN_Pos (23U)
+#define ADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL_Pos (22U)
+#define ADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN_Pos (16U)
+#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF_Pos (15U)
+#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
+#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT_Pos (14U)
+#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
+#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT_Pos (13U)
+#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD_Pos (12U)
+#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN_Pos (10U)
+#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
+#define ADC_CFGR1_EXTSEL_Pos (6U)
+#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
+#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
+#define ADC_CFGR1_ALIGN_Pos (5U)
+#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
+#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
+#define ADC_CFGR1_RES_Pos (3U)
+#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
+#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
+#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
+#define ADC_CFGR1_SCANDIR_Pos (2U)
+#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG_Pos (1U)
+#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
+#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN_Pos (0U)
+#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
+#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_TOVS_Pos (9U)
+#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
+#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+#define ADC_CFGR2_OVSR_Pos (2U)
+#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
+#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+#define ADC_CFGR2_OVSE_Pos (0U)
+#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
+#define ADC_CFGR2_CKMODE_Pos (30U)
+#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
+#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
+#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
+#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
+
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP_Pos (0U)
+#define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
+#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
+#define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
+#define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define ADC_SMPR_SMPR ADC_SMPR_SMP
+#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
+#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
+#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT_Pos (16U)
+#define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
+#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
+#define ADC_TR_LT_Pos (0U)
+#define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL_Pos (0U)
+#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
+#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
+#define ADC_CHSELR_CHSEL18_Pos (18U)
+#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17_Pos (17U)
+#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
+#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL15_Pos (15U)
+#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
+#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14_Pos (14U)
+#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
+#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13_Pos (13U)
+#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
+#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12_Pos (12U)
+#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
+#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11_Pos (11U)
+#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
+#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10_Pos (10U)
+#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
+#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9_Pos (9U)
+#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
+#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8_Pos (8U)
+#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
+#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7_Pos (7U)
+#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
+#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6_Pos (6U)
+#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
+#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5_Pos (5U)
+#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
+#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4_Pos (4U)
+#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
+#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3_Pos (3U)
+#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
+#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2_Pos (2U)
+#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
+#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1_Pos (1U)
+#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
+#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0_Pos (0U)
+#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
+#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_CALFACT_Pos (0U)
+#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_LFMEN_Pos (25U)
+#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
+#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
+#define ADC_CCR_TSEN_Pos (23U)
+#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+/******************************************************************************/
+/* */
+/* Advanced Encryption Standard (AES) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for AES_CR register *********************/
+#define AES_CR_EN_Pos (0U)
+#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */
+#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */
+#define AES_CR_DATATYPE_Pos (1U)
+#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */
+#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */
+#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */
+#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */
+
+#define AES_CR_MODE_Pos (3U)
+#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */
+#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */
+#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */
+#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */
+
+#define AES_CR_CHMOD_Pos (5U)
+#define AES_CR_CHMOD_Msk (0x3UL << AES_CR_CHMOD_Pos) /*!< 0x00000060 */
+#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */
+#define AES_CR_CHMOD_0 (0x1UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */
+#define AES_CR_CHMOD_1 (0x2UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */
+
+#define AES_CR_CCFC_Pos (7U)
+#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */
+#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */
+#define AES_CR_ERRC_Pos (8U)
+#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */
+#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */
+#define AES_CR_CCIE_Pos (9U)
+#define AES_CR_CCIE_Msk (0x1UL << AES_CR_CCIE_Pos) /*!< 0x00000200 */
+#define AES_CR_CCIE AES_CR_CCIE_Msk /*!< Computation Complete Interrupt Enable */
+#define AES_CR_ERRIE_Pos (10U)
+#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */
+#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */
+#define AES_CR_DMAINEN_Pos (11U)
+#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */
+#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< DMA ENable managing the data input phase */
+#define AES_CR_DMAOUTEN_Pos (12U)
+#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */
+#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< DMA Enable managing the data output phase */
+
+/******************* Bit definition for AES_SR register *********************/
+#define AES_SR_CCF_Pos (0U)
+#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */
+#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */
+#define AES_SR_RDERR_Pos (1U)
+#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */
+#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */
+#define AES_SR_WRERR_Pos (2U)
+#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */
+#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */
+
+/******************* Bit definition for AES_DINR register *******************/
+#define AES_DINR_Pos (0U)
+#define AES_DINR_Msk (0xFFFFUL << AES_DINR_Pos) /*!< 0x0000FFFF */
+#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */
+
+/******************* Bit definition for AES_DOUTR register ******************/
+#define AES_DOUTR_Pos (0U)
+#define AES_DOUTR_Msk (0xFFFFUL << AES_DOUTR_Pos) /*!< 0x0000FFFF */
+#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */
+
+/******************* Bit definition for AES_KEYR0 register ******************/
+#define AES_KEYR0_Pos (0U)
+#define AES_KEYR0_Msk (0xFFFFUL << AES_KEYR0_Pos) /*!< 0x0000FFFF */
+#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */
+
+/******************* Bit definition for AES_KEYR1 register ******************/
+#define AES_KEYR1_Pos (0U)
+#define AES_KEYR1_Msk (0xFFFFUL << AES_KEYR1_Pos) /*!< 0x0000FFFF */
+#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */
+
+/******************* Bit definition for AES_KEYR2 register ******************/
+#define AES_KEYR2_Pos (0U)
+#define AES_KEYR2_Msk (0xFFFFUL << AES_KEYR2_Pos) /*!< 0x0000FFFF */
+#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */
+
+/******************* Bit definition for AES_KEYR3 register ******************/
+#define AES_KEYR3_Pos (0U)
+#define AES_KEYR3_Msk (0xFFFFUL << AES_KEYR3_Pos) /*!< 0x0000FFFF */
+#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */
+
+/******************* Bit definition for AES_IVR0 register *******************/
+#define AES_IVR0_Pos (0U)
+#define AES_IVR0_Msk (0xFFFFUL << AES_IVR0_Pos) /*!< 0x0000FFFF */
+#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */
+
+/******************* Bit definition for AES_IVR1 register *******************/
+#define AES_IVR1_Pos (0U)
+#define AES_IVR1_Msk (0xFFFFUL << AES_IVR1_Pos) /*!< 0x0000FFFF */
+#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */
+
+/******************* Bit definition for AES_IVR2 register *******************/
+#define AES_IVR2_Pos (0U)
+#define AES_IVR2_Msk (0xFFFFUL << AES_IVR2_Pos) /*!< 0x0000FFFF */
+#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */
+
+/******************* Bit definition for AES_IVR3 register *******************/
+#define AES_IVR3_Pos (0U)
+#define AES_IVR3_Msk (0xFFFFUL << AES_IVR3_Pos) /*!< 0x0000FFFF */
+#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+/************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN_Pos (0U)
+#define COMP_CSR_COMP1EN_Msk (0x1UL << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
+#define COMP_CSR_COMP1INNSEL_Pos (4U)
+#define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
+#define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP1WM_Pos (8U)
+#define COMP_CSR_COMP1WM_Msk (0x1UL << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */
+#define COMP_CSR_COMP1LPTIM1IN1_Pos (12U)
+#define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP1POLARITY_Pos (15U)
+#define COMP_CSR_COMP1POLARITY_Msk (0x1UL << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1VALUE_Pos (30U)
+#define COMP_CSR_COMP1VALUE_Msk (0x1UL << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK_Pos (31U)
+#define COMP_CSR_COMP1LOCK_Msk (0x1UL << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN_Pos (0U)
+#define COMP_CSR_COMP2EN_Msk (0x1UL << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
+#define COMP_CSR_COMP2SPEED_Pos (3U)
+#define COMP_CSR_COMP2SPEED_Msk (0x1UL << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */
+#define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */
+#define COMP_CSR_COMP2INNSEL_Pos (4U)
+#define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */
+#define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
+#define COMP_CSR_COMP2INPSEL_Pos (8U)
+#define COMP_CSR_COMP2INPSEL_Msk (0x7UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */
+#define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2INPSEL_0 (0x1UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP2INPSEL_1 (0x2UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */
+#define COMP_CSR_COMP2INPSEL_2 (0x4UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */
+#define COMP_CSR_COMP2LPTIM1IN2_Pos (12U)
+#define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */
+#define COMP_CSR_COMP2LPTIM1IN1_Pos (13U)
+#define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */
+#define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP2POLARITY_Pos (15U)
+#define COMP_CSR_COMP2POLARITY_Msk (0x1UL << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2VALUE_Pos (30U)
+#define COMP_CSR_COMP2VALUE_Msk (0x1UL << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK_Pos (31U)
+#define COMP_CSR_COMP2LOCK_Msk (0x1UL << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
+
+/********************** Bit definition for COMP_CSR register common ****************/
+#define COMP_CSR_COMPxEN_Pos (0U)
+#define COMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
+#define COMP_CSR_COMPxPOLARITY_Pos (15U)
+#define COMP_CSR_COMPxPOLARITY_Msk (0x1UL << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */
+#define COMP_CSR_COMPxOUTVALUE_Pos (30U)
+#define COMP_CSR_COMPxOUTVALUE_Msk (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK_Pos (31U)
+#define COMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
+
+/* Reference defines */
+#define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR (0xFFU) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos (3U)
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos (5U)
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos (7U)
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT_Pos (0U)
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL_Pos (0U)
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* CRS Clock Recovery System */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRS_CR register *********************/
+#define CRS_CR_SYNCOKIE_Pos (0U)
+#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
+#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /* SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE_Pos (1U)
+#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
+#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /* SYNC warning interrupt enable */
+#define CRS_CR_ERRIE_Pos (2U)
+#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
+#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /* SYNC error interrupt enable */
+#define CRS_CR_ESYNCIE_Pos (3U)
+#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
+#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /* Expected SYNC(ESYNCF) interrupt Enable*/
+#define CRS_CR_CEN_Pos (5U)
+#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
+#define CRS_CR_CEN CRS_CR_CEN_Msk /* Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN_Pos (6U)
+#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
+#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /* Automatic trimming enable */
+#define CRS_CR_SWSYNC_Pos (7U)
+#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
+#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /* A Software SYNC event is generated */
+#define CRS_CR_TRIM_Pos (8U)
+#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
+#define CRS_CR_TRIM CRS_CR_TRIM_Msk /* HSI48 oscillator smooth trimming */
+
+/******************* Bit definition for CRS_CFGR register *********************/
+#define CRS_CFGR_RELOAD_Pos (0U)
+#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
+#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /* Counter reload value */
+#define CRS_CFGR_FELIM_Pos (16U)
+#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
+#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /* Frequency error limit */
+
+#define CRS_CFGR_SYNCDIV_Pos (24U)
+#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
+#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /* SYNC divider */
+#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
+#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
+#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
+
+#define CRS_CFGR_SYNCSRC_Pos (28U)
+#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
+#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /* SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
+#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
+
+#define CRS_CFGR_SYNCPOL_Pos (31U)
+#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
+#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /* SYNC polarity selection */
+
+/******************* Bit definition for CRS_ISR register *********************/
+#define CRS_ISR_SYNCOKF_Pos (0U)
+#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
+#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /* SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF_Pos (1U)
+#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
+#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /* SYNC warning */
+#define CRS_ISR_ERRF_Pos (2U)
+#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
+#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /* SYNC error flag */
+#define CRS_ISR_ESYNCF_Pos (3U)
+#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
+#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /* Expected SYNC flag */
+#define CRS_ISR_SYNCERR_Pos (8U)
+#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
+#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /* SYNC error */
+#define CRS_ISR_SYNCMISS_Pos (9U)
+#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
+#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /* SYNC missed */
+#define CRS_ISR_TRIMOVF_Pos (10U)
+#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
+#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /* Trimming overflow or underflow */
+#define CRS_ISR_FEDIR_Pos (15U)
+#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
+#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /* Frequency error direction */
+#define CRS_ISR_FECAP_Pos (16U)
+#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
+#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /* Frequency error capture */
+
+/******************* Bit definition for CRS_ICR register *********************/
+#define CRS_ICR_SYNCOKC_Pos (0U)
+#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
+#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /* SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC_Pos (1U)
+#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
+#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /* SYNC warning clear flag */
+#define CRS_ICR_ERRC_Pos (2U)
+#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
+#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /* Error clear flag */
+#define CRS_ICR_ESYNCC_Pos (3U)
+#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
+#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /* Expected SYNC clear flag */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter (DAC) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos (1U)
+#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos (2U)
+#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (3U)
+#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos (13U)
+#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun interrupt enable */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1_Pos (13U)
+#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_Pos (0U)
+#define DBGMCU_CR_DBG_Msk (0x7UL << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
+#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+
+/******************* Bit definition for DMA_CSELR register *******************/
+#define DMA_CSELR_C1S_Pos (0U)
+#define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
+#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos (4U)
+#define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
+#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos (8U)
+#define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
+#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos (12U)
+#define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
+#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos (16U)
+#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
+#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S_Pos (20U)
+#define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
+#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S_Pos (24U)
+#define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
+#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_IM0_Pos (0U)
+#define EXTI_IMR_IM0_Msk (0x1UL << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_IM1_Pos (1U)
+#define EXTI_IMR_IM1_Msk (0x1UL << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_IM2_Pos (2U)
+#define EXTI_IMR_IM2_Msk (0x1UL << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_IM3_Pos (3U)
+#define EXTI_IMR_IM3_Msk (0x1UL << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_IM4_Pos (4U)
+#define EXTI_IMR_IM4_Msk (0x1UL << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_IM5_Pos (5U)
+#define EXTI_IMR_IM5_Msk (0x1UL << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_IM6_Pos (6U)
+#define EXTI_IMR_IM6_Msk (0x1UL << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_IM7_Pos (7U)
+#define EXTI_IMR_IM7_Msk (0x1UL << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_IM8_Pos (8U)
+#define EXTI_IMR_IM8_Msk (0x1UL << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_IM9_Pos (9U)
+#define EXTI_IMR_IM9_Msk (0x1UL << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_IM10_Pos (10U)
+#define EXTI_IMR_IM10_Msk (0x1UL << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_IM11_Pos (11U)
+#define EXTI_IMR_IM11_Msk (0x1UL << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_IM12_Pos (12U)
+#define EXTI_IMR_IM12_Msk (0x1UL << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_IM13_Pos (13U)
+#define EXTI_IMR_IM13_Msk (0x1UL << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_IM14_Pos (14U)
+#define EXTI_IMR_IM14_Msk (0x1UL << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_IM15_Pos (15U)
+#define EXTI_IMR_IM15_Msk (0x1UL << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_IM16_Pos (16U)
+#define EXTI_IMR_IM16_Msk (0x1UL << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_IM17_Pos (17U)
+#define EXTI_IMR_IM17_Msk (0x1UL << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_IM18_Pos (18U)
+#define EXTI_IMR_IM18_Msk (0x1UL << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_IM19_Pos (19U)
+#define EXTI_IMR_IM19_Msk (0x1UL << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_IM20_Pos (20U)
+#define EXTI_IMR_IM20_Msk (0x1UL << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_IM21_Pos (21U)
+#define EXTI_IMR_IM21_Msk (0x1UL << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_IM22_Pos (22U)
+#define EXTI_IMR_IM22_Msk (0x1UL << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_IM23_Pos (23U)
+#define EXTI_IMR_IM23_Msk (0x1UL << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
+#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_IM25_Pos (25U)
+#define EXTI_IMR_IM25_Msk (0x1UL << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */
+#define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_IM26_Pos (26U)
+#define EXTI_IMR_IM26_Msk (0x1UL << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
+#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_IM28_Pos (28U)
+#define EXTI_IMR_IM28_Msk (0x1UL << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
+#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_IM29_Pos (29U)
+#define EXTI_IMR_IM29_Msk (0x1UL << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
+#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
+
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x36FFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x36FFFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_EM0_Pos (0U)
+#define EXTI_EMR_EM0_Msk (0x1UL << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_EM1_Pos (1U)
+#define EXTI_EMR_EM1_Msk (0x1UL << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_EM2_Pos (2U)
+#define EXTI_EMR_EM2_Msk (0x1UL << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_EM3_Pos (3U)
+#define EXTI_EMR_EM3_Msk (0x1UL << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_EM4_Pos (4U)
+#define EXTI_EMR_EM4_Msk (0x1UL << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_EM5_Pos (5U)
+#define EXTI_EMR_EM5_Msk (0x1UL << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_EM6_Pos (6U)
+#define EXTI_EMR_EM6_Msk (0x1UL << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_EM7_Pos (7U)
+#define EXTI_EMR_EM7_Msk (0x1UL << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_EM8_Pos (8U)
+#define EXTI_EMR_EM8_Msk (0x1UL << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_EM9_Pos (9U)
+#define EXTI_EMR_EM9_Msk (0x1UL << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_EM10_Pos (10U)
+#define EXTI_EMR_EM10_Msk (0x1UL << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_EM11_Pos (11U)
+#define EXTI_EMR_EM11_Msk (0x1UL << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_EM12_Pos (12U)
+#define EXTI_EMR_EM12_Msk (0x1UL << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_EM13_Pos (13U)
+#define EXTI_EMR_EM13_Msk (0x1UL << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_EM14_Pos (14U)
+#define EXTI_EMR_EM14_Msk (0x1UL << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_EM15_Pos (15U)
+#define EXTI_EMR_EM15_Msk (0x1UL << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_EM16_Pos (16U)
+#define EXTI_EMR_EM16_Msk (0x1UL << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_EM17_Pos (17U)
+#define EXTI_EMR_EM17_Msk (0x1UL << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_EM18_Pos (18U)
+#define EXTI_EMR_EM18_Msk (0x1UL << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_EM19_Pos (19U)
+#define EXTI_EMR_EM19_Msk (0x1UL << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_EM20_Pos (20U)
+#define EXTI_EMR_EM20_Msk (0x1UL << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_EM21_Pos (21U)
+#define EXTI_EMR_EM21_Msk (0x1UL << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_EM22_Pos (22U)
+#define EXTI_EMR_EM22_Msk (0x1UL << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */
+#define EXTI_EMR_EM23_Pos (23U)
+#define EXTI_EMR_EM23_Msk (0x1UL << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
+#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
+#define EXTI_EMR_EM25_Pos (25U)
+#define EXTI_EMR_EM25_Msk (0x1UL << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */
+#define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */
+#define EXTI_EMR_EM26_Pos (26U)
+#define EXTI_EMR_EM26_Msk (0x1UL << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
+#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
+#define EXTI_EMR_EM28_Pos (28U)
+#define EXTI_EMR_EM28_Msk (0x1UL << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
+#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
+#define EXTI_EMR_EM29_Pos (29U)
+#define EXTI_EMR_EM29_Msk (0x1UL << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
+#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_RT0_Pos (0U)
+#define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_RT1_Pos (1U)
+#define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_RT2_Pos (2U)
+#define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_RT3_Pos (3U)
+#define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_RT4_Pos (4U)
+#define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_RT5_Pos (5U)
+#define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_RT6_Pos (6U)
+#define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_RT7_Pos (7U)
+#define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_RT8_Pos (8U)
+#define EXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_RT9_Pos (9U)
+#define EXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_RT10_Pos (10U)
+#define EXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_RT11_Pos (11U)
+#define EXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_RT12_Pos (12U)
+#define EXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_RT13_Pos (13U)
+#define EXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_RT14_Pos (14U)
+#define EXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_RT15_Pos (15U)
+#define EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_RT16_Pos (16U)
+#define EXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_RT17_Pos (17U)
+#define EXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_RT19_Pos (19U)
+#define EXTI_RTSR_RT19_Msk (0x1UL << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_RT20_Pos (20U)
+#define EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_RT21_Pos (21U)
+#define EXTI_RTSR_RT21_Msk (0x1UL << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_RT22_Pos (22U)
+#define EXTI_RTSR_RT22_Msk (0x1UL << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
+#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
+#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
+#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
+#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
+#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
+#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
+#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
+#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
+#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
+#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
+#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
+#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
+#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
+#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
+#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
+#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
+#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
+#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
+#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
+#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
+#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_FT0_Pos (0U)
+#define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_FT1_Pos (1U)
+#define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_FT2_Pos (2U)
+#define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_FT3_Pos (3U)
+#define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_FT4_Pos (4U)
+#define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_FT5_Pos (5U)
+#define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_FT6_Pos (6U)
+#define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_FT7_Pos (7U)
+#define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_FT8_Pos (8U)
+#define EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_FT9_Pos (9U)
+#define EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_FT10_Pos (10U)
+#define EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_FT11_Pos (11U)
+#define EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_FT12_Pos (12U)
+#define EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_FT13_Pos (13U)
+#define EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_FT14_Pos (14U)
+#define EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_FT15_Pos (15U)
+#define EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_FT16_Pos (16U)
+#define EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_FT17_Pos (17U)
+#define EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_FT19_Pos (19U)
+#define EXTI_FTSR_FT19_Msk (0x1UL << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_FT20_Pos (20U)
+#define EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_FT21_Pos (21U)
+#define EXTI_FTSR_FT21_Msk (0x1UL << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_FT22_Pos (22U)
+#define EXTI_FTSR_FT22_Msk (0x1UL << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
+#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
+#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
+#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
+#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
+#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
+#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
+#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
+#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
+#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
+#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
+#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
+#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
+#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
+#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
+#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
+#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
+#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
+#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
+#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
+#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
+#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWI0_Pos (0U)
+#define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWI1_Pos (1U)
+#define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWI2_Pos (2U)
+#define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWI3_Pos (3U)
+#define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWI4_Pos (4U)
+#define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWI5_Pos (5U)
+#define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWI6_Pos (6U)
+#define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWI7_Pos (7U)
+#define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWI8_Pos (8U)
+#define EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWI9_Pos (9U)
+#define EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWI10_Pos (10U)
+#define EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWI11_Pos (11U)
+#define EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWI12_Pos (12U)
+#define EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWI13_Pos (13U)
+#define EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWI14_Pos (14U)
+#define EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWI15_Pos (15U)
+#define EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWI16_Pos (16U)
+#define EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWI17_Pos (17U)
+#define EXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWI19_Pos (19U)
+#define EXTI_SWIER_SWI19_Msk (0x1UL << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWI20_Pos (20U)
+#define EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWI21_Pos (21U)
+#define EXTI_SWIER_SWI21_Msk (0x1UL << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWI22_Pos (22U)
+#define EXTI_SWIER_SWI22_Msk (0x1UL << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
+
+/* Legacy defines */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PIF0_Pos (0U)
+#define EXTI_PR_PIF0_Msk (0x1UL << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
+#define EXTI_PR_PIF1_Pos (1U)
+#define EXTI_PR_PIF1_Msk (0x1UL << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
+#define EXTI_PR_PIF2_Pos (2U)
+#define EXTI_PR_PIF2_Msk (0x1UL << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
+#define EXTI_PR_PIF3_Pos (3U)
+#define EXTI_PR_PIF3_Msk (0x1UL << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
+#define EXTI_PR_PIF4_Pos (4U)
+#define EXTI_PR_PIF4_Msk (0x1UL << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
+#define EXTI_PR_PIF5_Pos (5U)
+#define EXTI_PR_PIF5_Msk (0x1UL << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
+#define EXTI_PR_PIF6_Pos (6U)
+#define EXTI_PR_PIF6_Msk (0x1UL << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
+#define EXTI_PR_PIF7_Pos (7U)
+#define EXTI_PR_PIF7_Msk (0x1UL << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
+#define EXTI_PR_PIF8_Pos (8U)
+#define EXTI_PR_PIF8_Msk (0x1UL << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
+#define EXTI_PR_PIF9_Pos (9U)
+#define EXTI_PR_PIF9_Msk (0x1UL << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
+#define EXTI_PR_PIF10_Pos (10U)
+#define EXTI_PR_PIF10_Msk (0x1UL << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
+#define EXTI_PR_PIF11_Pos (11U)
+#define EXTI_PR_PIF11_Msk (0x1UL << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
+#define EXTI_PR_PIF12_Pos (12U)
+#define EXTI_PR_PIF12_Msk (0x1UL << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
+#define EXTI_PR_PIF13_Pos (13U)
+#define EXTI_PR_PIF13_Msk (0x1UL << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
+#define EXTI_PR_PIF14_Pos (14U)
+#define EXTI_PR_PIF14_Msk (0x1UL << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
+#define EXTI_PR_PIF15_Pos (15U)
+#define EXTI_PR_PIF15_Msk (0x1UL << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
+#define EXTI_PR_PIF16_Pos (16U)
+#define EXTI_PR_PIF16_Msk (0x1UL << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
+#define EXTI_PR_PIF17_Pos (17U)
+#define EXTI_PR_PIF17_Msk (0x1UL << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
+#define EXTI_PR_PIF19_Pos (19U)
+#define EXTI_PR_PIF19_Msk (0x1UL << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
+#define EXTI_PR_PIF20_Pos (20U)
+#define EXTI_PR_PIF20_Msk (0x1UL << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
+#define EXTI_PR_PIF21_Pos (21U)
+#define EXTI_PR_PIF21_Msk (0x1UL << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
+#define EXTI_PR_PIF22_Pos (22U)
+#define EXTI_PR_PIF22_Msk (0x1UL << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
+
+/* Legacy defines */
+#define EXTI_PR_PR0 EXTI_PR_PIF0
+#define EXTI_PR_PR1 EXTI_PR_PIF1
+#define EXTI_PR_PR2 EXTI_PR_PIF2
+#define EXTI_PR_PR3 EXTI_PR_PIF3
+#define EXTI_PR_PR4 EXTI_PR_PIF4
+#define EXTI_PR_PR5 EXTI_PR_PIF5
+#define EXTI_PR_PR6 EXTI_PR_PIF6
+#define EXTI_PR_PR7 EXTI_PR_PIF7
+#define EXTI_PR_PR8 EXTI_PR_PIF8
+#define EXTI_PR_PR9 EXTI_PR_PIF9
+#define EXTI_PR_PR10 EXTI_PR_PIF10
+#define EXTI_PR_PR11 EXTI_PR_PIF11
+#define EXTI_PR_PR12 EXTI_PR_PIF12
+#define EXTI_PR_PR13 EXTI_PR_PIF13
+#define EXTI_PR_PR14 EXTI_PR_PIF14
+#define EXTI_PR_PR15 EXTI_PR_PIF15
+#define EXTI_PR_PR16 EXTI_PR_PIF16
+#define EXTI_PR_PR17 EXTI_PR_PIF17
+#define EXTI_PR_PR19 EXTI_PR_PIF19
+#define EXTI_PR_PR20 EXTI_PR_PIF20
+#define EXTI_PR_PR21 EXTI_PR_PIF21
+#define EXTI_PR_PR22 EXTI_PR_PIF22
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
+#define FLASH_ACR_PRFTEN_Pos (1U)
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_SLEEP_PD_Pos (3U)
+#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD_Pos (4U)
+#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
+#define FLASH_ACR_DISAB_BUF_Pos (5U)
+#define FLASH_ACR_DISAB_BUF_Msk (0x1UL << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
+#define FLASH_ACR_PRE_READ_Pos (6U)
+#define FLASH_ACR_PRE_READ_Msk (0x1UL << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
+#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
+
+/******************* Bit definition for FLASH_PECR register ******************/
+#define FLASH_PECR_PELOCK_Pos (0U)
+#define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
+#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK_Pos (1U)
+#define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
+#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK_Pos (2U)
+#define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
+#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG_Pos (3U)
+#define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
+#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
+#define FLASH_PECR_DATA_Pos (4U)
+#define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
+#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
+#define FLASH_PECR_FIX_Pos (8U)
+#define FLASH_PECR_FIX_Msk (0x1UL << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
+#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE_Pos (9U)
+#define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
+#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
+#define FLASH_PECR_FPRG_Pos (10U)
+#define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
+#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_EOPIE_Pos (16U)
+#define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
+#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
+#define FLASH_PECR_ERRIE_Pos (17U)
+#define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
+#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
+#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
+#define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
+#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
+#define FLASH_PECR_HALF_ARRAY_Pos (19U)
+#define FLASH_PECR_HALF_ARRAY_Msk (0x1UL << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
+#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
+
+/****************** Bit definition for FLASH_PDKEYR register ******************/
+#define FLASH_PDKEYR_PDKEYR_Pos (0U)
+#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PEKEYR register ******************/
+#define FLASH_PEKEYR_PEKEYR_Pos (0U)
+#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PRGKEYR register ******************/
+#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
+#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
+
+/****************** Bit definition for FLASH_OPTKEYR register ******************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_EOP_Pos (1U)
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
+#define FLASH_SR_HVOFF_Pos (2U)
+#define FLASH_SR_HVOFF_Msk (0x1UL << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
+#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
+#define FLASH_SR_READY_Pos (3U)
+#define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */
+#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR_Pos (8U)
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
+#define FLASH_SR_PGAERR_Pos (9U)
+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR_Pos (10U)
+#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
+#define FLASH_SR_OPTVERR_Pos (11U)
+#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
+#define FLASH_SR_RDERR_Pos (13U)
+#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
+#define FLASH_SR_NOTZEROERR_Pos (16U)
+#define FLASH_SR_NOTZEROERR_Msk (0x1UL << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
+#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
+#define FLASH_SR_FWWERR_Pos (17U)
+#define FLASH_SR_FWWERR_Msk (0x1UL << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
+#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
+
+/* Legacy defines */
+#define FLASH_SR_FWWER FLASH_SR_FWWERR
+#define FLASH_SR_ENHV FLASH_SR_HVOFF
+#define FLASH_SR_ENDHV FLASH_SR_HVOFF
+
+/****************** Bit definition for FLASH_OPTR register *******************/
+#define FLASH_OPTR_RDPROT_Pos (0U)
+#define FLASH_OPTR_RDPROT_Msk (0xFFUL << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
+#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
+#define FLASH_OPTR_WPRMOD_Pos (8U)
+#define FLASH_OPTR_WPRMOD_Msk (0x1UL << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
+#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
+#define FLASH_OPTR_BOR_LEV_Pos (16U)
+#define FLASH_OPTR_BOR_LEV_Msk (0xFUL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
+#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OPTR_IWDG_SW_Pos (20U)
+#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
+#define FLASH_OPTR_nRST_STOP_Pos (21U)
+#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OPTR_nRST_STDBY_Pos (22U)
+#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OPTR_USER_Pos (20U)
+#define FLASH_OPTR_USER_Msk (0x7UL << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
+#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OPTR_BOOT1_Pos (31U)
+#define FLASH_OPTR_BOOT1_Msk (0x1UL << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
+#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 (0x00000001U)
+#define GPIO_OTYPER_OT_1 (0x00000002U)
+#define GPIO_OTYPER_OT_2 (0x00000004U)
+#define GPIO_OTYPER_OT_3 (0x00000008U)
+#define GPIO_OTYPER_OT_4 (0x00000010U)
+#define GPIO_OTYPER_OT_5 (0x00000020U)
+#define GPIO_OTYPER_OT_6 (0x00000040U)
+#define GPIO_OTYPER_OT_7 (0x00000080U)
+#define GPIO_OTYPER_OT_8 (0x00000100U)
+#define GPIO_OTYPER_OT_9 (0x00000200U)
+#define GPIO_OTYPER_OT_10 (0x00000400U)
+#define GPIO_OTYPER_OT_11 (0x00000800U)
+#define GPIO_OTYPER_OT_12 (0x00001000U)
+#define GPIO_OTYPER_OT_13 (0x00002000U)
+#define GPIO_OTYPER_OT_14 (0x00004000U)
+#define GPIO_OTYPER_OT_15 (0x00008000U)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDER_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
+#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDER_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
+#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDER_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
+#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDER_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
+#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDER_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
+#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDER_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
+#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDER_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
+#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDER_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
+#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDER_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
+#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDER_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
+#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDER_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
+#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDER_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
+#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDER_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
+#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDER_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
+#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDER_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
+#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDER_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
+#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 (0x00000001U)
+#define GPIO_BSRR_BS_1 (0x00000002U)
+#define GPIO_BSRR_BS_2 (0x00000004U)
+#define GPIO_BSRR_BS_3 (0x00000008U)
+#define GPIO_BSRR_BS_4 (0x00000010U)
+#define GPIO_BSRR_BS_5 (0x00000020U)
+#define GPIO_BSRR_BS_6 (0x00000040U)
+#define GPIO_BSRR_BS_7 (0x00000080U)
+#define GPIO_BSRR_BS_8 (0x00000100U)
+#define GPIO_BSRR_BS_9 (0x00000200U)
+#define GPIO_BSRR_BS_10 (0x00000400U)
+#define GPIO_BSRR_BS_11 (0x00000800U)
+#define GPIO_BSRR_BS_12 (0x00001000U)
+#define GPIO_BSRR_BS_13 (0x00002000U)
+#define GPIO_BSRR_BS_14 (0x00004000U)
+#define GPIO_BSRR_BS_15 (0x00008000U)
+#define GPIO_BSRR_BR_0 (0x00010000U)
+#define GPIO_BSRR_BR_1 (0x00020000U)
+#define GPIO_BSRR_BR_2 (0x00040000U)
+#define GPIO_BSRR_BR_3 (0x00080000U)
+#define GPIO_BSRR_BR_4 (0x00100000U)
+#define GPIO_BSRR_BR_5 (0x00200000U)
+#define GPIO_BSRR_BR_6 (0x00400000U)
+#define GPIO_BSRR_BR_7 (0x00800000U)
+#define GPIO_BSRR_BR_8 (0x01000000U)
+#define GPIO_BSRR_BR_9 (0x02000000U)
+#define GPIO_BSRR_BR_10 (0x04000000U)
+#define GPIO_BSRR_BR_11 (0x08000000U)
+#define GPIO_BSRR_BR_12 (0x10000000U)
+#define GPIO_BSRR_BR_13 (0x20000000U)
+#define GPIO_BSRR_BR_14 (0x40000000U)
+#define GPIO_BSRR_BR_15 (0x80000000U)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 (0x00000001U)
+#define GPIO_BRR_BR_1 (0x00000002U)
+#define GPIO_BRR_BR_2 (0x00000004U)
+#define GPIO_BRR_BR_3 (0x00000008U)
+#define GPIO_BRR_BR_4 (0x00000010U)
+#define GPIO_BRR_BR_5 (0x00000020U)
+#define GPIO_BRR_BR_6 (0x00000040U)
+#define GPIO_BRR_BR_7 (0x00000080U)
+#define GPIO_BRR_BR_8 (0x00000100U)
+#define GPIO_BRR_BR_9 (0x00000200U)
+#define GPIO_BRR_BR_10 (0x00000400U)
+#define GPIO_BRR_BR_11 (0x00000800U)
+#define GPIO_BRR_BR_12 (0x00001000U)
+#define GPIO_BRR_BR_13 (0x00002000U)
+#define GPIO_BRR_BR_14 (0x00004000U)
+#define GPIO_BRR_BR_15 (0x00008000U)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos (1U)
+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos (2U)
+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos (3U)
+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos (4U)
+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos (5U)
+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos (6U)
+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos (7U)
+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos (8U)
+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos (12U)
+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos (14U)
+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos (15U)
+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos (16U)
+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos (17U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos (18U)
+#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos (19U)
+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos (20U)
+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos (21U)
+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos (22U)
+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos (23U)
+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD_Pos (0U)
+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos (10U)
+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos (11U)
+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos (12U)
+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos (13U)
+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
+#define I2C_CR2_STOP_Pos (14U)
+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos (15U)
+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos (16U)
+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos (24U)
+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos (25U)
+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos (26U)
+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1_Pos (0U)
+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos (10U)
+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos (15U)
+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2_Pos (1U)
+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos (8U)
+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos (8U)
+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos (9U)
+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos (8U)
+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos (10U)
+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos (8U)
+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos (9U)
+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos (8U)
+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos (15U)
+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos (0U)
+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos (8U)
+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos (16U)
+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos (20U)
+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos (28U)
+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE_Pos (0U)
+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos (1U)
+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos (2U)
+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos (3U)
+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos (4U)
+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos (5U)
+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos (6U)
+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos (7U)
+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos (8U)
+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
+#define I2C_ISR_ARLO_Pos (9U)
+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos (10U)
+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos (11U)
+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos (12U)
+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos (13U)
+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos (15U)
+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
+#define I2C_ISR_DIR_Pos (16U)
+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos (17U)
+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF_Pos (3U)
+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos (4U)
+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos (5U)
+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos (8U)
+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos (9U)
+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos (10U)
+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos (11U)
+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos (12U)
+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos (13U)
+#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define I2C_PECR_PEC_Pos (0U)
+#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA_Pos (0U)
+#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA_Pos (0U)
+#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos (2U)
+#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN_Pos (0U)
+#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM_Pos (0U)
+#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos (1U)
+#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos (2U)
+#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos (3U)
+#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos (4U)
+#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos (5U)
+#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos (6U)
+#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF_Pos (0U)
+#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos (1U)
+#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos (3U)
+#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos (4U)
+#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos (5U)
+#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos (6U)
+#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos (0U)
+#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos (1U)
+#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos (3U)
+#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos (4U)
+#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos (5U)
+#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos (6U)
+#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos (0U)
+#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos (1U)
+#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos (3U)
+#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos (6U)
+#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos (9U)
+#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos (17U)
+#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos (19U)
+#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos (20U)
+#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos (21U)
+#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos (22U)
+#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos (24U)
+#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE_Pos (0U)
+#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos (1U)
+#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos (2U)
+#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP_Pos (0U)
+#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR_Pos (0U)
+#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT_Pos (0U)
+#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
+
+/******************************************************************************/
+/* */
+/* MIFARE Firewall */
+/* */
+/******************************************************************************/
+
+/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
+#define FW_CSSA_ADD_Pos (8U)
+#define FW_CSSA_ADD_Msk (0xFFFFUL << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
+#define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
+#define FW_CSL_LENG_Pos (8U)
+#define FW_CSL_LENG_Msk (0x3FFFUL << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
+#define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
+#define FW_NVDSSA_ADD_Pos (8U)
+#define FW_NVDSSA_ADD_Msk (0xFFFFUL << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
+#define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
+#define FW_NVDSL_LENG_Pos (8U)
+#define FW_NVDSL_LENG_Msk (0x3FFFUL << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
+#define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
+#define FW_VDSSA_ADD_Pos (6U)
+#define FW_VDSSA_ADD_Msk (0x3FFUL << FW_VDSSA_ADD_Pos) /*!< 0x0000FFC0 */
+#define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
+#define FW_VDSL_LENG_Pos (6U)
+#define FW_VDSL_LENG_Msk (0x3FFUL << FW_VDSL_LENG_Pos) /*!< 0x0000FFC0 */
+#define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
+
+/**************************Bit definition for CR register *********************/
+#define FW_CR_FPA_Pos (0U)
+#define FW_CR_FPA_Msk (0x1UL << FW_CR_FPA_Pos) /*!< 0x00000001 */
+#define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
+#define FW_CR_VDS_Pos (1U)
+#define FW_CR_VDS_Msk (0x1UL << FW_CR_VDS_Pos) /*!< 0x00000002 */
+#define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
+#define FW_CR_VDE_Pos (2U)
+#define FW_CR_VDE_Msk (0x1UL << FW_CR_VDE_Pos) /*!< 0x00000004 */
+#define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
+
+/******************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/******************************************************************************/
+
+#define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPSDSR_Pos (0U)
+#define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP_Pos (9U)
+#define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /*!< 0x00000200 */
+#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
+#define PWR_CR_FWU_Pos (10U)
+#define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /*!< 0x00000400 */
+#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
+
+#define PWR_CR_VOS_Pos (11U)
+#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x00001800 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /*!< 0x00000800 */
+#define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /*!< 0x00001000 */
+#define PWR_CR_DSEEKOFF_Pos (13U)
+#define PWR_CR_DSEEKOFF_Msk (0x1UL << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */
+#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */
+#define PWR_CR_LPRUN_Pos (14U)
+#define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
+#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF_Pos (3U)
+#define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
+#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF_Pos (4U)
+#define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
+#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF_Pos (5U)
+#define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
+#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1_Pos (8U)
+#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2_Pos (9U)
+#define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
+#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+#define RCC_HSI48_SUPPORT /*!< HSI48 feature support */
+#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos (1U)
+#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos (2U)
+#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIVEN_Pos (3U)
+#define RCC_CR_HSIDIVEN_Msk (0x1UL << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */
+#define RCC_CR_HSIDIVF_Pos (4U)
+#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */
+#define RCC_CR_MSION_Pos (8U)
+#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000100 */
+#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY_Pos (9U)
+#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
+#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON_Pos (19U)
+#define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */
+#define RCC_CR_RTCPRE_Pos (20U)
+#define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
+#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */
+#define RCC_CR_RTCPRE_0 (0x1UL << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */
+#define RCC_CR_RTCPRE_1 (0x2UL << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+/* Reference defines */
+#define RCC_CR_CSSON RCC_CR_CSSHSEON
+
+/******************** Bit definition for RCC_ICSCR register *****************/
+#define RCC_ICSCR_HSICAL_Pos (0U)
+#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
+#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM_Pos (8U)
+#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
+#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE_Pos (13U)
+#define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
+#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
+#define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
+#define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
+#define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
+#define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
+#define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
+#define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
+#define RCC_ICSCR_MSICAL_Pos (16U)
+#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
+#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM_Pos (24U)
+#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
+#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
+
+/******************** Bit definition for RCC_CRRCR register *****************/
+#define RCC_CRRCR_HSI48ON_Pos (0U)
+#define RCC_CRRCR_HSI48ON_Msk (0x1UL << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
+#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk /*!< HSI 48MHz clock enable */
+#define RCC_CRRCR_HSI48RDY_Pos (1U)
+#define RCC_CRRCR_HSI48RDY_Msk (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
+#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk /*!< HSI 48MHz clock ready flag */
+#define RCC_CRRCR_HSI48CAL_Pos (8U)
+#define RCC_CRRCR_HSI48CAL_Msk (0xFFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI 48MHz clock Calibration */
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos (15U)
+#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */
+
+/*!< PLL entry clock source*/
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
+
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL_Pos (18U)
+#define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV_Pos (22U)
+#define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
+
+#define RCC_CFGR_PLLDIV2_Pos (22U)
+#define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3_Pos (23U)
+#define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4_Pos (22U)
+#define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCOSEL_Pos (24U)
+#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
+#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
+
+#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
+#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCOSEL_HSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_MSI_Pos (24U)
+#define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
+#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_HSE_Pos (26U)
+#define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCOSEL_PLL_Pos (24U)
+#define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
+#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
+#define RCC_CFGR_MCOSEL_LSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
+#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
+#define RCC_CFGR_MCOSEL_LSE_Pos (24U)
+#define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
+#define RCC_CFGR_MCOSEL_HSI48_Pos (27U)
+#define RCC_CFGR_MCOSEL_HSI48_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */
+#define RCC_CFGR_MCOSEL_HSI48 RCC_CFGR_MCOSEL_HSI48_Msk /*!< HSI48 clock selected as MCO source */
+
+#define RCC_CFGR_MCOPRE_Pos (28U)
+#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
+
+#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
+
+/* Legacy defines */
+#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
+#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
+#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
+#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
+#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
+#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
+#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
+#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
+#ifdef RCC_CFGR_MCOSEL_HSI48
+#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48
+#endif
+
+#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
+#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
+
+/*!<****************** Bit definition for RCC_CIER register ********************/
+#define RCC_CIER_LSIRDYIE_Pos (0U)
+#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIER_LSERDYIE_Pos (1U)
+#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIER_HSIRDYIE_Pos (2U)
+#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIER_HSERDYIE_Pos (3U)
+#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIER_PLLRDYIE_Pos (4U)
+#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIER_MSIRDYIE_Pos (5U)
+#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
+#define RCC_CIER_HSI48RDYIE_Pos (6U)
+#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000040 */
+#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk /*!< HSI48 Ready Interrupt Enable */
+#define RCC_CIER_CSSLSE_Pos (7U)
+#define RCC_CIER_CSSLSE_Msk (0x1UL << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */
+
+/* Reference defines */
+#define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
+
+/*!<****************** Bit definition for RCC_CIFR register ********************/
+#define RCC_CIFR_LSIRDYF_Pos (0U)
+#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIFR_LSERDYF_Pos (1U)
+#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIFR_HSIRDYF_Pos (2U)
+#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIFR_HSERDYF_Pos (3U)
+#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIFR_PLLRDYF_Pos (4U)
+#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIFR_MSIRDYF_Pos (5U)
+#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
+#define RCC_CIFR_HSI48RDYF_Pos (6U)
+#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk /*!< HSI48 Ready Interrupt flag */
+#define RCC_CIFR_CSSLSEF_Pos (7U)
+#define RCC_CIFR_CSSLSEF_Msk (0x1UL << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */
+#define RCC_CIFR_CSSHSEF_Pos (8U)
+#define RCC_CIFR_CSSHSEF_Msk (0x1UL << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */
+#define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */
+
+/* Reference defines */
+#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
+#define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
+
+/*!<****************** Bit definition for RCC_CICR register ********************/
+#define RCC_CICR_LSIRDYC_Pos (0U)
+#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CICR_LSERDYC_Pos (1U)
+#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CICR_HSIRDYC_Pos (2U)
+#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CICR_HSERDYC_Pos (3U)
+#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CICR_PLLRDYC_Pos (4U)
+#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CICR_MSIRDYC_Pos (5U)
+#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
+#define RCC_CICR_HSI48RDYC_Pos (6U)
+#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000040 */
+#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk /*!< HSI48 Ready Interrupt Clear */
+#define RCC_CICR_CSSLSEC_Pos (7U)
+#define RCC_CICR_CSSLSEC_Msk (0x1UL << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */
+#define RCC_CICR_CSSHSEC_Pos (8U)
+#define RCC_CICR_CSSHSEC_Msk (0x1UL << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */
+#define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */
+
+/* Reference defines */
+#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
+#define RCC_CICR_CSSC RCC_CICR_CSSHSEC
+/***************** Bit definition for RCC_IOPRSTR register ******************/
+#define RCC_IOPRSTR_IOPARST_Pos (0U)
+#define RCC_IOPRSTR_IOPARST_Msk (0x1UL << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */
+#define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */
+#define RCC_IOPRSTR_IOPBRST_Pos (1U)
+#define RCC_IOPRSTR_IOPBRST_Msk (0x1UL << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */
+#define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */
+#define RCC_IOPRSTR_IOPCRST_Pos (2U)
+#define RCC_IOPRSTR_IOPCRST_Msk (0x1UL << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */
+#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */
+#define RCC_IOPRSTR_IOPDRST_Pos (3U)
+#define RCC_IOPRSTR_IOPDRST_Msk (0x1UL << RCC_IOPRSTR_IOPDRST_Pos) /*!< 0x00000008 */
+#define RCC_IOPRSTR_IOPDRST RCC_IOPRSTR_IOPDRST_Msk /*!< GPIO port D reset */
+#define RCC_IOPRSTR_IOPHRST_Pos (7U)
+#define RCC_IOPRSTR_IOPHRST_Msk (0x1UL << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */
+#define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */
+
+/* Reference defines */
+#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
+#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
+#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
+#define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_IOPDRST /*!< GPIO port D reset */
+#define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
+
+
+/****************** Bit definition for RCC_AHBRST register ******************/
+#define RCC_AHBRSTR_DMARST_Pos (0U)
+#define RCC_AHBRSTR_DMARST_Msk (0x1UL << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */
+#define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */
+#define RCC_AHBRSTR_MIFRST_Pos (8U)
+#define RCC_AHBRSTR_MIFRST_Msk (0x1UL << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */
+#define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset */
+#define RCC_AHBRSTR_CRCRST_Pos (12U)
+#define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */
+#define RCC_AHBRSTR_TSCRST_Pos (16U)
+#define RCC_AHBRSTR_TSCRST_Msk (0x1UL << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x00010000 */
+#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TSC reset */
+#define RCC_AHBRSTR_RNGRST_Pos (20U)
+#define RCC_AHBRSTR_RNGRST_Msk (0x1UL << RCC_AHBRSTR_RNGRST_Pos) /*!< 0x00100000 */
+#define RCC_AHBRSTR_RNGRST RCC_AHBRSTR_RNGRST_Msk /*!< RNG reset */
+#define RCC_AHBRSTR_CRYPRST_Pos (24U)
+#define RCC_AHBRSTR_CRYPRST_Msk (0x1UL << RCC_AHBRSTR_CRYPRST_Pos) /*!< 0x01000000 */
+#define RCC_AHBRSTR_CRYPRST RCC_AHBRSTR_CRYPRST_Msk /*!< Crypto reset */
+
+/* Reference defines */
+#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
+#define RCC_APB2RSTR_TIM21RST_Pos (2U)
+#define RCC_APB2RSTR_TIM21RST_Msk (0x1UL << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 reset */
+#define RCC_APB2RSTR_TIM22RST_Pos (5U)
+#define RCC_APB2RSTR_TIM22RST_Msk (0x1UL << RCC_APB2RSTR_TIM22RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk /*!< TIM22 reset */
+#define RCC_APB2RSTR_ADCRST_Pos (9U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
+#define RCC_APB2RSTR_DBGRST_Pos (22U)
+#define RCC_APB2RSTR_DBGRST_Msk (0x1UL << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU reset */
+
+/* Reference defines */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 reset */
+#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU reset */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_LPUART1RST_Pos (18U)
+#define RCC_APB1RSTR_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
+#define RCC_APB1RSTR_USBRST_Pos (23U)
+#define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */
+#define RCC_APB1RSTR_CRSRST_Pos (27U)
+#define RCC_APB1RSTR_CRSRST_Msk (0x1UL << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
+#define RCC_APB1RSTR_DACRST_Pos (29U)
+#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC reset */
+#define RCC_APB1RSTR_LPTIM1RST_Pos (31U)
+#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 reset */
+
+/***************** Bit definition for RCC_IOPENR register ******************/
+#define RCC_IOPENR_IOPAEN_Pos (0U)
+#define RCC_IOPENR_IOPAEN_Msk (0x1UL << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */
+#define RCC_IOPENR_IOPBEN_Pos (1U)
+#define RCC_IOPENR_IOPBEN_Msk (0x1UL << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */
+#define RCC_IOPENR_IOPCEN_Pos (2U)
+#define RCC_IOPENR_IOPCEN_Msk (0x1UL << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */
+#define RCC_IOPENR_IOPDEN_Pos (3U)
+#define RCC_IOPENR_IOPDEN_Msk (0x1UL << RCC_IOPENR_IOPDEN_Pos) /*!< 0x00000008 */
+#define RCC_IOPENR_IOPDEN RCC_IOPENR_IOPDEN_Msk /*!< GPIO port D clock enable */
+#define RCC_IOPENR_IOPHEN_Pos (7U)
+#define RCC_IOPENR_IOPHEN_Msk (0x1UL << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */
+
+/* Reference defines */
+#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
+#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
+#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
+#define RCC_IOPENR_GPIODEN RCC_IOPENR_IOPDEN /*!< GPIO port D clock enable */
+#define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
+
+/***************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMAEN_Pos (0U)
+#define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_MIFEN_Pos (8U)
+#define RCC_AHBENR_MIFEN_Msk (0x1UL << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */
+#define RCC_AHBENR_CRCEN_Pos (12U)
+#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+#define RCC_AHBENR_TSCEN_Pos (16U)
+#define RCC_AHBENR_TSCEN_Msk (0x1UL << RCC_AHBENR_TSCEN_Pos) /*!< 0x00010000 */
+#define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TSC clock enable */
+#define RCC_AHBENR_RNGEN_Pos (20U)
+#define RCC_AHBENR_RNGEN_Msk (0x1UL << RCC_AHBENR_RNGEN_Pos) /*!< 0x00100000 */
+#define RCC_AHBENR_RNGEN RCC_AHBENR_RNGEN_Msk /*!< RNG clock enable */
+#define RCC_AHBENR_CRYPEN_Pos (24U)
+#define RCC_AHBENR_CRYPEN_Msk (0x1UL << RCC_AHBENR_CRYPEN_Pos) /*!< 0x01000000 */
+#define RCC_AHBENR_CRYPEN RCC_AHBENR_CRYPEN_Msk /*!< Crypto clock enable*/
+
+/* Reference defines */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register ******************/
+#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM21EN_Pos (2U)
+#define RCC_APB2ENR_TIM21EN_Msk (0x1UL << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */
+#define RCC_APB2ENR_TIM22EN_Pos (5U)
+#define RCC_APB2ENR_TIM22EN_Msk (0x1UL << RCC_APB2ENR_TIM22EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk /*!< TIM22 clock enable */
+#define RCC_APB2ENR_FWEN_Pos (7U)
+#define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADCEN_Pos (9U)
+#define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
+#define RCC_APB2ENR_DBGEN_Pos (22U)
+#define RCC_APB2ENR_DBGEN_Msk (0x1UL << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */
+
+/* Reference defines */
+
+#define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
+#define RCC_APB1ENR_LPUART1EN_Pos (18U)
+#define RCC_APB1ENR_LPUART1EN_Msk (0x1UL << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */
+#define RCC_APB1ENR_USBEN_Pos (23U)
+#define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */
+#define RCC_APB1ENR_CRSEN_Pos (27U)
+#define RCC_APB1ENR_CRSEN_Msk (0x1UL << RCC_APB1ENR_CRSEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
+#define RCC_APB1ENR_DACEN_Pos (29U)
+#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC clock enable */
+#define RCC_APB1ENR_LPTIM1EN_Pos (31U)
+#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */
+
+/****************** Bit definition for RCC_IOPSMENR register ****************/
+#define RCC_IOPSMENR_IOPASMEN_Pos (0U)
+#define RCC_IOPSMENR_IOPASMEN_Msk (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPBSMEN_Pos (1U)
+#define RCC_IOPSMENR_IOPBSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPCSMEN_Pos (2U)
+#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPDSMEN_Pos (3U)
+#define RCC_IOPSMENR_IOPDSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos) /*!< 0x00000008 */
+#define RCC_IOPSMENR_IOPDSMEN RCC_IOPSMENR_IOPDSMEN_Msk /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPHSMEN_Pos (7U)
+#define RCC_IOPSMENR_IOPHSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_IOPDSMEN /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_AHBSMENR register ******************/
+#define RCC_AHBSMENR_DMASMEN_Pos (0U)
+#define RCC_AHBSMENR_DMASMEN_Msk (0x1UL << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */
+#define RCC_AHBSMENR_MIFSMEN_Pos (8U)
+#define RCC_AHBSMENR_MIFSMEN_Msk (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */
+#define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
+#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRCSMEN_Pos (12U)
+#define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */
+#define RCC_AHBSMENR_TSCSMEN_Pos (16U)
+#define RCC_AHBSMENR_TSCSMEN_Msk (0x1UL << RCC_AHBSMENR_TSCSMEN_Pos) /*!< 0x00010000 */
+#define RCC_AHBSMENR_TSCSMEN RCC_AHBSMENR_TSCSMEN_Msk /*!< TSC clock enabled in sleep mode */
+#define RCC_AHBSMENR_RNGSMEN_Pos (20U)
+#define RCC_AHBSMENR_RNGSMEN_Msk (0x1UL << RCC_AHBSMENR_RNGSMEN_Pos) /*!< 0x00100000 */
+#define RCC_AHBSMENR_RNGSMEN RCC_AHBSMENR_RNGSMEN_Msk /*!< RNG clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRYPSMEN_Pos (24U)
+#define RCC_AHBSMENR_CRYPSMEN_Msk (0x1UL << RCC_AHBSMENR_CRYPSMEN_Pos) /*!< 0x01000000 */
+#define RCC_AHBSMENR_CRYPSMEN RCC_AHBSMENR_CRYPSMEN_Msk /*!< Crypto clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB2SMENR register ******************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM21SMEN_Pos (2U)
+#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM22SMEN_Pos (5U)
+#define RCC_APB2SMENR_TIM22SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk /*!< TIM22 clock enabled in sleep mode */
+#define RCC_APB2SMENR_ADCSMEN_Pos (9U)
+#define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
+#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
+#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk /*!< USART1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGSMEN_Pos (22U)
+#define RCC_APB2SMENR_DBGSMEN_Msk (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB1SMENR register ******************/
+#define RCC_APB1SMENR_TIM2SMEN_Pos (0U)
+#define RCC_APB1SMENR_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_TIM6SMEN_Pos (4U)
+#define RCC_APB1SMENR_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM6SMEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1SMENR_TIM6SMEN RCC_APB1SMENR_TIM6SMEN_Msk /*!< Timer 6 clock enabled in sleep mode */
+#define RCC_APB1SMENR_WWDGSMEN_Pos (11U)
+#define RCC_APB1SMENR_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */
+#define RCC_APB1SMENR_SPI2SMEN_Pos (14U)
+#define RCC_APB1SMENR_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR_SPI2SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1SMENR_SPI2SMEN RCC_APB1SMENR_SPI2SMEN_Msk /*!< SPI2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART2SMEN_Pos (17U)
+#define RCC_APB1SMENR_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPUART1SMEN_Pos (18U)
+#define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C1SMEN_Pos (21U)
+#define RCC_APB1SMENR_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C2SMEN_Pos (22U)
+#define RCC_APB1SMENR_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1SMENR_I2C2SMEN RCC_APB1SMENR_I2C2SMEN_Msk /*!< I2C2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USBSMEN_Pos (23U)
+#define RCC_APB1SMENR_USBSMEN_Msk (0x1UL << RCC_APB1SMENR_USBSMEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1SMENR_USBSMEN RCC_APB1SMENR_USBSMEN_Msk /*!< USB clock enabled in sleep mode */
+#define RCC_APB1SMENR_CRSSMEN_Pos (27U)
+#define RCC_APB1SMENR_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR_CRSSMEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1SMENR_CRSSMEN RCC_APB1SMENR_CRSSMEN_Msk /*!< CRS clock enabled in sleep mode */
+#define RCC_APB1SMENR_PWRSMEN_Pos (28U)
+#define RCC_APB1SMENR_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */
+#define RCC_APB1SMENR_DACSMEN_Pos (29U)
+#define RCC_APB1SMENR_DACSMEN_Msk (0x1UL << RCC_APB1SMENR_DACSMEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1SMENR_DACSMEN RCC_APB1SMENR_DACSMEN_Msk /*!< DAC clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U)
+#define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */
+
+/******************* Bit definition for RCC_CCIPR register *******************/
+/*!< USART1 Clock source selection */
+#define RCC_CCIPR_USART1SEL_Pos (0U)
+#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
+#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk /*!< USART1SEL[1:0] bits */
+#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
+
+/*!< USART2 Clock source selection */
+#define RCC_CCIPR_USART2SEL_Pos (2U)
+#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */
+#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+/*!< LPUART1 Clock source selection */
+#define RCC_CCIPR_LPUART1SEL_Pos (10U)
+#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */
+#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */
+#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CCIPR_I2C1SEL_Pos (12U)
+#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */
+#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
+
+
+/*!< LPTIM1 Clock source selection */
+#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
+#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */
+#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+/*!< HSI48 Clock source selection */
+#define RCC_CCIPR_HSI48SEL_Pos (26U)
+#define RCC_CCIPR_HSI48SEL_Msk (0x1UL << RCC_CCIPR_HSI48SEL_Pos) /*!< 0x04000000 */
+#define RCC_CCIPR_HSI48SEL RCC_CCIPR_HSI48SEL_Msk /*!< HSI48 RC clock source selection bit for USB and RNG*/
+
+/* Legacy defines */
+#define RCC_CCIPR_HSI48MSEL RCC_CCIPR_HSI48SEL
+
+/******************* Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSEON_Pos (8U)
+#define RCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */
+#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_CSR_LSERDY_Pos (9U)
+#define RCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */
+#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP_Pos (10U)
+#define RCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */
+#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_CSR_LSEDRV_Pos (11U)
+#define RCC_CSR_LSEDRV_Msk (0x3UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */
+#define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_CSR_LSEDRV_0 (0x1UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */
+#define RCC_CSR_LSEDRV_1 (0x2UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */
+
+#define RCC_CSR_LSECSSON_Pos (13U)
+#define RCC_CSR_LSECSSON_Msk (0x1UL << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */
+#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */
+#define RCC_CSR_LSECSSD_Pos (14U)
+#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
+#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
+
+/*!< RTC congiguration */
+#define RCC_CSR_RTCSEL_Pos (16U)
+#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
+
+#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CSR_RTCSEL_LSE_Pos (16U)
+#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_LSI_Pos (17U)
+#define RCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */
+#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_HSE_Pos (16U)
+#define RCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */
+
+#define RCC_CSR_RTCEN_Pos (18U)
+#define RCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */
+#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_CSR_RTCRST_Pos (19U)
+#define RCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */
+#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */
+
+#define RCC_CSR_RMVF_Pos (23U)
+#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_FWRSTF_Pos (24U)
+#define RCC_CSR_FWRSTF_Msk (0x1UL << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk /*!< Mifare Firewall reset flag */
+#define RCC_CSR_OBLRSTF_Pos (25U)
+#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+/* Reference defines */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN_Pos (2U)
+#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
+#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos (3U)
+#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
+#define RNG_CR_IE RNG_CR_IE_Msk
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY_Pos (0U)
+#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
+#define RNG_SR_DRDY RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos (1U)
+#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
+#define RNG_SR_CECS RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos (2U)
+#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
+#define RNG_SR_SECS RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos (5U)
+#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
+#define RNG_SR_CEIS RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos (6U)
+#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
+#define RNG_SR_SEIS RNG_SR_SEIS_Msk
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER1_SUPPORT
+#define RTC_TAMPER2_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk /*!< */
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk /*!< */
+#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk /*!< */
+#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */
+#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */
+#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk /*!< */
+#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk /*!< */
+#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk /*!< */
+#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk /*!< */
+#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */
+#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk /*!< */
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk /*!< */
+#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk /*!< */
+#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk /*!< */
+#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk /*!< */
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */
+#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk /*!< */
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< */
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */
+#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */
+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */
+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */
+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */
+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */
+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */
+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */
+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */
+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */
+#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */
+#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */
+#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */
+#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */
+#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */
+#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */
+#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */
+#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */
+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */
+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */
+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */
+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */
+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */
+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */
+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */
+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */
+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */
+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CALR register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */
+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define RTC_CAL_CALP RTC_CALR_CALP
+#define RTC_CAL_CALW8 RTC_CALR_CALW8
+#define RTC_CAL_CALW16 RTC_CALR_CALW16
+#define RTC_CAL_CALM RTC_CALR_CALM
+#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
+
+/******************** Bits definition for RTC_TAMPCR register ****************/
+#define RTC_TAMPCR_TAMP2MF_Pos (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2IE_Pos (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1MF_Pos (18U)
+#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
+#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1IE_Pos (16U)
+#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */
+#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */
+#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */
+#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos (7U)
+#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */
+#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP2E_Pos (3U)
+#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */
+#define RTC_TAMPCR_TAMPIE_Pos (2U)
+#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
+#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP1E_Pos (0U)
+#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_OR register ****************/
+#define RTC_OR_OUT_RMP_Pos (1U)
+#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */
+#define RTC_OR_ALARMOUTTYPE_Pos (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */
+
+/* Legacy defines */
+#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk /*!< */
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER (0x00000005U) /*!< */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+#define SPI_I2S_SUPPORT /*!< I2S support */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
+#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR1_BOOT_MODE_Pos (8U)
+#define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
+#define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */
+#define SYSCFG_CFGR1_BOOT_MODE_0 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOT_MODE_1 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_FWDISEN_Pos (0U)
+#define SYSCFG_CFGR2_FWDISEN_Msk (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos (8U)
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR2_I2C_PB6_FMP SYSCFG_CFGR2_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos (9U)
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR2_I2C_PB7_FMP SYSCFG_CFGR2_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos (10U)
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
+#define SYSCFG_CFGR2_I2C_PB8_FMP SYSCFG_CFGR2_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos (11U)
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
+#define SYSCFG_CFGR2_I2C_PB9_FMP SYSCFG_CFGR2_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR2_I2C1_FMP_Pos (12U)
+#define SYSCFG_CFGR2_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR2_I2C1_FMP SYSCFG_CFGR2_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR2_I2C2_FMP_Pos (13U)
+#define SYSCFG_CFGR2_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
+#define SYSCFG_CFGR2_I2C2_FMP SYSCFG_CFGR2_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
+
+
+/***************** Bit definition for SYSCFG_CFGR3 register ****************/
+#define SYSCFG_CFGR3_EN_VREFINT_Pos (0U)
+#define SYSCFG_CFGR3_EN_VREFINT_Msk (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_EN_VREFINT SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
+#define SYSCFG_CFGR3_VREF_OUT_Pos (4U)
+#define SYSCFG_CFGR3_VREF_OUT_Msk (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
+#define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */
+#define SYSCFG_CFGR3_VREF_OUT_0 (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
+#define SYSCFG_CFGR3_VREF_OUT_1 (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U)
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U)
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U)
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
+#define SYSCFG_CFGR3_ENREF_HSI48_Pos (13U)
+#define SYSCFG_CFGR3_ENREF_HSI48_Msk (0x1UL << SYSCFG_CFGR3_ENREF_HSI48_Pos) /*!< 0x00002000 */
+#define SYSCFG_CFGR3_ENREF_HSI48 SYSCFG_CFGR3_ENREF_HSI48_Msk /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
+#define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U)
+#define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
+#define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
+#define SYSCFG_CFGR3_REF_LOCK_Pos (31U)
+#define SYSCFG_CFGR3_REF_LOCK_Msk (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
+#define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */
+
+/* Legacy defines */
+
+#define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
+#define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
+#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
+#define SYSCFG_CFGR3_ENREF_RC48MHz SYSCFG_CFGR3_ENREF_HSI48
+#define SYSCFG_CFGR3_REF_RC48MHz_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_REF_HSI48_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+
+/******************************************************************************/
+/* */
+/* Timers (TIM)*/
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
+#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
+ || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#else
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#endif
+
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFUL << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFUL << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM2_OR_ETR_RMP_Pos (0U)
+#define TIM2_OR_ETR_RMP_Msk (0x7UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000007 */
+#define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
+#define TIM2_OR_ETR_RMP_0 (0x1UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM2_OR_ETR_RMP_1 (0x2UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM2_OR_ETR_RMP_2 (0x4UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000004 */
+#define TIM2_OR_TI4_RMP_Pos (3U)
+#define TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000018 */
+#define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
+#define TIM2_OR_TI4_RMP_0 (0x1UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */
+#define TIM2_OR_TI4_RMP_1 (0x2UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000010 */
+
+#define TIM21_OR_ETR_RMP_Pos (0U)
+#define TIM21_OR_ETR_RMP_Msk (0x3UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
+#define TIM21_OR_ETR_RMP_0 (0x1UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM21_OR_ETR_RMP_1 (0x2UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM21_OR_TI1_RMP_Pos (2U)
+#define TIM21_OR_TI1_RMP_Msk (0x7UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x0000001C */
+#define TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
+#define TIM21_OR_TI1_RMP_0 (0x1UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM21_OR_TI1_RMP_1 (0x2UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+#define TIM21_OR_TI1_RMP_2 (0x4UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000010 */
+#define TIM21_OR_TI2_RMP_Pos (5U)
+#define TIM21_OR_TI2_RMP_Msk (0x1UL << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */
+#define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */
+
+#define TIM22_OR_ETR_RMP_Pos (0U)
+#define TIM22_OR_ETR_RMP_Msk (0x3UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM22_OR_ETR_RMP TIM22_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
+#define TIM22_OR_ETR_RMP_0 (0x1UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM22_OR_ETR_RMP_1 (0x2UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM22_OR_TI1_RMP_Pos (2U)
+#define TIM22_OR_TI1_RMP_Msk (0x3UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x0000000C */
+#define TIM22_OR_TI1_RMP TIM22_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
+#define TIM22_OR_TI1_RMP_0 (0x1UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM22_OR_TI1_RMP_1 (0x2UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+
+
+/******************************************************************************/
+/* */
+/* Touch Sensing Controller (TSC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TSC_CR register *********************/
+#define TSC_CR_TSCE_Pos (0U)
+#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
+#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
+#define TSC_CR_START_Pos (1U)
+#define TSC_CR_START_Msk (0x1UL << TSC_CR_START_Pos) /*!< 0x00000002 */
+#define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
+#define TSC_CR_AM_Pos (2U)
+#define TSC_CR_AM_Msk (0x1UL << TSC_CR_AM_Pos) /*!< 0x00000004 */
+#define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL_Pos (3U)
+#define TSC_CR_SYNCPOL_Msk (0x1UL << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
+#define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF_Pos (4U)
+#define TSC_CR_IODEF_Msk (0x1UL << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
+#define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
+
+#define TSC_CR_MCV_Pos (5U)
+#define TSC_CR_MCV_Msk (0x7UL << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
+#define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0 (0x1UL << TSC_CR_MCV_Pos) /*!< 0x00000020 */
+#define TSC_CR_MCV_1 (0x2UL << TSC_CR_MCV_Pos) /*!< 0x00000040 */
+#define TSC_CR_MCV_2 (0x4UL << TSC_CR_MCV_Pos) /*!< 0x00000080 */
+
+#define TSC_CR_PGPSC_Pos (12U)
+#define TSC_CR_PGPSC_Msk (0x7UL << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
+#define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0 (0x1UL << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
+#define TSC_CR_PGPSC_1 (0x2UL << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
+#define TSC_CR_PGPSC_2 (0x4UL << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
+
+#define TSC_CR_SSPSC_Pos (15U)
+#define TSC_CR_SSPSC_Msk (0x1UL << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
+#define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE_Pos (16U)
+#define TSC_CR_SSE_Msk (0x1UL << TSC_CR_SSE_Pos) /*!< 0x00010000 */
+#define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD_Pos (17U)
+#define TSC_CR_SSD_Msk (0x7FUL << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
+#define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0 (0x01UL << TSC_CR_SSD_Pos) /*!< 0x00020000 */
+#define TSC_CR_SSD_1 (0x02UL << TSC_CR_SSD_Pos) /*!< 0x00040000 */
+#define TSC_CR_SSD_2 (0x04UL << TSC_CR_SSD_Pos) /*!< 0x00080000 */
+#define TSC_CR_SSD_3 (0x08UL << TSC_CR_SSD_Pos) /*!< 0x00100000 */
+#define TSC_CR_SSD_4 (0x10UL << TSC_CR_SSD_Pos) /*!< 0x00200000 */
+#define TSC_CR_SSD_5 (0x20UL << TSC_CR_SSD_Pos) /*!< 0x00400000 */
+#define TSC_CR_SSD_6 (0x40UL << TSC_CR_SSD_Pos) /*!< 0x00800000 */
+
+#define TSC_CR_CTPL_Pos (24U)
+#define TSC_CR_CTPL_Msk (0xFUL << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
+#define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0 (0x1UL << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
+#define TSC_CR_CTPL_1 (0x2UL << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
+#define TSC_CR_CTPL_2 (0x4UL << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
+#define TSC_CR_CTPL_3 (0x8UL << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
+
+#define TSC_CR_CTPH_Pos (28U)
+#define TSC_CR_CTPH_Msk (0xFUL << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
+#define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0 (0x1UL << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
+#define TSC_CR_CTPH_1 (0x2UL << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
+#define TSC_CR_CTPH_2 (0x4UL << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
+#define TSC_CR_CTPH_3 (0x8UL << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for TSC_IER register ********************/
+#define TSC_IER_EOAIE_Pos (0U)
+#define TSC_IER_EOAIE_Msk (0x1UL << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
+#define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE_Pos (1U)
+#define TSC_IER_MCEIE_Msk (0x1UL << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
+#define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
+
+/******************* Bit definition for TSC_ICR register ********************/
+#define TSC_ICR_EOAIC_Pos (0U)
+#define TSC_ICR_EOAIC_Msk (0x1UL << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
+#define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC_Pos (1U)
+#define TSC_ICR_MCEIC_Msk (0x1UL << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
+#define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
+
+/******************* Bit definition for TSC_ISR register ********************/
+#define TSC_ISR_EOAF_Pos (0U)
+#define TSC_ISR_EOAF_Msk (0x1UL << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
+#define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
+#define TSC_ISR_MCEF_Pos (1U)
+#define TSC_ISR_MCEF_Msk (0x1UL << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
+#define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
+
+/******************* Bit definition for TSC_IOHCR register ******************/
+#define TSC_IOHCR_G1_IO1_Pos (0U)
+#define TSC_IOHCR_G1_IO1_Msk (0x1UL << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2_Pos (1U)
+#define TSC_IOHCR_G1_IO2_Msk (0x1UL << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3_Pos (2U)
+#define TSC_IOHCR_G1_IO3_Msk (0x1UL << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4_Pos (3U)
+#define TSC_IOHCR_G1_IO4_Msk (0x1UL << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1_Pos (4U)
+#define TSC_IOHCR_G2_IO1_Msk (0x1UL << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2_Pos (5U)
+#define TSC_IOHCR_G2_IO2_Msk (0x1UL << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3_Pos (6U)
+#define TSC_IOHCR_G2_IO3_Msk (0x1UL << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4_Pos (7U)
+#define TSC_IOHCR_G2_IO4_Msk (0x1UL << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1_Pos (8U)
+#define TSC_IOHCR_G3_IO1_Msk (0x1UL << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2_Pos (9U)
+#define TSC_IOHCR_G3_IO2_Msk (0x1UL << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3_Pos (10U)
+#define TSC_IOHCR_G3_IO3_Msk (0x1UL << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4_Pos (11U)
+#define TSC_IOHCR_G3_IO4_Msk (0x1UL << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1_Pos (12U)
+#define TSC_IOHCR_G4_IO1_Msk (0x1UL << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2_Pos (13U)
+#define TSC_IOHCR_G4_IO2_Msk (0x1UL << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3_Pos (14U)
+#define TSC_IOHCR_G4_IO3_Msk (0x1UL << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4_Pos (15U)
+#define TSC_IOHCR_G4_IO4_Msk (0x1UL << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1_Pos (16U)
+#define TSC_IOHCR_G5_IO1_Msk (0x1UL << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2_Pos (17U)
+#define TSC_IOHCR_G5_IO2_Msk (0x1UL << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3_Pos (18U)
+#define TSC_IOHCR_G5_IO3_Msk (0x1UL << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4_Pos (19U)
+#define TSC_IOHCR_G5_IO4_Msk (0x1UL << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1_Pos (20U)
+#define TSC_IOHCR_G6_IO1_Msk (0x1UL << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2_Pos (21U)
+#define TSC_IOHCR_G6_IO2_Msk (0x1UL << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3_Pos (22U)
+#define TSC_IOHCR_G6_IO3_Msk (0x1UL << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4_Pos (23U)
+#define TSC_IOHCR_G6_IO4_Msk (0x1UL << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1_Pos (24U)
+#define TSC_IOHCR_G7_IO1_Msk (0x1UL << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2_Pos (25U)
+#define TSC_IOHCR_G7_IO2_Msk (0x1UL << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3_Pos (26U)
+#define TSC_IOHCR_G7_IO3_Msk (0x1UL << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4_Pos (27U)
+#define TSC_IOHCR_G7_IO4_Msk (0x1UL << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1_Pos (28U)
+#define TSC_IOHCR_G8_IO1_Msk (0x1UL << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2_Pos (29U)
+#define TSC_IOHCR_G8_IO2_Msk (0x1UL << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3_Pos (30U)
+#define TSC_IOHCR_G8_IO3_Msk (0x1UL << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4_Pos (31U)
+#define TSC_IOHCR_G8_IO4_Msk (0x1UL << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+
+/******************* Bit definition for TSC_IOASCR register *****************/
+#define TSC_IOASCR_G1_IO1_Pos (0U)
+#define TSC_IOASCR_G1_IO1_Msk (0x1UL << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2_Pos (1U)
+#define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3_Pos (2U)
+#define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4_Pos (3U)
+#define TSC_IOASCR_G1_IO4_Msk (0x1UL << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1_Pos (4U)
+#define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2_Pos (5U)
+#define TSC_IOASCR_G2_IO2_Msk (0x1UL << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3_Pos (6U)
+#define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4_Pos (7U)
+#define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1_Pos (8U)
+#define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2_Pos (9U)
+#define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3_Pos (10U)
+#define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4_Pos (11U)
+#define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1_Pos (12U)
+#define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2_Pos (13U)
+#define TSC_IOASCR_G4_IO2_Msk (0x1UL << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3_Pos (14U)
+#define TSC_IOASCR_G4_IO3_Msk (0x1UL << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4_Pos (15U)
+#define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1_Pos (16U)
+#define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2_Pos (17U)
+#define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3_Pos (18U)
+#define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4_Pos (19U)
+#define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1_Pos (20U)
+#define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2_Pos (21U)
+#define TSC_IOASCR_G6_IO2_Msk (0x1UL << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3_Pos (22U)
+#define TSC_IOASCR_G6_IO3_Msk (0x1UL << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4_Pos (23U)
+#define TSC_IOASCR_G6_IO4_Msk (0x1UL << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1_Pos (24U)
+#define TSC_IOASCR_G7_IO1_Msk (0x1UL << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2_Pos (25U)
+#define TSC_IOASCR_G7_IO2_Msk (0x1UL << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3_Pos (26U)
+#define TSC_IOASCR_G7_IO3_Msk (0x1UL << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4_Pos (27U)
+#define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1_Pos (28U)
+#define TSC_IOASCR_G8_IO1_Msk (0x1UL << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2_Pos (29U)
+#define TSC_IOASCR_G8_IO2_Msk (0x1UL << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3_Pos (30U)
+#define TSC_IOASCR_G8_IO3_Msk (0x1UL << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4_Pos (31U)
+#define TSC_IOASCR_G8_IO4_Msk (0x1UL << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */
+
+/******************* Bit definition for TSC_IOSCR register ******************/
+#define TSC_IOSCR_G1_IO1_Pos (0U)
+#define TSC_IOSCR_G1_IO1_Msk (0x1UL << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2_Pos (1U)
+#define TSC_IOSCR_G1_IO2_Msk (0x1UL << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3_Pos (2U)
+#define TSC_IOSCR_G1_IO3_Msk (0x1UL << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4_Pos (3U)
+#define TSC_IOSCR_G1_IO4_Msk (0x1UL << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1_Pos (4U)
+#define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2_Pos (5U)
+#define TSC_IOSCR_G2_IO2_Msk (0x1UL << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3_Pos (6U)
+#define TSC_IOSCR_G2_IO3_Msk (0x1UL << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4_Pos (7U)
+#define TSC_IOSCR_G2_IO4_Msk (0x1UL << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1_Pos (8U)
+#define TSC_IOSCR_G3_IO1_Msk (0x1UL << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2_Pos (9U)
+#define TSC_IOSCR_G3_IO2_Msk (0x1UL << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3_Pos (10U)
+#define TSC_IOSCR_G3_IO3_Msk (0x1UL << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4_Pos (11U)
+#define TSC_IOSCR_G3_IO4_Msk (0x1UL << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1_Pos (12U)
+#define TSC_IOSCR_G4_IO1_Msk (0x1UL << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2_Pos (13U)
+#define TSC_IOSCR_G4_IO2_Msk (0x1UL << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3_Pos (14U)
+#define TSC_IOSCR_G4_IO3_Msk (0x1UL << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4_Pos (15U)
+#define TSC_IOSCR_G4_IO4_Msk (0x1UL << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1_Pos (16U)
+#define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2_Pos (17U)
+#define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3_Pos (18U)
+#define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4_Pos (19U)
+#define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1_Pos (20U)
+#define TSC_IOSCR_G6_IO1_Msk (0x1UL << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2_Pos (21U)
+#define TSC_IOSCR_G6_IO2_Msk (0x1UL << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3_Pos (22U)
+#define TSC_IOSCR_G6_IO3_Msk (0x1UL << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4_Pos (23U)
+#define TSC_IOSCR_G6_IO4_Msk (0x1UL << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1_Pos (24U)
+#define TSC_IOSCR_G7_IO1_Msk (0x1UL << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2_Pos (25U)
+#define TSC_IOSCR_G7_IO2_Msk (0x1UL << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3_Pos (26U)
+#define TSC_IOSCR_G7_IO3_Msk (0x1UL << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4_Pos (27U)
+#define TSC_IOSCR_G7_IO4_Msk (0x1UL << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1_Pos (28U)
+#define TSC_IOSCR_G8_IO1_Msk (0x1UL << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2_Pos (29U)
+#define TSC_IOSCR_G8_IO2_Msk (0x1UL << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3_Pos (30U)
+#define TSC_IOSCR_G8_IO3_Msk (0x1UL << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4_Pos (31U)
+#define TSC_IOSCR_G8_IO4_Msk (0x1UL << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */
+
+/******************* Bit definition for TSC_IOCCR register ******************/
+#define TSC_IOCCR_G1_IO1_Pos (0U)
+#define TSC_IOCCR_G1_IO1_Msk (0x1UL << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2_Pos (1U)
+#define TSC_IOCCR_G1_IO2_Msk (0x1UL << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3_Pos (2U)
+#define TSC_IOCCR_G1_IO3_Msk (0x1UL << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4_Pos (3U)
+#define TSC_IOCCR_G1_IO4_Msk (0x1UL << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1_Pos (4U)
+#define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2_Pos (5U)
+#define TSC_IOCCR_G2_IO2_Msk (0x1UL << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3_Pos (6U)
+#define TSC_IOCCR_G2_IO3_Msk (0x1UL << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4_Pos (7U)
+#define TSC_IOCCR_G2_IO4_Msk (0x1UL << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1_Pos (8U)
+#define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2_Pos (9U)
+#define TSC_IOCCR_G3_IO2_Msk (0x1UL << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3_Pos (10U)
+#define TSC_IOCCR_G3_IO3_Msk (0x1UL << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4_Pos (11U)
+#define TSC_IOCCR_G3_IO4_Msk (0x1UL << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1_Pos (12U)
+#define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2_Pos (13U)
+#define TSC_IOCCR_G4_IO2_Msk (0x1UL << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3_Pos (14U)
+#define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4_Pos (15U)
+#define TSC_IOCCR_G4_IO4_Msk (0x1UL << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1_Pos (16U)
+#define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2_Pos (17U)
+#define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3_Pos (18U)
+#define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4_Pos (19U)
+#define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1_Pos (20U)
+#define TSC_IOCCR_G6_IO1_Msk (0x1UL << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2_Pos (21U)
+#define TSC_IOCCR_G6_IO2_Msk (0x1UL << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3_Pos (22U)
+#define TSC_IOCCR_G6_IO3_Msk (0x1UL << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4_Pos (23U)
+#define TSC_IOCCR_G6_IO4_Msk (0x1UL << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1_Pos (24U)
+#define TSC_IOCCR_G7_IO1_Msk (0x1UL << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2_Pos (25U)
+#define TSC_IOCCR_G7_IO2_Msk (0x1UL << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3_Pos (26U)
+#define TSC_IOCCR_G7_IO3_Msk (0x1UL << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4_Pos (27U)
+#define TSC_IOCCR_G7_IO4_Msk (0x1UL << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1_Pos (28U)
+#define TSC_IOCCR_G8_IO1_Msk (0x1UL << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2_Pos (29U)
+#define TSC_IOCCR_G8_IO2_Msk (0x1UL << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3_Pos (30U)
+#define TSC_IOCCR_G8_IO3_Msk (0x1UL << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4_Pos (31U)
+#define TSC_IOCCR_G8_IO4_Msk (0x1UL << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */
+
+/******************* Bit definition for TSC_IOGCSR register *****************/
+#define TSC_IOGCSR_G1E_Pos (0U)
+#define TSC_IOGCSR_G1E_Msk (0x1UL << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
+#define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E_Pos (1U)
+#define TSC_IOGCSR_G2E_Msk (0x1UL << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
+#define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E_Pos (2U)
+#define TSC_IOGCSR_G3E_Msk (0x1UL << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
+#define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E_Pos (3U)
+#define TSC_IOGCSR_G4E_Msk (0x1UL << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
+#define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E_Pos (4U)
+#define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
+#define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E_Pos (5U)
+#define TSC_IOGCSR_G6E_Msk (0x1UL << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
+#define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E_Pos (6U)
+#define TSC_IOGCSR_G7E_Msk (0x1UL << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
+#define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E_Pos (7U)
+#define TSC_IOGCSR_G8E_Msk (0x1UL << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */
+#define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S_Pos (16U)
+#define TSC_IOGCSR_G1S_Msk (0x1UL << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
+#define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S_Pos (17U)
+#define TSC_IOGCSR_G2S_Msk (0x1UL << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
+#define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S_Pos (18U)
+#define TSC_IOGCSR_G3S_Msk (0x1UL << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
+#define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S_Pos (19U)
+#define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
+#define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S_Pos (20U)
+#define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
+#define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S_Pos (21U)
+#define TSC_IOGCSR_G6S_Msk (0x1UL << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
+#define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S_Pos (22U)
+#define TSC_IOGCSR_G7S_Msk (0x1UL << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
+#define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S_Pos (23U)
+#define TSC_IOGCSR_G8S_Msk (0x1UL << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */
+#define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */
+
+/******************* Bit definition for TSC_IOGXCR register *****************/
+#define TSC_IOGXCR_CNT_Pos (0U)
+#define TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
+#define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE_Pos (0U)
+#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+#define USART_CR1_UESM_Pos (1U)
+#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
+#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_M0_Pos (12U)
+#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
+#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos (13U)
+#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos (14U)
+#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos (16U)
+#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
+#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
+#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
+#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
+#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos (21U)
+#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
+#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
+#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
+#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
+#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos (26U)
+#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos (27U)
+#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos (28U)
+#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
+#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7_Pos (4U)
+#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos (15U)
+#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos (16U)
+#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos (17U)
+#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos (18U)
+#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos (19U)
+#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos (20U)
+#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos (21U)
+#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos (23U)
+#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos (24U)
+#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos (12U)
+#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos (13U)
+#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos (14U)
+#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos (15U)
+#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos (17U)
+#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos (20U)
+#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
+#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
+#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos (22U)
+#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
+#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
+#define USART_CR3_UCESM_Pos (23U)
+#define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
+#define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION_Pos (0U)
+#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos (4U)
+#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO_Pos (0U)
+#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos (24U)
+#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ_Pos (0U)
+#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
+#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos (1U)
+#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
+#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos (2U)
+#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
+#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos (3U)
+#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
+#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos (4U)
+#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
+#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE_Pos (0U)
+#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
+#define USART_ISR_FE_Pos (1U)
+#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
+#define USART_ISR_NE_Pos (2U)
+#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos (3U)
+#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos (4U)
+#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos (5U)
+#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos (6U)
+#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos (7U)
+#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
+#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos (8U)
+#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos (9U)
+#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos (10U)
+#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
+#define USART_ISR_RTOF_Pos (11U)
+#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos (12U)
+#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos (14U)
+#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos (15U)
+#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos (16U)
+#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
+#define USART_ISR_CMF_Pos (17U)
+#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos (18U)
+#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos (19U)
+#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos (20U)
+#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
+#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos (21U)
+#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos (22U)
+#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
+#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF_Pos (0U)
+#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos (1U)
+#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos (2U)
+#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */
+#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos (3U)
+#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos (4U)
+#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos (6U)
+#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF_Pos (8U)
+#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos (9U)
+#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos (11U)
+#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos (12U)
+#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos (17U)
+#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos (20U)
+#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
+#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
+
+/* Compatibility defines with other series */
+#define USART_ICR_NECF USART_ICR_NCF
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR_Pos (0U)
+#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR_Pos (0U)
+#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* USB Device General registers */
+/* */
+/******************************************************************************/
+#define USB_BASE (0x40005C00U) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR_Pos (13U)
+#define USB_PMAADDR_Msk (0x20003UL << USB_PMAADDR_Pos) /*!< 0x40006000 */
+#define USB_PMAADDR USB_PMAADDR_Msk /*!< USB_IP Packet Memory Area base address */
+
+#define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
+#define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
+#define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
+#define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
+#define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
+#define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
+#define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
+
+/**************************** ISTR interrupt events *************************/
+#define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
+#define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
+#define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
+#define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
+#define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
+#define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
+#define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
+#define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
+#define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
+
+#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
+#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
+#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
+#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
+#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
+#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
+#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
+#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
+#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
+/************************* CNTR control register bits definitions ***********/
+#define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
+#define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
+#define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
+#define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
+#define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
+#define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
+#define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
+#define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
+#define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
+#define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
+#define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
+#define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
+#define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
+#define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
+/************************* BCDR control register bits definitions ***********/
+#define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
+#define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
+#define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
+#define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
+#define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
+#define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
+#define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
+#define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
+#define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
+/*************************** LPM register bits definitions ******************/
+#define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
+#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
+#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
+/******************** FNR Frame Number Register bit definitions ************/
+#define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
+#define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
+#define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
+#define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
+#define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
+/******************** DADDR Device ADDRess bit definitions ****************/
+#define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */
+#define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */
+/****************************** Endpoint register *************************/
+#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
+#define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
+#define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
+#define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
+#define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
+#define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
+#define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
+#define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
+/* bit positions */
+#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
+#define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
+#define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
+#define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
+#define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+ /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
+#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+/******************************* AES Instances ********************************/
+#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
+
+/******************************* COMP Instances *******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+ ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances *********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOH))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
+
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SMBUS Instances *****************************/
+#define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/************* LPTIM instances supporting the encoder mode feature ************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM6))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM21) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM22) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/******************* TIM Instances : output(s) OCXEC register *****************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** USART Instances : Auto Baud Rate detection ****************/
+
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/******************************* USB Instances *******************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32L0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32L0 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+
+#define LPUART1_IRQn AES_RNG_LPUART1_IRQn
+#define AES_LPUART1_IRQn AES_RNG_LPUART1_IRQn
+#define RNG_LPUART1_IRQn AES_RNG_LPUART1_IRQn
+#define TIM6_IRQn TIM6_DAC_IRQn
+#define RCC_IRQn RCC_CRS_IRQn
+#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
+#define ADC1_IRQn ADC1_COMP_IRQn
+
+/* Aliases for __IRQHandler */
+#define LPUART1_IRQHandler AES_RNG_LPUART1_IRQHandler
+#define RNG_LPUART1_IRQHandler AES_RNG_LPUART1_IRQHandler
+#define AES_LPUART1_IRQHandler AES_RNG_LPUART1_IRQHandler
+#define TIM6_IRQHandler TIM6_DAC_IRQHandler
+#define RCC_IRQHandler RCC_CRS_IRQHandler
+#define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
+#define ADC1_IRQHandler ADC1_COMP_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L062xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/CMSIS/device/stm32l063xx.h b/CMSIS/device/stm32l063xx.h
new file mode 100644
index 0000000..462e1ea
--- /dev/null
+++ b/CMSIS/device/stm32l063xx.h
@@ -0,0 +1,7649 @@
+/**
+ ******************************************************************************
+ * @file stm32l063xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for stm32l063xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright(c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l063xx
+ * @{
+ */
+
+#ifndef __STM32L063xx_H
+#define __STM32L063xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 1U /*!< STM32L0xx provides an MPU */
+#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
+#define __NVIC_PRIO_BITS 2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief stm32l063xx Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+/*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
+
+/****** STM32L-0 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */
+ RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ TSC_IRQn = 8, /*!< TSC Interrupt */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
+ ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
+ LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 Interrupt */
+ TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
+ TIM21_IRQn = 20, /*!< TIM21 Interrupt */
+ TIM22_IRQn = 22, /*!< TIM22 Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */
+ I2C2_IRQn = 24, /*!< I2C2 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ SPI2_IRQn = 26, /*!< SPI2 Interrupt */
+ USART1_IRQn = 27, /*!< USART1 Interrupt */
+ USART2_IRQn = 28, /*!< USART2 Interrupt */
+ AES_RNG_LPUART1_IRQn = 29, /*!< AES and RNG and LPUART1 Interrupts */
+ LCD_IRQn = 30, /*!< LCD Interrupt */
+ USB_IRQn = 31, /*!< USB global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0plus.h"
+#include "system_stm32l0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+ uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+} ADC_Common_TypeDef;
+
+/**
+ * @brief AES hardware accelerator
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
+ __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
+ __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
+ __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
+ __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
+ __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
+ __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
+ __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
+ __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
+ __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
+ __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
+} AES_TypeDef;
+
+/**
+ * @brief Comparator
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
+} COMP_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+
+/**
+* @brief CRC calculation unit
+*/
+
+typedef struct
+{
+__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+uint8_t RESERVED0; /*!< Reserved, 0x05 */
+uint16_t RESERVED1; /*!< Reserved, 0x06 */
+__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+uint32_t RESERVED2; /*!< Reserved, 0x0C */
+__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Clock Recovery System
+ */
+
+typedef struct
+{
+__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
+__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
+__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
+__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
+} CRS_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ uint32_t RESERVED0[6]; /*!< 0x14-0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ uint32_t RESERVED1; /*!< 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
+} DMA_Request_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
+ __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
+ __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
+ __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
+ __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
+ __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
+ __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
+ __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
+ __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
+ __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
+} OB_TypeDef;
+
+
+/**
+ * @brief General Purpose IO
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief LPTIMIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+} LPTIM_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+ * @brief Independent WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief LCD
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
+ __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
+ __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
+ __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
+} LCD_TypeDef;
+
+/**
+ * @brief MIFARE Firewall
+ */
+typedef struct
+{
+ __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
+ __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
+ __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
+ __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
+ __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
+ __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
+ __IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x18 */
+ __IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */
+ __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
+
+} FIREWALL_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
+ __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
+ __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
+ __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
+ __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
+ __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
+ __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
+ __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
+ __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
+ __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
+ __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
+} RCC_TypeDef;
+
+/**
+ * @brief Random numbers generator
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Touch Sensing Controller (TSC)
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
+ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
+ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
+ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
+ __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief Universal Serial Bus Full Speed Device
+ */
+typedef struct
+{
+ __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
+ __IO uint16_t RESERVED0; /*!< Reserved */
+ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
+ __IO uint16_t RESERVED1; /*!< Reserved */
+ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
+ __IO uint16_t RESERVED2; /*!< Reserved */
+ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
+ __IO uint16_t RESERVED3; /*!< Reserved */
+ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
+ __IO uint16_t RESERVED4; /*!< Reserved */
+ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
+ __IO uint16_t RESERVED5; /*!< Reserved */
+ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
+ __IO uint16_t RESERVED6; /*!< Reserved */
+ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
+ __IO uint16_t RESERVED7[17]; /*!< Reserved */
+ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
+ __IO uint16_t RESERVED8; /*!< Reserved */
+ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
+ __IO uint16_t RESERVED9; /*!< Reserved */
+ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
+ __IO uint16_t RESERVEDA; /*!< Reserved */
+ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
+ __IO uint16_t RESERVEDB; /*!< Reserved */
+ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
+ __IO uint16_t RESERVEDC; /*!< Reserved */
+ __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
+ __IO uint16_t RESERVEDD; /*!< Reserved */
+ __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
+ __IO uint16_t RESERVEDE; /*!< Reserved */
+} USB_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */
+
+#define DATA_EEPROM_BASE (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
+#define DATA_EEPROM_END (0x080807FFUL) /*!< DATA EEPROM end address in the alias region */
+#define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */
+#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8KBytes) */
+
+#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000UL)
+
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL)
+#define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL)
+#define LCD_BASE (APBPERIPH_BASE + 0x00002400UL)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
+#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
+#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800UL)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
+#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL)
+#define CRS_BASE (APBPERIPH_BASE + 0x00006C00UL)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
+#define DAC_BASE (APBPERIPH_BASE + 0x00007400UL)
+#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL)
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
+#define COMP1_BASE (APBPERIPH_BASE + 0x00010018UL)
+#define COMP2_BASE (APBPERIPH_BASE + 0x0001001CUL)
+#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL)
+#define TIM21_BASE (APBPERIPH_BASE + 0x00010800UL)
+#define TIM22_BASE (APBPERIPH_BASE + 0x00011400UL)
+#define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00UL)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708UL)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
+#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
+#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL)
+
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
+#define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */
+#define FLASHSIZE_BASE (0x1FF8007CUL) /*!< FLASH Size register base address */
+#define UID_BASE (0x1FF80050UL) /*!< Unique device ID register base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
+#define TSC_BASE (AHBPERIPH_BASE + 0x00004000UL)
+#define RNG_BASE (AHBPERIPH_BASE + 0x00005000UL)
+#define AES_BASE (AHBPERIPH_BASE + 0x00006000UL)
+
+#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL)
+#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL)
+#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL)
+#define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00UL)
+#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00UL)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define CRS ((CRS_TypeDef *) CRS_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define LCD ((LCD_TypeDef *) LCD_BASE)
+
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
+#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
+#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
+/* Legacy defines */
+#define ADC ADC1_COMMON
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define TSC ((TSC_TypeDef *) TSC_BASE)
+#define AES ((AES_TypeDef *) AES_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+
+#define USB ((USB_TypeDef *) USB_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_EOCAL_Pos (11U)
+#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
+#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
+#define ADC_ISR_AWD_Pos (7U)
+#define ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
+#define ADC_ISR_EOSEQ_Pos (3U)
+#define ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_EOCALIE_Pos (11U)
+#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
+#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
+#define ADC_IER_AWDIE_Pos (7U)
+#define ADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE_Pos (3U)
+#define ADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH_Pos (26U)
+#define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
+#define ADC_CFGR1_AWDEN_Pos (23U)
+#define ADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL_Pos (22U)
+#define ADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN_Pos (16U)
+#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF_Pos (15U)
+#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
+#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT_Pos (14U)
+#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
+#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT_Pos (13U)
+#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD_Pos (12U)
+#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN_Pos (10U)
+#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
+#define ADC_CFGR1_EXTSEL_Pos (6U)
+#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
+#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
+#define ADC_CFGR1_ALIGN_Pos (5U)
+#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
+#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
+#define ADC_CFGR1_RES_Pos (3U)
+#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
+#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
+#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
+#define ADC_CFGR1_SCANDIR_Pos (2U)
+#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG_Pos (1U)
+#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
+#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN_Pos (0U)
+#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
+#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_TOVS_Pos (9U)
+#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
+#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+#define ADC_CFGR2_OVSR_Pos (2U)
+#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
+#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+#define ADC_CFGR2_OVSE_Pos (0U)
+#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
+#define ADC_CFGR2_CKMODE_Pos (30U)
+#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
+#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
+#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
+#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
+
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP_Pos (0U)
+#define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
+#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
+#define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
+#define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define ADC_SMPR_SMPR ADC_SMPR_SMP
+#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
+#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
+#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT_Pos (16U)
+#define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
+#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
+#define ADC_TR_LT_Pos (0U)
+#define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL_Pos (0U)
+#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
+#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
+#define ADC_CHSELR_CHSEL18_Pos (18U)
+#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17_Pos (17U)
+#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
+#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL16_Pos (16U)
+#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */
+#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< Channel 16 selection */
+#define ADC_CHSELR_CHSEL15_Pos (15U)
+#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
+#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14_Pos (14U)
+#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
+#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13_Pos (13U)
+#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
+#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12_Pos (12U)
+#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
+#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11_Pos (11U)
+#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
+#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10_Pos (10U)
+#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
+#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9_Pos (9U)
+#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
+#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8_Pos (8U)
+#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
+#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7_Pos (7U)
+#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
+#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6_Pos (6U)
+#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
+#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5_Pos (5U)
+#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
+#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4_Pos (4U)
+#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
+#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3_Pos (3U)
+#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
+#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2_Pos (2U)
+#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
+#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1_Pos (1U)
+#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
+#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0_Pos (0U)
+#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
+#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_CALFACT_Pos (0U)
+#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_LFMEN_Pos (25U)
+#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
+#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
+#define ADC_CCR_VLCDEN_Pos (24U)
+#define ADC_CCR_VLCDEN_Msk (0x1UL << ADC_CCR_VLCDEN_Pos) /*!< 0x01000000 */
+#define ADC_CCR_VLCDEN ADC_CCR_VLCDEN_Msk /*!< Voltage LCD enable */
+#define ADC_CCR_TSEN_Pos (23U)
+#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+/******************************************************************************/
+/* */
+/* Advanced Encryption Standard (AES) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for AES_CR register *********************/
+#define AES_CR_EN_Pos (0U)
+#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */
+#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */
+#define AES_CR_DATATYPE_Pos (1U)
+#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */
+#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */
+#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */
+#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */
+
+#define AES_CR_MODE_Pos (3U)
+#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */
+#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */
+#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */
+#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */
+
+#define AES_CR_CHMOD_Pos (5U)
+#define AES_CR_CHMOD_Msk (0x3UL << AES_CR_CHMOD_Pos) /*!< 0x00000060 */
+#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */
+#define AES_CR_CHMOD_0 (0x1UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */
+#define AES_CR_CHMOD_1 (0x2UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */
+
+#define AES_CR_CCFC_Pos (7U)
+#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */
+#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */
+#define AES_CR_ERRC_Pos (8U)
+#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */
+#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */
+#define AES_CR_CCIE_Pos (9U)
+#define AES_CR_CCIE_Msk (0x1UL << AES_CR_CCIE_Pos) /*!< 0x00000200 */
+#define AES_CR_CCIE AES_CR_CCIE_Msk /*!< Computation Complete Interrupt Enable */
+#define AES_CR_ERRIE_Pos (10U)
+#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */
+#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */
+#define AES_CR_DMAINEN_Pos (11U)
+#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */
+#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< DMA ENable managing the data input phase */
+#define AES_CR_DMAOUTEN_Pos (12U)
+#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */
+#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< DMA Enable managing the data output phase */
+
+/******************* Bit definition for AES_SR register *********************/
+#define AES_SR_CCF_Pos (0U)
+#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */
+#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */
+#define AES_SR_RDERR_Pos (1U)
+#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */
+#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */
+#define AES_SR_WRERR_Pos (2U)
+#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */
+#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */
+
+/******************* Bit definition for AES_DINR register *******************/
+#define AES_DINR_Pos (0U)
+#define AES_DINR_Msk (0xFFFFUL << AES_DINR_Pos) /*!< 0x0000FFFF */
+#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */
+
+/******************* Bit definition for AES_DOUTR register ******************/
+#define AES_DOUTR_Pos (0U)
+#define AES_DOUTR_Msk (0xFFFFUL << AES_DOUTR_Pos) /*!< 0x0000FFFF */
+#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */
+
+/******************* Bit definition for AES_KEYR0 register ******************/
+#define AES_KEYR0_Pos (0U)
+#define AES_KEYR0_Msk (0xFFFFUL << AES_KEYR0_Pos) /*!< 0x0000FFFF */
+#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */
+
+/******************* Bit definition for AES_KEYR1 register ******************/
+#define AES_KEYR1_Pos (0U)
+#define AES_KEYR1_Msk (0xFFFFUL << AES_KEYR1_Pos) /*!< 0x0000FFFF */
+#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */
+
+/******************* Bit definition for AES_KEYR2 register ******************/
+#define AES_KEYR2_Pos (0U)
+#define AES_KEYR2_Msk (0xFFFFUL << AES_KEYR2_Pos) /*!< 0x0000FFFF */
+#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */
+
+/******************* Bit definition for AES_KEYR3 register ******************/
+#define AES_KEYR3_Pos (0U)
+#define AES_KEYR3_Msk (0xFFFFUL << AES_KEYR3_Pos) /*!< 0x0000FFFF */
+#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */
+
+/******************* Bit definition for AES_IVR0 register *******************/
+#define AES_IVR0_Pos (0U)
+#define AES_IVR0_Msk (0xFFFFUL << AES_IVR0_Pos) /*!< 0x0000FFFF */
+#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */
+
+/******************* Bit definition for AES_IVR1 register *******************/
+#define AES_IVR1_Pos (0U)
+#define AES_IVR1_Msk (0xFFFFUL << AES_IVR1_Pos) /*!< 0x0000FFFF */
+#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */
+
+/******************* Bit definition for AES_IVR2 register *******************/
+#define AES_IVR2_Pos (0U)
+#define AES_IVR2_Msk (0xFFFFUL << AES_IVR2_Pos) /*!< 0x0000FFFF */
+#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */
+
+/******************* Bit definition for AES_IVR3 register *******************/
+#define AES_IVR3_Pos (0U)
+#define AES_IVR3_Msk (0xFFFFUL << AES_IVR3_Pos) /*!< 0x0000FFFF */
+#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+/************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN_Pos (0U)
+#define COMP_CSR_COMP1EN_Msk (0x1UL << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
+#define COMP_CSR_COMP1INNSEL_Pos (4U)
+#define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
+#define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP1WM_Pos (8U)
+#define COMP_CSR_COMP1WM_Msk (0x1UL << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */
+#define COMP_CSR_COMP1LPTIM1IN1_Pos (12U)
+#define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP1POLARITY_Pos (15U)
+#define COMP_CSR_COMP1POLARITY_Msk (0x1UL << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1VALUE_Pos (30U)
+#define COMP_CSR_COMP1VALUE_Msk (0x1UL << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK_Pos (31U)
+#define COMP_CSR_COMP1LOCK_Msk (0x1UL << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN_Pos (0U)
+#define COMP_CSR_COMP2EN_Msk (0x1UL << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
+#define COMP_CSR_COMP2SPEED_Pos (3U)
+#define COMP_CSR_COMP2SPEED_Msk (0x1UL << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */
+#define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */
+#define COMP_CSR_COMP2INNSEL_Pos (4U)
+#define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */
+#define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
+#define COMP_CSR_COMP2INPSEL_Pos (8U)
+#define COMP_CSR_COMP2INPSEL_Msk (0x7UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */
+#define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2INPSEL_0 (0x1UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP2INPSEL_1 (0x2UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */
+#define COMP_CSR_COMP2INPSEL_2 (0x4UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */
+#define COMP_CSR_COMP2LPTIM1IN2_Pos (12U)
+#define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */
+#define COMP_CSR_COMP2LPTIM1IN1_Pos (13U)
+#define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */
+#define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP2POLARITY_Pos (15U)
+#define COMP_CSR_COMP2POLARITY_Msk (0x1UL << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2VALUE_Pos (30U)
+#define COMP_CSR_COMP2VALUE_Msk (0x1UL << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK_Pos (31U)
+#define COMP_CSR_COMP2LOCK_Msk (0x1UL << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
+
+/********************** Bit definition for COMP_CSR register common ****************/
+#define COMP_CSR_COMPxEN_Pos (0U)
+#define COMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
+#define COMP_CSR_COMPxPOLARITY_Pos (15U)
+#define COMP_CSR_COMPxPOLARITY_Msk (0x1UL << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */
+#define COMP_CSR_COMPxOUTVALUE_Pos (30U)
+#define COMP_CSR_COMPxOUTVALUE_Msk (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK_Pos (31U)
+#define COMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
+
+/* Reference defines */
+#define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR (0xFFU) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos (3U)
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos (5U)
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos (7U)
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT_Pos (0U)
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL_Pos (0U)
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* CRS Clock Recovery System */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRS_CR register *********************/
+#define CRS_CR_SYNCOKIE_Pos (0U)
+#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
+#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /* SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE_Pos (1U)
+#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
+#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /* SYNC warning interrupt enable */
+#define CRS_CR_ERRIE_Pos (2U)
+#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
+#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /* SYNC error interrupt enable */
+#define CRS_CR_ESYNCIE_Pos (3U)
+#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
+#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /* Expected SYNC(ESYNCF) interrupt Enable*/
+#define CRS_CR_CEN_Pos (5U)
+#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
+#define CRS_CR_CEN CRS_CR_CEN_Msk /* Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN_Pos (6U)
+#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
+#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /* Automatic trimming enable */
+#define CRS_CR_SWSYNC_Pos (7U)
+#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
+#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /* A Software SYNC event is generated */
+#define CRS_CR_TRIM_Pos (8U)
+#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
+#define CRS_CR_TRIM CRS_CR_TRIM_Msk /* HSI48 oscillator smooth trimming */
+
+/******************* Bit definition for CRS_CFGR register *********************/
+#define CRS_CFGR_RELOAD_Pos (0U)
+#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
+#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /* Counter reload value */
+#define CRS_CFGR_FELIM_Pos (16U)
+#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
+#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /* Frequency error limit */
+
+#define CRS_CFGR_SYNCDIV_Pos (24U)
+#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
+#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /* SYNC divider */
+#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
+#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
+#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
+
+#define CRS_CFGR_SYNCSRC_Pos (28U)
+#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
+#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /* SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
+#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
+
+#define CRS_CFGR_SYNCPOL_Pos (31U)
+#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
+#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /* SYNC polarity selection */
+
+/******************* Bit definition for CRS_ISR register *********************/
+#define CRS_ISR_SYNCOKF_Pos (0U)
+#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
+#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /* SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF_Pos (1U)
+#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
+#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /* SYNC warning */
+#define CRS_ISR_ERRF_Pos (2U)
+#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
+#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /* SYNC error flag */
+#define CRS_ISR_ESYNCF_Pos (3U)
+#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
+#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /* Expected SYNC flag */
+#define CRS_ISR_SYNCERR_Pos (8U)
+#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
+#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /* SYNC error */
+#define CRS_ISR_SYNCMISS_Pos (9U)
+#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
+#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /* SYNC missed */
+#define CRS_ISR_TRIMOVF_Pos (10U)
+#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
+#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /* Trimming overflow or underflow */
+#define CRS_ISR_FEDIR_Pos (15U)
+#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
+#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /* Frequency error direction */
+#define CRS_ISR_FECAP_Pos (16U)
+#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
+#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /* Frequency error capture */
+
+/******************* Bit definition for CRS_ICR register *********************/
+#define CRS_ICR_SYNCOKC_Pos (0U)
+#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
+#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /* SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC_Pos (1U)
+#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
+#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /* SYNC warning clear flag */
+#define CRS_ICR_ERRC_Pos (2U)
+#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
+#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /* Error clear flag */
+#define CRS_ICR_ESYNCC_Pos (3U)
+#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
+#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /* Expected SYNC clear flag */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter (DAC) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos (1U)
+#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos (2U)
+#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (3U)
+#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos (13U)
+#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun interrupt enable */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1_Pos (13U)
+#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_Pos (0U)
+#define DBGMCU_CR_DBG_Msk (0x7UL << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
+#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+
+/******************* Bit definition for DMA_CSELR register *******************/
+#define DMA_CSELR_C1S_Pos (0U)
+#define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
+#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos (4U)
+#define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
+#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos (8U)
+#define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
+#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos (12U)
+#define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
+#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos (16U)
+#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
+#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S_Pos (20U)
+#define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
+#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S_Pos (24U)
+#define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
+#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_IM0_Pos (0U)
+#define EXTI_IMR_IM0_Msk (0x1UL << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_IM1_Pos (1U)
+#define EXTI_IMR_IM1_Msk (0x1UL << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_IM2_Pos (2U)
+#define EXTI_IMR_IM2_Msk (0x1UL << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_IM3_Pos (3U)
+#define EXTI_IMR_IM3_Msk (0x1UL << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_IM4_Pos (4U)
+#define EXTI_IMR_IM4_Msk (0x1UL << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_IM5_Pos (5U)
+#define EXTI_IMR_IM5_Msk (0x1UL << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_IM6_Pos (6U)
+#define EXTI_IMR_IM6_Msk (0x1UL << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_IM7_Pos (7U)
+#define EXTI_IMR_IM7_Msk (0x1UL << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_IM8_Pos (8U)
+#define EXTI_IMR_IM8_Msk (0x1UL << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_IM9_Pos (9U)
+#define EXTI_IMR_IM9_Msk (0x1UL << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_IM10_Pos (10U)
+#define EXTI_IMR_IM10_Msk (0x1UL << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_IM11_Pos (11U)
+#define EXTI_IMR_IM11_Msk (0x1UL << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_IM12_Pos (12U)
+#define EXTI_IMR_IM12_Msk (0x1UL << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_IM13_Pos (13U)
+#define EXTI_IMR_IM13_Msk (0x1UL << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_IM14_Pos (14U)
+#define EXTI_IMR_IM14_Msk (0x1UL << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_IM15_Pos (15U)
+#define EXTI_IMR_IM15_Msk (0x1UL << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_IM16_Pos (16U)
+#define EXTI_IMR_IM16_Msk (0x1UL << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_IM17_Pos (17U)
+#define EXTI_IMR_IM17_Msk (0x1UL << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_IM18_Pos (18U)
+#define EXTI_IMR_IM18_Msk (0x1UL << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_IM19_Pos (19U)
+#define EXTI_IMR_IM19_Msk (0x1UL << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_IM20_Pos (20U)
+#define EXTI_IMR_IM20_Msk (0x1UL << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_IM21_Pos (21U)
+#define EXTI_IMR_IM21_Msk (0x1UL << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_IM22_Pos (22U)
+#define EXTI_IMR_IM22_Msk (0x1UL << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_IM23_Pos (23U)
+#define EXTI_IMR_IM23_Msk (0x1UL << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
+#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_IM25_Pos (25U)
+#define EXTI_IMR_IM25_Msk (0x1UL << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */
+#define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_IM26_Pos (26U)
+#define EXTI_IMR_IM26_Msk (0x1UL << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
+#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_IM28_Pos (28U)
+#define EXTI_IMR_IM28_Msk (0x1UL << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
+#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_IM29_Pos (29U)
+#define EXTI_IMR_IM29_Msk (0x1UL << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
+#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
+
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x36FFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x36FFFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_EM0_Pos (0U)
+#define EXTI_EMR_EM0_Msk (0x1UL << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_EM1_Pos (1U)
+#define EXTI_EMR_EM1_Msk (0x1UL << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_EM2_Pos (2U)
+#define EXTI_EMR_EM2_Msk (0x1UL << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_EM3_Pos (3U)
+#define EXTI_EMR_EM3_Msk (0x1UL << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_EM4_Pos (4U)
+#define EXTI_EMR_EM4_Msk (0x1UL << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_EM5_Pos (5U)
+#define EXTI_EMR_EM5_Msk (0x1UL << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_EM6_Pos (6U)
+#define EXTI_EMR_EM6_Msk (0x1UL << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_EM7_Pos (7U)
+#define EXTI_EMR_EM7_Msk (0x1UL << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_EM8_Pos (8U)
+#define EXTI_EMR_EM8_Msk (0x1UL << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_EM9_Pos (9U)
+#define EXTI_EMR_EM9_Msk (0x1UL << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_EM10_Pos (10U)
+#define EXTI_EMR_EM10_Msk (0x1UL << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_EM11_Pos (11U)
+#define EXTI_EMR_EM11_Msk (0x1UL << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_EM12_Pos (12U)
+#define EXTI_EMR_EM12_Msk (0x1UL << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_EM13_Pos (13U)
+#define EXTI_EMR_EM13_Msk (0x1UL << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_EM14_Pos (14U)
+#define EXTI_EMR_EM14_Msk (0x1UL << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_EM15_Pos (15U)
+#define EXTI_EMR_EM15_Msk (0x1UL << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_EM16_Pos (16U)
+#define EXTI_EMR_EM16_Msk (0x1UL << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_EM17_Pos (17U)
+#define EXTI_EMR_EM17_Msk (0x1UL << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_EM18_Pos (18U)
+#define EXTI_EMR_EM18_Msk (0x1UL << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_EM19_Pos (19U)
+#define EXTI_EMR_EM19_Msk (0x1UL << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_EM20_Pos (20U)
+#define EXTI_EMR_EM20_Msk (0x1UL << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_EM21_Pos (21U)
+#define EXTI_EMR_EM21_Msk (0x1UL << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_EM22_Pos (22U)
+#define EXTI_EMR_EM22_Msk (0x1UL << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */
+#define EXTI_EMR_EM23_Pos (23U)
+#define EXTI_EMR_EM23_Msk (0x1UL << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
+#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
+#define EXTI_EMR_EM25_Pos (25U)
+#define EXTI_EMR_EM25_Msk (0x1UL << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */
+#define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */
+#define EXTI_EMR_EM26_Pos (26U)
+#define EXTI_EMR_EM26_Msk (0x1UL << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
+#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
+#define EXTI_EMR_EM28_Pos (28U)
+#define EXTI_EMR_EM28_Msk (0x1UL << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
+#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
+#define EXTI_EMR_EM29_Pos (29U)
+#define EXTI_EMR_EM29_Msk (0x1UL << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
+#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_RT0_Pos (0U)
+#define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_RT1_Pos (1U)
+#define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_RT2_Pos (2U)
+#define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_RT3_Pos (3U)
+#define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_RT4_Pos (4U)
+#define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_RT5_Pos (5U)
+#define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_RT6_Pos (6U)
+#define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_RT7_Pos (7U)
+#define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_RT8_Pos (8U)
+#define EXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_RT9_Pos (9U)
+#define EXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_RT10_Pos (10U)
+#define EXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_RT11_Pos (11U)
+#define EXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_RT12_Pos (12U)
+#define EXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_RT13_Pos (13U)
+#define EXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_RT14_Pos (14U)
+#define EXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_RT15_Pos (15U)
+#define EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_RT16_Pos (16U)
+#define EXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_RT17_Pos (17U)
+#define EXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_RT19_Pos (19U)
+#define EXTI_RTSR_RT19_Msk (0x1UL << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_RT20_Pos (20U)
+#define EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_RT21_Pos (21U)
+#define EXTI_RTSR_RT21_Msk (0x1UL << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_RT22_Pos (22U)
+#define EXTI_RTSR_RT22_Msk (0x1UL << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
+#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
+#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
+#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
+#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
+#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
+#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
+#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
+#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
+#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
+#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
+#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
+#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
+#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
+#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
+#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
+#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
+#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
+#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
+#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
+#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
+#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_FT0_Pos (0U)
+#define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_FT1_Pos (1U)
+#define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_FT2_Pos (2U)
+#define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_FT3_Pos (3U)
+#define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_FT4_Pos (4U)
+#define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_FT5_Pos (5U)
+#define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_FT6_Pos (6U)
+#define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_FT7_Pos (7U)
+#define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_FT8_Pos (8U)
+#define EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_FT9_Pos (9U)
+#define EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_FT10_Pos (10U)
+#define EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_FT11_Pos (11U)
+#define EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_FT12_Pos (12U)
+#define EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_FT13_Pos (13U)
+#define EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_FT14_Pos (14U)
+#define EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_FT15_Pos (15U)
+#define EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_FT16_Pos (16U)
+#define EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_FT17_Pos (17U)
+#define EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_FT19_Pos (19U)
+#define EXTI_FTSR_FT19_Msk (0x1UL << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_FT20_Pos (20U)
+#define EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_FT21_Pos (21U)
+#define EXTI_FTSR_FT21_Msk (0x1UL << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_FT22_Pos (22U)
+#define EXTI_FTSR_FT22_Msk (0x1UL << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
+#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
+#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
+#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
+#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
+#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
+#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
+#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
+#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
+#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
+#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
+#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
+#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
+#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
+#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
+#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
+#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
+#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
+#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
+#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
+#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
+#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWI0_Pos (0U)
+#define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWI1_Pos (1U)
+#define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWI2_Pos (2U)
+#define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWI3_Pos (3U)
+#define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWI4_Pos (4U)
+#define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWI5_Pos (5U)
+#define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWI6_Pos (6U)
+#define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWI7_Pos (7U)
+#define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWI8_Pos (8U)
+#define EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWI9_Pos (9U)
+#define EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWI10_Pos (10U)
+#define EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWI11_Pos (11U)
+#define EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWI12_Pos (12U)
+#define EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWI13_Pos (13U)
+#define EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWI14_Pos (14U)
+#define EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWI15_Pos (15U)
+#define EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWI16_Pos (16U)
+#define EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWI17_Pos (17U)
+#define EXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWI19_Pos (19U)
+#define EXTI_SWIER_SWI19_Msk (0x1UL << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWI20_Pos (20U)
+#define EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWI21_Pos (21U)
+#define EXTI_SWIER_SWI21_Msk (0x1UL << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWI22_Pos (22U)
+#define EXTI_SWIER_SWI22_Msk (0x1UL << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
+
+/* Legacy defines */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PIF0_Pos (0U)
+#define EXTI_PR_PIF0_Msk (0x1UL << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
+#define EXTI_PR_PIF1_Pos (1U)
+#define EXTI_PR_PIF1_Msk (0x1UL << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
+#define EXTI_PR_PIF2_Pos (2U)
+#define EXTI_PR_PIF2_Msk (0x1UL << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
+#define EXTI_PR_PIF3_Pos (3U)
+#define EXTI_PR_PIF3_Msk (0x1UL << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
+#define EXTI_PR_PIF4_Pos (4U)
+#define EXTI_PR_PIF4_Msk (0x1UL << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
+#define EXTI_PR_PIF5_Pos (5U)
+#define EXTI_PR_PIF5_Msk (0x1UL << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
+#define EXTI_PR_PIF6_Pos (6U)
+#define EXTI_PR_PIF6_Msk (0x1UL << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
+#define EXTI_PR_PIF7_Pos (7U)
+#define EXTI_PR_PIF7_Msk (0x1UL << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
+#define EXTI_PR_PIF8_Pos (8U)
+#define EXTI_PR_PIF8_Msk (0x1UL << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
+#define EXTI_PR_PIF9_Pos (9U)
+#define EXTI_PR_PIF9_Msk (0x1UL << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
+#define EXTI_PR_PIF10_Pos (10U)
+#define EXTI_PR_PIF10_Msk (0x1UL << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
+#define EXTI_PR_PIF11_Pos (11U)
+#define EXTI_PR_PIF11_Msk (0x1UL << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
+#define EXTI_PR_PIF12_Pos (12U)
+#define EXTI_PR_PIF12_Msk (0x1UL << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
+#define EXTI_PR_PIF13_Pos (13U)
+#define EXTI_PR_PIF13_Msk (0x1UL << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
+#define EXTI_PR_PIF14_Pos (14U)
+#define EXTI_PR_PIF14_Msk (0x1UL << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
+#define EXTI_PR_PIF15_Pos (15U)
+#define EXTI_PR_PIF15_Msk (0x1UL << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
+#define EXTI_PR_PIF16_Pos (16U)
+#define EXTI_PR_PIF16_Msk (0x1UL << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
+#define EXTI_PR_PIF17_Pos (17U)
+#define EXTI_PR_PIF17_Msk (0x1UL << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
+#define EXTI_PR_PIF19_Pos (19U)
+#define EXTI_PR_PIF19_Msk (0x1UL << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
+#define EXTI_PR_PIF20_Pos (20U)
+#define EXTI_PR_PIF20_Msk (0x1UL << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
+#define EXTI_PR_PIF21_Pos (21U)
+#define EXTI_PR_PIF21_Msk (0x1UL << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
+#define EXTI_PR_PIF22_Pos (22U)
+#define EXTI_PR_PIF22_Msk (0x1UL << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
+
+/* Legacy defines */
+#define EXTI_PR_PR0 EXTI_PR_PIF0
+#define EXTI_PR_PR1 EXTI_PR_PIF1
+#define EXTI_PR_PR2 EXTI_PR_PIF2
+#define EXTI_PR_PR3 EXTI_PR_PIF3
+#define EXTI_PR_PR4 EXTI_PR_PIF4
+#define EXTI_PR_PR5 EXTI_PR_PIF5
+#define EXTI_PR_PR6 EXTI_PR_PIF6
+#define EXTI_PR_PR7 EXTI_PR_PIF7
+#define EXTI_PR_PR8 EXTI_PR_PIF8
+#define EXTI_PR_PR9 EXTI_PR_PIF9
+#define EXTI_PR_PR10 EXTI_PR_PIF10
+#define EXTI_PR_PR11 EXTI_PR_PIF11
+#define EXTI_PR_PR12 EXTI_PR_PIF12
+#define EXTI_PR_PR13 EXTI_PR_PIF13
+#define EXTI_PR_PR14 EXTI_PR_PIF14
+#define EXTI_PR_PR15 EXTI_PR_PIF15
+#define EXTI_PR_PR16 EXTI_PR_PIF16
+#define EXTI_PR_PR17 EXTI_PR_PIF17
+#define EXTI_PR_PR19 EXTI_PR_PIF19
+#define EXTI_PR_PR20 EXTI_PR_PIF20
+#define EXTI_PR_PR21 EXTI_PR_PIF21
+#define EXTI_PR_PR22 EXTI_PR_PIF22
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
+#define FLASH_ACR_PRFTEN_Pos (1U)
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_SLEEP_PD_Pos (3U)
+#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD_Pos (4U)
+#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
+#define FLASH_ACR_DISAB_BUF_Pos (5U)
+#define FLASH_ACR_DISAB_BUF_Msk (0x1UL << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
+#define FLASH_ACR_PRE_READ_Pos (6U)
+#define FLASH_ACR_PRE_READ_Msk (0x1UL << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
+#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
+
+/******************* Bit definition for FLASH_PECR register ******************/
+#define FLASH_PECR_PELOCK_Pos (0U)
+#define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
+#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK_Pos (1U)
+#define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
+#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK_Pos (2U)
+#define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
+#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG_Pos (3U)
+#define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
+#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
+#define FLASH_PECR_DATA_Pos (4U)
+#define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
+#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
+#define FLASH_PECR_FIX_Pos (8U)
+#define FLASH_PECR_FIX_Msk (0x1UL << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
+#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE_Pos (9U)
+#define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
+#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
+#define FLASH_PECR_FPRG_Pos (10U)
+#define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
+#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_EOPIE_Pos (16U)
+#define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
+#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
+#define FLASH_PECR_ERRIE_Pos (17U)
+#define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
+#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
+#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
+#define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
+#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
+#define FLASH_PECR_HALF_ARRAY_Pos (19U)
+#define FLASH_PECR_HALF_ARRAY_Msk (0x1UL << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
+#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
+
+/****************** Bit definition for FLASH_PDKEYR register ******************/
+#define FLASH_PDKEYR_PDKEYR_Pos (0U)
+#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PEKEYR register ******************/
+#define FLASH_PEKEYR_PEKEYR_Pos (0U)
+#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PRGKEYR register ******************/
+#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
+#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
+
+/****************** Bit definition for FLASH_OPTKEYR register ******************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_EOP_Pos (1U)
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
+#define FLASH_SR_HVOFF_Pos (2U)
+#define FLASH_SR_HVOFF_Msk (0x1UL << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
+#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
+#define FLASH_SR_READY_Pos (3U)
+#define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */
+#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR_Pos (8U)
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
+#define FLASH_SR_PGAERR_Pos (9U)
+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR_Pos (10U)
+#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
+#define FLASH_SR_OPTVERR_Pos (11U)
+#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
+#define FLASH_SR_RDERR_Pos (13U)
+#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
+#define FLASH_SR_NOTZEROERR_Pos (16U)
+#define FLASH_SR_NOTZEROERR_Msk (0x1UL << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
+#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
+#define FLASH_SR_FWWERR_Pos (17U)
+#define FLASH_SR_FWWERR_Msk (0x1UL << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
+#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
+
+/* Legacy defines */
+#define FLASH_SR_FWWER FLASH_SR_FWWERR
+#define FLASH_SR_ENHV FLASH_SR_HVOFF
+#define FLASH_SR_ENDHV FLASH_SR_HVOFF
+
+/****************** Bit definition for FLASH_OPTR register *******************/
+#define FLASH_OPTR_RDPROT_Pos (0U)
+#define FLASH_OPTR_RDPROT_Msk (0xFFUL << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
+#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
+#define FLASH_OPTR_WPRMOD_Pos (8U)
+#define FLASH_OPTR_WPRMOD_Msk (0x1UL << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
+#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
+#define FLASH_OPTR_BOR_LEV_Pos (16U)
+#define FLASH_OPTR_BOR_LEV_Msk (0xFUL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
+#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OPTR_IWDG_SW_Pos (20U)
+#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
+#define FLASH_OPTR_nRST_STOP_Pos (21U)
+#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OPTR_nRST_STDBY_Pos (22U)
+#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OPTR_USER_Pos (20U)
+#define FLASH_OPTR_USER_Msk (0x7UL << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
+#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OPTR_BOOT1_Pos (31U)
+#define FLASH_OPTR_BOOT1_Msk (0x1UL << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
+#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 (0x00000001U)
+#define GPIO_OTYPER_OT_1 (0x00000002U)
+#define GPIO_OTYPER_OT_2 (0x00000004U)
+#define GPIO_OTYPER_OT_3 (0x00000008U)
+#define GPIO_OTYPER_OT_4 (0x00000010U)
+#define GPIO_OTYPER_OT_5 (0x00000020U)
+#define GPIO_OTYPER_OT_6 (0x00000040U)
+#define GPIO_OTYPER_OT_7 (0x00000080U)
+#define GPIO_OTYPER_OT_8 (0x00000100U)
+#define GPIO_OTYPER_OT_9 (0x00000200U)
+#define GPIO_OTYPER_OT_10 (0x00000400U)
+#define GPIO_OTYPER_OT_11 (0x00000800U)
+#define GPIO_OTYPER_OT_12 (0x00001000U)
+#define GPIO_OTYPER_OT_13 (0x00002000U)
+#define GPIO_OTYPER_OT_14 (0x00004000U)
+#define GPIO_OTYPER_OT_15 (0x00008000U)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDER_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
+#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDER_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
+#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDER_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
+#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDER_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
+#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDER_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
+#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDER_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
+#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDER_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
+#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDER_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
+#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDER_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
+#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDER_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
+#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDER_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
+#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDER_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
+#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDER_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
+#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDER_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
+#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDER_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
+#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDER_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
+#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 (0x00000001U)
+#define GPIO_BSRR_BS_1 (0x00000002U)
+#define GPIO_BSRR_BS_2 (0x00000004U)
+#define GPIO_BSRR_BS_3 (0x00000008U)
+#define GPIO_BSRR_BS_4 (0x00000010U)
+#define GPIO_BSRR_BS_5 (0x00000020U)
+#define GPIO_BSRR_BS_6 (0x00000040U)
+#define GPIO_BSRR_BS_7 (0x00000080U)
+#define GPIO_BSRR_BS_8 (0x00000100U)
+#define GPIO_BSRR_BS_9 (0x00000200U)
+#define GPIO_BSRR_BS_10 (0x00000400U)
+#define GPIO_BSRR_BS_11 (0x00000800U)
+#define GPIO_BSRR_BS_12 (0x00001000U)
+#define GPIO_BSRR_BS_13 (0x00002000U)
+#define GPIO_BSRR_BS_14 (0x00004000U)
+#define GPIO_BSRR_BS_15 (0x00008000U)
+#define GPIO_BSRR_BR_0 (0x00010000U)
+#define GPIO_BSRR_BR_1 (0x00020000U)
+#define GPIO_BSRR_BR_2 (0x00040000U)
+#define GPIO_BSRR_BR_3 (0x00080000U)
+#define GPIO_BSRR_BR_4 (0x00100000U)
+#define GPIO_BSRR_BR_5 (0x00200000U)
+#define GPIO_BSRR_BR_6 (0x00400000U)
+#define GPIO_BSRR_BR_7 (0x00800000U)
+#define GPIO_BSRR_BR_8 (0x01000000U)
+#define GPIO_BSRR_BR_9 (0x02000000U)
+#define GPIO_BSRR_BR_10 (0x04000000U)
+#define GPIO_BSRR_BR_11 (0x08000000U)
+#define GPIO_BSRR_BR_12 (0x10000000U)
+#define GPIO_BSRR_BR_13 (0x20000000U)
+#define GPIO_BSRR_BR_14 (0x40000000U)
+#define GPIO_BSRR_BR_15 (0x80000000U)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 (0x00000001U)
+#define GPIO_BRR_BR_1 (0x00000002U)
+#define GPIO_BRR_BR_2 (0x00000004U)
+#define GPIO_BRR_BR_3 (0x00000008U)
+#define GPIO_BRR_BR_4 (0x00000010U)
+#define GPIO_BRR_BR_5 (0x00000020U)
+#define GPIO_BRR_BR_6 (0x00000040U)
+#define GPIO_BRR_BR_7 (0x00000080U)
+#define GPIO_BRR_BR_8 (0x00000100U)
+#define GPIO_BRR_BR_9 (0x00000200U)
+#define GPIO_BRR_BR_10 (0x00000400U)
+#define GPIO_BRR_BR_11 (0x00000800U)
+#define GPIO_BRR_BR_12 (0x00001000U)
+#define GPIO_BRR_BR_13 (0x00002000U)
+#define GPIO_BRR_BR_14 (0x00004000U)
+#define GPIO_BRR_BR_15 (0x00008000U)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos (1U)
+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos (2U)
+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos (3U)
+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos (4U)
+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos (5U)
+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos (6U)
+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos (7U)
+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos (8U)
+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos (12U)
+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos (14U)
+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos (15U)
+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos (16U)
+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos (17U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos (18U)
+#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos (19U)
+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos (20U)
+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos (21U)
+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos (22U)
+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos (23U)
+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD_Pos (0U)
+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos (10U)
+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos (11U)
+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos (12U)
+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos (13U)
+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
+#define I2C_CR2_STOP_Pos (14U)
+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos (15U)
+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos (16U)
+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos (24U)
+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos (25U)
+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos (26U)
+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1_Pos (0U)
+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos (10U)
+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos (15U)
+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2_Pos (1U)
+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos (8U)
+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos (8U)
+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos (9U)
+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos (8U)
+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos (10U)
+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos (8U)
+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos (9U)
+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos (8U)
+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos (15U)
+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos (0U)
+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos (8U)
+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos (16U)
+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos (20U)
+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos (28U)
+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE_Pos (0U)
+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos (1U)
+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos (2U)
+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos (3U)
+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos (4U)
+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos (5U)
+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos (6U)
+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos (7U)
+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos (8U)
+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
+#define I2C_ISR_ARLO_Pos (9U)
+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos (10U)
+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos (11U)
+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos (12U)
+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos (13U)
+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos (15U)
+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
+#define I2C_ISR_DIR_Pos (16U)
+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos (17U)
+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF_Pos (3U)
+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos (4U)
+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos (5U)
+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos (8U)
+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos (9U)
+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos (10U)
+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos (11U)
+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos (12U)
+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos (13U)
+#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define I2C_PECR_PEC_Pos (0U)
+#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA_Pos (0U)
+#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA_Pos (0U)
+#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos (2U)
+#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN_Pos (0U)
+#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* LCD Controller (LCD) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for LCD_CR register *********************/
+#define LCD_CR_LCDEN_Pos (0U)
+#define LCD_CR_LCDEN_Msk (0x1UL << LCD_CR_LCDEN_Pos) /*!< 0x00000001 */
+#define LCD_CR_LCDEN LCD_CR_LCDEN_Msk /*!< LCD Enable Bit */
+#define LCD_CR_VSEL_Pos (1U)
+#define LCD_CR_VSEL_Msk (0x1UL << LCD_CR_VSEL_Pos) /*!< 0x00000002 */
+#define LCD_CR_VSEL LCD_CR_VSEL_Msk /*!< Voltage source selector Bit */
+
+#define LCD_CR_DUTY_Pos (2U)
+#define LCD_CR_DUTY_Msk (0x7UL << LCD_CR_DUTY_Pos) /*!< 0x0000001C */
+#define LCD_CR_DUTY LCD_CR_DUTY_Msk /*!< DUTY[2:0] bits (Duty selector) */
+#define LCD_CR_DUTY_0 (0x1UL << LCD_CR_DUTY_Pos) /*!< 0x00000004 */
+#define LCD_CR_DUTY_1 (0x2UL << LCD_CR_DUTY_Pos) /*!< 0x00000008 */
+#define LCD_CR_DUTY_2 (0x4UL << LCD_CR_DUTY_Pos) /*!< 0x00000010 */
+
+#define LCD_CR_BIAS_Pos (5U)
+#define LCD_CR_BIAS_Msk (0x3UL << LCD_CR_BIAS_Pos) /*!< 0x00000060 */
+#define LCD_CR_BIAS LCD_CR_BIAS_Msk /*!< BIAS[1:0] bits (Bias selector) */
+#define LCD_CR_BIAS_0 (0x1UL << LCD_CR_BIAS_Pos) /*!< 0x00000020 */
+#define LCD_CR_BIAS_1 (0x2UL << LCD_CR_BIAS_Pos) /*!< 0x00000040 */
+
+#define LCD_CR_MUX_SEG_Pos (7U)
+#define LCD_CR_MUX_SEG_Msk (0x1UL << LCD_CR_MUX_SEG_Pos) /*!< 0x00000080 */
+#define LCD_CR_MUX_SEG LCD_CR_MUX_SEG_Msk /*!< Mux Segment Enable Bit */
+
+#define LCD_CR_BUFEN_Pos (8U)
+#define LCD_CR_BUFEN_Msk (0x1UL << LCD_CR_BUFEN_Pos) /*!< 0x00000100 */
+#define LCD_CR_BUFEN LCD_CR_BUFEN_Msk /*!< Voltage output buffer enable Bit */
+
+/******************* Bit definition for LCD_FCR register ********************/
+#define LCD_FCR_HD_Pos (0U)
+#define LCD_FCR_HD_Msk (0x1UL << LCD_FCR_HD_Pos) /*!< 0x00000001 */
+#define LCD_FCR_HD LCD_FCR_HD_Msk /*!< High Drive Enable Bit */
+#define LCD_FCR_SOFIE_Pos (1U)
+#define LCD_FCR_SOFIE_Msk (0x1UL << LCD_FCR_SOFIE_Pos) /*!< 0x00000002 */
+#define LCD_FCR_SOFIE LCD_FCR_SOFIE_Msk /*!< Start of Frame Interrupt Enable Bit */
+#define LCD_FCR_UDDIE_Pos (3U)
+#define LCD_FCR_UDDIE_Msk (0x1UL << LCD_FCR_UDDIE_Pos) /*!< 0x00000008 */
+#define LCD_FCR_UDDIE LCD_FCR_UDDIE_Msk /*!< Update Display Done Interrupt Enable Bit */
+
+#define LCD_FCR_PON_Pos (4U)
+#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */
+#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */
+#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */
+#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */
+
+#define LCD_FCR_DEAD_Pos (7U)
+#define LCD_FCR_DEAD_Msk (0x7UL << LCD_FCR_DEAD_Pos) /*!< 0x00000380 */
+#define LCD_FCR_DEAD LCD_FCR_DEAD_Msk /*!< DEAD[2:0] bits (DEAD Time) */
+#define LCD_FCR_DEAD_0 (0x1UL << LCD_FCR_DEAD_Pos) /*!< 0x00000080 */
+#define LCD_FCR_DEAD_1 (0x2UL << LCD_FCR_DEAD_Pos) /*!< 0x00000100 */
+#define LCD_FCR_DEAD_2 (0x4UL << LCD_FCR_DEAD_Pos) /*!< 0x00000200 */
+
+#define LCD_FCR_CC_Pos (10U)
+#define LCD_FCR_CC_Msk (0x7UL << LCD_FCR_CC_Pos) /*!< 0x00001C00 */
+#define LCD_FCR_CC LCD_FCR_CC_Msk /*!< CC[2:0] bits (Contrast Control) */
+#define LCD_FCR_CC_0 (0x1UL << LCD_FCR_CC_Pos) /*!< 0x00000400 */
+#define LCD_FCR_CC_1 (0x2UL << LCD_FCR_CC_Pos) /*!< 0x00000800 */
+#define LCD_FCR_CC_2 (0x4UL << LCD_FCR_CC_Pos) /*!< 0x00001000 */
+
+#define LCD_FCR_BLINKF_Pos (13U)
+#define LCD_FCR_BLINKF_Msk (0x7UL << LCD_FCR_BLINKF_Pos) /*!< 0x0000E000 */
+#define LCD_FCR_BLINKF LCD_FCR_BLINKF_Msk /*!< BLINKF[2:0] bits (Blink Frequency) */
+#define LCD_FCR_BLINKF_0 (0x1UL << LCD_FCR_BLINKF_Pos) /*!< 0x00002000 */
+#define LCD_FCR_BLINKF_1 (0x2UL << LCD_FCR_BLINKF_Pos) /*!< 0x00004000 */
+#define LCD_FCR_BLINKF_2 (0x4UL << LCD_FCR_BLINKF_Pos) /*!< 0x00008000 */
+
+#define LCD_FCR_BLINK_Pos (16U)
+#define LCD_FCR_BLINK_Msk (0x3UL << LCD_FCR_BLINK_Pos) /*!< 0x00030000 */
+#define LCD_FCR_BLINK LCD_FCR_BLINK_Msk /*!< BLINK[1:0] bits (Blink Enable) */
+#define LCD_FCR_BLINK_0 (0x1UL << LCD_FCR_BLINK_Pos) /*!< 0x00010000 */
+#define LCD_FCR_BLINK_1 (0x2UL << LCD_FCR_BLINK_Pos) /*!< 0x00020000 */
+
+#define LCD_FCR_DIV_Pos (18U)
+#define LCD_FCR_DIV_Msk (0xFUL << LCD_FCR_DIV_Pos) /*!< 0x003C0000 */
+#define LCD_FCR_DIV LCD_FCR_DIV_Msk /*!< DIV[3:0] bits (Divider) */
+#define LCD_FCR_PS_Pos (22U)
+#define LCD_FCR_PS_Msk (0xFUL << LCD_FCR_PS_Pos) /*!< 0x03C00000 */
+#define LCD_FCR_PS LCD_FCR_PS_Msk /*!< PS[3:0] bits (Prescaler) */
+
+/******************* Bit definition for LCD_SR register *********************/
+#define LCD_SR_ENS_Pos (0U)
+#define LCD_SR_ENS_Msk (0x1UL << LCD_SR_ENS_Pos) /*!< 0x00000001 */
+#define LCD_SR_ENS LCD_SR_ENS_Msk /*!< LCD Enabled Bit */
+#define LCD_SR_SOF_Pos (1U)
+#define LCD_SR_SOF_Msk (0x1UL << LCD_SR_SOF_Pos) /*!< 0x00000002 */
+#define LCD_SR_SOF LCD_SR_SOF_Msk /*!< Start Of Frame Flag Bit */
+#define LCD_SR_UDR_Pos (2U)
+#define LCD_SR_UDR_Msk (0x1UL << LCD_SR_UDR_Pos) /*!< 0x00000004 */
+#define LCD_SR_UDR LCD_SR_UDR_Msk /*!< Update Display Request Bit */
+#define LCD_SR_UDD_Pos (3U)
+#define LCD_SR_UDD_Msk (0x1UL << LCD_SR_UDD_Pos) /*!< 0x00000008 */
+#define LCD_SR_UDD LCD_SR_UDD_Msk /*!< Update Display Done Flag Bit */
+#define LCD_SR_RDY_Pos (4U)
+#define LCD_SR_RDY_Msk (0x1UL << LCD_SR_RDY_Pos) /*!< 0x00000010 */
+#define LCD_SR_RDY LCD_SR_RDY_Msk /*!< Ready Flag Bit */
+#define LCD_SR_FCRSR_Pos (5U)
+#define LCD_SR_FCRSR_Msk (0x1UL << LCD_SR_FCRSR_Pos) /*!< 0x00000020 */
+#define LCD_SR_FCRSR LCD_SR_FCRSR_Msk /*!< LCD FCR Register Synchronization Flag Bit */
+
+/******************* Bit definition for LCD_CLR register ********************/
+#define LCD_CLR_SOFC_Pos (1U)
+#define LCD_CLR_SOFC_Msk (0x1UL << LCD_CLR_SOFC_Pos) /*!< 0x00000002 */
+#define LCD_CLR_SOFC LCD_CLR_SOFC_Msk /*!< Start Of Frame Flag Clear Bit */
+#define LCD_CLR_UDDC_Pos (3U)
+#define LCD_CLR_UDDC_Msk (0x1UL << LCD_CLR_UDDC_Pos) /*!< 0x00000008 */
+#define LCD_CLR_UDDC LCD_CLR_UDDC_Msk /*!< Update Display Done Flag Clear Bit */
+
+/******************* Bit definition for LCD_RAM register ********************/
+#define LCD_RAM_SEGMENT_DATA_Pos (0U)
+#define LCD_RAM_SEGMENT_DATA_Msk (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos) /*!< 0xFFFFFFFF */
+#define LCD_RAM_SEGMENT_DATA LCD_RAM_SEGMENT_DATA_Msk /*!< Segment Data Bits */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM_Pos (0U)
+#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos (1U)
+#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos (2U)
+#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos (3U)
+#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos (4U)
+#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos (5U)
+#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos (6U)
+#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF_Pos (0U)
+#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos (1U)
+#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos (3U)
+#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos (4U)
+#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos (5U)
+#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos (6U)
+#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos (0U)
+#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos (1U)
+#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos (3U)
+#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos (4U)
+#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos (5U)
+#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos (6U)
+#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos (0U)
+#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos (1U)
+#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos (3U)
+#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos (6U)
+#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos (9U)
+#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos (17U)
+#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos (19U)
+#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos (20U)
+#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos (21U)
+#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos (22U)
+#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos (24U)
+#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE_Pos (0U)
+#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos (1U)
+#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos (2U)
+#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP_Pos (0U)
+#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR_Pos (0U)
+#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT_Pos (0U)
+#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
+
+/******************************************************************************/
+/* */
+/* MIFARE Firewall */
+/* */
+/******************************************************************************/
+
+/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
+#define FW_CSSA_ADD_Pos (8U)
+#define FW_CSSA_ADD_Msk (0xFFFFUL << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
+#define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
+#define FW_CSL_LENG_Pos (8U)
+#define FW_CSL_LENG_Msk (0x3FFFUL << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
+#define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
+#define FW_NVDSSA_ADD_Pos (8U)
+#define FW_NVDSSA_ADD_Msk (0xFFFFUL << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
+#define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
+#define FW_NVDSL_LENG_Pos (8U)
+#define FW_NVDSL_LENG_Msk (0x3FFFUL << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
+#define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
+#define FW_VDSSA_ADD_Pos (6U)
+#define FW_VDSSA_ADD_Msk (0x3FFUL << FW_VDSSA_ADD_Pos) /*!< 0x0000FFC0 */
+#define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
+#define FW_VDSL_LENG_Pos (6U)
+#define FW_VDSL_LENG_Msk (0x3FFUL << FW_VDSL_LENG_Pos) /*!< 0x0000FFC0 */
+#define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
+
+/**************************Bit definition for CR register *********************/
+#define FW_CR_FPA_Pos (0U)
+#define FW_CR_FPA_Msk (0x1UL << FW_CR_FPA_Pos) /*!< 0x00000001 */
+#define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
+#define FW_CR_VDS_Pos (1U)
+#define FW_CR_VDS_Msk (0x1UL << FW_CR_VDS_Pos) /*!< 0x00000002 */
+#define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
+#define FW_CR_VDE_Pos (2U)
+#define FW_CR_VDE_Msk (0x1UL << FW_CR_VDE_Pos) /*!< 0x00000004 */
+#define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
+
+/******************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/******************************************************************************/
+
+#define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPSDSR_Pos (0U)
+#define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP_Pos (9U)
+#define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /*!< 0x00000200 */
+#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
+#define PWR_CR_FWU_Pos (10U)
+#define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /*!< 0x00000400 */
+#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
+
+#define PWR_CR_VOS_Pos (11U)
+#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x00001800 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /*!< 0x00000800 */
+#define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /*!< 0x00001000 */
+#define PWR_CR_DSEEKOFF_Pos (13U)
+#define PWR_CR_DSEEKOFF_Msk (0x1UL << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */
+#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */
+#define PWR_CR_LPRUN_Pos (14U)
+#define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
+#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF_Pos (3U)
+#define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
+#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF_Pos (4U)
+#define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
+#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF_Pos (5U)
+#define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
+#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1_Pos (8U)
+#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2_Pos (9U)
+#define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
+#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+#define RCC_HSI48_SUPPORT /*!< HSI48 feature support */
+#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos (1U)
+#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos (2U)
+#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIVEN_Pos (3U)
+#define RCC_CR_HSIDIVEN_Msk (0x1UL << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */
+#define RCC_CR_HSIDIVF_Pos (4U)
+#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */
+#define RCC_CR_MSION_Pos (8U)
+#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000100 */
+#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY_Pos (9U)
+#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
+#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON_Pos (19U)
+#define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */
+#define RCC_CR_RTCPRE_Pos (20U)
+#define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
+#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC/LCD prescaler [1:0] bits */
+#define RCC_CR_RTCPRE_0 (0x1UL << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */
+#define RCC_CR_RTCPRE_1 (0x2UL << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+/* Reference defines */
+#define RCC_CR_CSSON RCC_CR_CSSHSEON
+
+/******************** Bit definition for RCC_ICSCR register *****************/
+#define RCC_ICSCR_HSICAL_Pos (0U)
+#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
+#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM_Pos (8U)
+#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
+#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE_Pos (13U)
+#define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
+#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
+#define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
+#define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
+#define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
+#define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
+#define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
+#define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
+#define RCC_ICSCR_MSICAL_Pos (16U)
+#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
+#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM_Pos (24U)
+#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
+#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
+
+/******************** Bit definition for RCC_CRRCR register *****************/
+#define RCC_CRRCR_HSI48ON_Pos (0U)
+#define RCC_CRRCR_HSI48ON_Msk (0x1UL << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
+#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk /*!< HSI 48MHz clock enable */
+#define RCC_CRRCR_HSI48RDY_Pos (1U)
+#define RCC_CRRCR_HSI48RDY_Msk (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
+#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk /*!< HSI 48MHz clock ready flag */
+#define RCC_CRRCR_HSI48CAL_Pos (8U)
+#define RCC_CRRCR_HSI48CAL_Msk (0xFFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI 48MHz clock Calibration */
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos (15U)
+#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */
+
+/*!< PLL entry clock source*/
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
+
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL_Pos (18U)
+#define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV_Pos (22U)
+#define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
+
+#define RCC_CFGR_PLLDIV2_Pos (22U)
+#define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3_Pos (23U)
+#define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4_Pos (22U)
+#define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCOSEL_Pos (24U)
+#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
+#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
+
+#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
+#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCOSEL_HSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_MSI_Pos (24U)
+#define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
+#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_HSE_Pos (26U)
+#define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCOSEL_PLL_Pos (24U)
+#define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
+#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
+#define RCC_CFGR_MCOSEL_LSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
+#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
+#define RCC_CFGR_MCOSEL_LSE_Pos (24U)
+#define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
+#define RCC_CFGR_MCOSEL_HSI48_Pos (27U)
+#define RCC_CFGR_MCOSEL_HSI48_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */
+#define RCC_CFGR_MCOSEL_HSI48 RCC_CFGR_MCOSEL_HSI48_Msk /*!< HSI48 clock selected as MCO source */
+
+#define RCC_CFGR_MCOPRE_Pos (28U)
+#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
+
+#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
+
+/* Legacy defines */
+#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
+#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
+#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
+#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
+#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
+#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
+#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
+#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
+#ifdef RCC_CFGR_MCOSEL_HSI48
+#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48
+#endif
+
+#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
+#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
+
+/*!<****************** Bit definition for RCC_CIER register ********************/
+#define RCC_CIER_LSIRDYIE_Pos (0U)
+#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIER_LSERDYIE_Pos (1U)
+#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIER_HSIRDYIE_Pos (2U)
+#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIER_HSERDYIE_Pos (3U)
+#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIER_PLLRDYIE_Pos (4U)
+#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIER_MSIRDYIE_Pos (5U)
+#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
+#define RCC_CIER_HSI48RDYIE_Pos (6U)
+#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000040 */
+#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk /*!< HSI48 Ready Interrupt Enable */
+#define RCC_CIER_CSSLSE_Pos (7U)
+#define RCC_CIER_CSSLSE_Msk (0x1UL << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */
+
+/* Reference defines */
+#define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
+
+/*!<****************** Bit definition for RCC_CIFR register ********************/
+#define RCC_CIFR_LSIRDYF_Pos (0U)
+#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIFR_LSERDYF_Pos (1U)
+#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIFR_HSIRDYF_Pos (2U)
+#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIFR_HSERDYF_Pos (3U)
+#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIFR_PLLRDYF_Pos (4U)
+#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIFR_MSIRDYF_Pos (5U)
+#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
+#define RCC_CIFR_HSI48RDYF_Pos (6U)
+#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk /*!< HSI48 Ready Interrupt flag */
+#define RCC_CIFR_CSSLSEF_Pos (7U)
+#define RCC_CIFR_CSSLSEF_Msk (0x1UL << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */
+#define RCC_CIFR_CSSHSEF_Pos (8U)
+#define RCC_CIFR_CSSHSEF_Msk (0x1UL << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */
+#define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */
+
+/* Reference defines */
+#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
+#define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
+
+/*!<****************** Bit definition for RCC_CICR register ********************/
+#define RCC_CICR_LSIRDYC_Pos (0U)
+#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CICR_LSERDYC_Pos (1U)
+#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CICR_HSIRDYC_Pos (2U)
+#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CICR_HSERDYC_Pos (3U)
+#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CICR_PLLRDYC_Pos (4U)
+#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CICR_MSIRDYC_Pos (5U)
+#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
+#define RCC_CICR_HSI48RDYC_Pos (6U)
+#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000040 */
+#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk /*!< HSI48 Ready Interrupt Clear */
+#define RCC_CICR_CSSLSEC_Pos (7U)
+#define RCC_CICR_CSSLSEC_Msk (0x1UL << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */
+#define RCC_CICR_CSSHSEC_Pos (8U)
+#define RCC_CICR_CSSHSEC_Msk (0x1UL << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */
+#define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */
+
+/* Reference defines */
+#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
+#define RCC_CICR_CSSC RCC_CICR_CSSHSEC
+/***************** Bit definition for RCC_IOPRSTR register ******************/
+#define RCC_IOPRSTR_IOPARST_Pos (0U)
+#define RCC_IOPRSTR_IOPARST_Msk (0x1UL << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */
+#define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */
+#define RCC_IOPRSTR_IOPBRST_Pos (1U)
+#define RCC_IOPRSTR_IOPBRST_Msk (0x1UL << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */
+#define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */
+#define RCC_IOPRSTR_IOPCRST_Pos (2U)
+#define RCC_IOPRSTR_IOPCRST_Msk (0x1UL << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */
+#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */
+#define RCC_IOPRSTR_IOPDRST_Pos (3U)
+#define RCC_IOPRSTR_IOPDRST_Msk (0x1UL << RCC_IOPRSTR_IOPDRST_Pos) /*!< 0x00000008 */
+#define RCC_IOPRSTR_IOPDRST RCC_IOPRSTR_IOPDRST_Msk /*!< GPIO port D reset */
+#define RCC_IOPRSTR_IOPHRST_Pos (7U)
+#define RCC_IOPRSTR_IOPHRST_Msk (0x1UL << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */
+#define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */
+
+/* Reference defines */
+#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
+#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
+#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
+#define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_IOPDRST /*!< GPIO port D reset */
+#define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
+
+
+/****************** Bit definition for RCC_AHBRST register ******************/
+#define RCC_AHBRSTR_DMARST_Pos (0U)
+#define RCC_AHBRSTR_DMARST_Msk (0x1UL << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */
+#define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */
+#define RCC_AHBRSTR_MIFRST_Pos (8U)
+#define RCC_AHBRSTR_MIFRST_Msk (0x1UL << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */
+#define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset */
+#define RCC_AHBRSTR_CRCRST_Pos (12U)
+#define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */
+#define RCC_AHBRSTR_TSCRST_Pos (16U)
+#define RCC_AHBRSTR_TSCRST_Msk (0x1UL << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x00010000 */
+#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TSC reset */
+#define RCC_AHBRSTR_RNGRST_Pos (20U)
+#define RCC_AHBRSTR_RNGRST_Msk (0x1UL << RCC_AHBRSTR_RNGRST_Pos) /*!< 0x00100000 */
+#define RCC_AHBRSTR_RNGRST RCC_AHBRSTR_RNGRST_Msk /*!< RNG reset */
+#define RCC_AHBRSTR_CRYPRST_Pos (24U)
+#define RCC_AHBRSTR_CRYPRST_Msk (0x1UL << RCC_AHBRSTR_CRYPRST_Pos) /*!< 0x01000000 */
+#define RCC_AHBRSTR_CRYPRST RCC_AHBRSTR_CRYPRST_Msk /*!< Crypto reset */
+
+/* Reference defines */
+#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
+#define RCC_APB2RSTR_TIM21RST_Pos (2U)
+#define RCC_APB2RSTR_TIM21RST_Msk (0x1UL << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 reset */
+#define RCC_APB2RSTR_TIM22RST_Pos (5U)
+#define RCC_APB2RSTR_TIM22RST_Msk (0x1UL << RCC_APB2RSTR_TIM22RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk /*!< TIM22 reset */
+#define RCC_APB2RSTR_ADCRST_Pos (9U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
+#define RCC_APB2RSTR_DBGRST_Pos (22U)
+#define RCC_APB2RSTR_DBGRST_Msk (0x1UL << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU reset */
+
+/* Reference defines */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 reset */
+#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU reset */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
+#define RCC_APB1RSTR_LCDRST_Pos (9U)
+#define RCC_APB1RSTR_LCDRST_Msk (0x1UL << RCC_APB1RSTR_LCDRST_Pos) /*!< 0x00000200 */
+#define RCC_APB1RSTR_LCDRST RCC_APB1RSTR_LCDRST_Msk /*!< LCD reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_LPUART1RST_Pos (18U)
+#define RCC_APB1RSTR_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
+#define RCC_APB1RSTR_USBRST_Pos (23U)
+#define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */
+#define RCC_APB1RSTR_CRSRST_Pos (27U)
+#define RCC_APB1RSTR_CRSRST_Msk (0x1UL << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
+#define RCC_APB1RSTR_DACRST_Pos (29U)
+#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC reset */
+#define RCC_APB1RSTR_LPTIM1RST_Pos (31U)
+#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 reset */
+
+/***************** Bit definition for RCC_IOPENR register ******************/
+#define RCC_IOPENR_IOPAEN_Pos (0U)
+#define RCC_IOPENR_IOPAEN_Msk (0x1UL << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */
+#define RCC_IOPENR_IOPBEN_Pos (1U)
+#define RCC_IOPENR_IOPBEN_Msk (0x1UL << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */
+#define RCC_IOPENR_IOPCEN_Pos (2U)
+#define RCC_IOPENR_IOPCEN_Msk (0x1UL << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */
+#define RCC_IOPENR_IOPDEN_Pos (3U)
+#define RCC_IOPENR_IOPDEN_Msk (0x1UL << RCC_IOPENR_IOPDEN_Pos) /*!< 0x00000008 */
+#define RCC_IOPENR_IOPDEN RCC_IOPENR_IOPDEN_Msk /*!< GPIO port D clock enable */
+#define RCC_IOPENR_IOPHEN_Pos (7U)
+#define RCC_IOPENR_IOPHEN_Msk (0x1UL << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */
+
+/* Reference defines */
+#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
+#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
+#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
+#define RCC_IOPENR_GPIODEN RCC_IOPENR_IOPDEN /*!< GPIO port D clock enable */
+#define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
+
+/***************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMAEN_Pos (0U)
+#define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_MIFEN_Pos (8U)
+#define RCC_AHBENR_MIFEN_Msk (0x1UL << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */
+#define RCC_AHBENR_CRCEN_Pos (12U)
+#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+#define RCC_AHBENR_TSCEN_Pos (16U)
+#define RCC_AHBENR_TSCEN_Msk (0x1UL << RCC_AHBENR_TSCEN_Pos) /*!< 0x00010000 */
+#define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TSC clock enable */
+#define RCC_AHBENR_RNGEN_Pos (20U)
+#define RCC_AHBENR_RNGEN_Msk (0x1UL << RCC_AHBENR_RNGEN_Pos) /*!< 0x00100000 */
+#define RCC_AHBENR_RNGEN RCC_AHBENR_RNGEN_Msk /*!< RNG clock enable */
+#define RCC_AHBENR_CRYPEN_Pos (24U)
+#define RCC_AHBENR_CRYPEN_Msk (0x1UL << RCC_AHBENR_CRYPEN_Pos) /*!< 0x01000000 */
+#define RCC_AHBENR_CRYPEN RCC_AHBENR_CRYPEN_Msk /*!< Crypto clock enable*/
+
+/* Reference defines */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register ******************/
+#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM21EN_Pos (2U)
+#define RCC_APB2ENR_TIM21EN_Msk (0x1UL << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */
+#define RCC_APB2ENR_TIM22EN_Pos (5U)
+#define RCC_APB2ENR_TIM22EN_Msk (0x1UL << RCC_APB2ENR_TIM22EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk /*!< TIM22 clock enable */
+#define RCC_APB2ENR_FWEN_Pos (7U)
+#define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADCEN_Pos (9U)
+#define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
+#define RCC_APB2ENR_DBGEN_Pos (22U)
+#define RCC_APB2ENR_DBGEN_Msk (0x1UL << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */
+
+/* Reference defines */
+
+#define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_LCDEN_Pos (9U)
+#define RCC_APB1ENR_LCDEN_Msk (0x1UL << RCC_APB1ENR_LCDEN_Pos) /*!< 0x00000200 */
+#define RCC_APB1ENR_LCDEN RCC_APB1ENR_LCDEN_Msk /*!< LCD clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
+#define RCC_APB1ENR_LPUART1EN_Pos (18U)
+#define RCC_APB1ENR_LPUART1EN_Msk (0x1UL << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */
+#define RCC_APB1ENR_USBEN_Pos (23U)
+#define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */
+#define RCC_APB1ENR_CRSEN_Pos (27U)
+#define RCC_APB1ENR_CRSEN_Msk (0x1UL << RCC_APB1ENR_CRSEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
+#define RCC_APB1ENR_DACEN_Pos (29U)
+#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC clock enable */
+#define RCC_APB1ENR_LPTIM1EN_Pos (31U)
+#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */
+
+/****************** Bit definition for RCC_IOPSMENR register ****************/
+#define RCC_IOPSMENR_IOPASMEN_Pos (0U)
+#define RCC_IOPSMENR_IOPASMEN_Msk (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPBSMEN_Pos (1U)
+#define RCC_IOPSMENR_IOPBSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPCSMEN_Pos (2U)
+#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPDSMEN_Pos (3U)
+#define RCC_IOPSMENR_IOPDSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos) /*!< 0x00000008 */
+#define RCC_IOPSMENR_IOPDSMEN RCC_IOPSMENR_IOPDSMEN_Msk /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPHSMEN_Pos (7U)
+#define RCC_IOPSMENR_IOPHSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_IOPDSMEN /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_AHBSMENR register ******************/
+#define RCC_AHBSMENR_DMASMEN_Pos (0U)
+#define RCC_AHBSMENR_DMASMEN_Msk (0x1UL << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */
+#define RCC_AHBSMENR_MIFSMEN_Pos (8U)
+#define RCC_AHBSMENR_MIFSMEN_Msk (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */
+#define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
+#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRCSMEN_Pos (12U)
+#define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */
+#define RCC_AHBSMENR_TSCSMEN_Pos (16U)
+#define RCC_AHBSMENR_TSCSMEN_Msk (0x1UL << RCC_AHBSMENR_TSCSMEN_Pos) /*!< 0x00010000 */
+#define RCC_AHBSMENR_TSCSMEN RCC_AHBSMENR_TSCSMEN_Msk /*!< TSC clock enabled in sleep mode */
+#define RCC_AHBSMENR_RNGSMEN_Pos (20U)
+#define RCC_AHBSMENR_RNGSMEN_Msk (0x1UL << RCC_AHBSMENR_RNGSMEN_Pos) /*!< 0x00100000 */
+#define RCC_AHBSMENR_RNGSMEN RCC_AHBSMENR_RNGSMEN_Msk /*!< RNG clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRYPSMEN_Pos (24U)
+#define RCC_AHBSMENR_CRYPSMEN_Msk (0x1UL << RCC_AHBSMENR_CRYPSMEN_Pos) /*!< 0x01000000 */
+#define RCC_AHBSMENR_CRYPSMEN RCC_AHBSMENR_CRYPSMEN_Msk /*!< Crypto clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB2SMENR register ******************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM21SMEN_Pos (2U)
+#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM22SMEN_Pos (5U)
+#define RCC_APB2SMENR_TIM22SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk /*!< TIM22 clock enabled in sleep mode */
+#define RCC_APB2SMENR_ADCSMEN_Pos (9U)
+#define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
+#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
+#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk /*!< USART1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGSMEN_Pos (22U)
+#define RCC_APB2SMENR_DBGSMEN_Msk (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB1SMENR register ******************/
+#define RCC_APB1SMENR_TIM2SMEN_Pos (0U)
+#define RCC_APB1SMENR_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_TIM6SMEN_Pos (4U)
+#define RCC_APB1SMENR_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM6SMEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1SMENR_TIM6SMEN RCC_APB1SMENR_TIM6SMEN_Msk /*!< Timer 6 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LCDSMEN_Pos (9U)
+#define RCC_APB1SMENR_LCDSMEN_Msk (0x1UL << RCC_APB1SMENR_LCDSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB1SMENR_LCDSMEN RCC_APB1SMENR_LCDSMEN_Msk /*!< LCD clock enabled in sleep mode */
+#define RCC_APB1SMENR_WWDGSMEN_Pos (11U)
+#define RCC_APB1SMENR_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */
+#define RCC_APB1SMENR_SPI2SMEN_Pos (14U)
+#define RCC_APB1SMENR_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR_SPI2SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1SMENR_SPI2SMEN RCC_APB1SMENR_SPI2SMEN_Msk /*!< SPI2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART2SMEN_Pos (17U)
+#define RCC_APB1SMENR_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPUART1SMEN_Pos (18U)
+#define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C1SMEN_Pos (21U)
+#define RCC_APB1SMENR_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C2SMEN_Pos (22U)
+#define RCC_APB1SMENR_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1SMENR_I2C2SMEN RCC_APB1SMENR_I2C2SMEN_Msk /*!< I2C2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USBSMEN_Pos (23U)
+#define RCC_APB1SMENR_USBSMEN_Msk (0x1UL << RCC_APB1SMENR_USBSMEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1SMENR_USBSMEN RCC_APB1SMENR_USBSMEN_Msk /*!< USB clock enabled in sleep mode */
+#define RCC_APB1SMENR_CRSSMEN_Pos (27U)
+#define RCC_APB1SMENR_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR_CRSSMEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1SMENR_CRSSMEN RCC_APB1SMENR_CRSSMEN_Msk /*!< CRS clock enabled in sleep mode */
+#define RCC_APB1SMENR_PWRSMEN_Pos (28U)
+#define RCC_APB1SMENR_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */
+#define RCC_APB1SMENR_DACSMEN_Pos (29U)
+#define RCC_APB1SMENR_DACSMEN_Msk (0x1UL << RCC_APB1SMENR_DACSMEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1SMENR_DACSMEN RCC_APB1SMENR_DACSMEN_Msk /*!< DAC clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U)
+#define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */
+
+/******************* Bit definition for RCC_CCIPR register *******************/
+/*!< USART1 Clock source selection */
+#define RCC_CCIPR_USART1SEL_Pos (0U)
+#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
+#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk /*!< USART1SEL[1:0] bits */
+#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
+
+/*!< USART2 Clock source selection */
+#define RCC_CCIPR_USART2SEL_Pos (2U)
+#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */
+#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+/*!< LPUART1 Clock source selection */
+#define RCC_CCIPR_LPUART1SEL_Pos (10U)
+#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */
+#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */
+#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CCIPR_I2C1SEL_Pos (12U)
+#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */
+#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
+
+
+/*!< LPTIM1 Clock source selection */
+#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
+#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */
+#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+/*!< HSI48 Clock source selection */
+#define RCC_CCIPR_HSI48SEL_Pos (26U)
+#define RCC_CCIPR_HSI48SEL_Msk (0x1UL << RCC_CCIPR_HSI48SEL_Pos) /*!< 0x04000000 */
+#define RCC_CCIPR_HSI48SEL RCC_CCIPR_HSI48SEL_Msk /*!< HSI48 RC clock source selection bit for USB and RNG*/
+
+/* Legacy defines */
+#define RCC_CCIPR_HSI48MSEL RCC_CCIPR_HSI48SEL
+
+/******************* Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSEON_Pos (8U)
+#define RCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */
+#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_CSR_LSERDY_Pos (9U)
+#define RCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */
+#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP_Pos (10U)
+#define RCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */
+#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_CSR_LSEDRV_Pos (11U)
+#define RCC_CSR_LSEDRV_Msk (0x3UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */
+#define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_CSR_LSEDRV_0 (0x1UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */
+#define RCC_CSR_LSEDRV_1 (0x2UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */
+
+#define RCC_CSR_LSECSSON_Pos (13U)
+#define RCC_CSR_LSECSSON_Msk (0x1UL << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */
+#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */
+#define RCC_CSR_LSECSSD_Pos (14U)
+#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
+#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
+
+/*!< RTC congiguration */
+#define RCC_CSR_RTCSEL_Pos (16U)
+#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
+
+#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CSR_RTCSEL_LSE_Pos (16U)
+#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_LSI_Pos (17U)
+#define RCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */
+#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_HSE_Pos (16U)
+#define RCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */
+
+#define RCC_CSR_RTCEN_Pos (18U)
+#define RCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */
+#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_CSR_RTCRST_Pos (19U)
+#define RCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */
+#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */
+
+#define RCC_CSR_RMVF_Pos (23U)
+#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_FWRSTF_Pos (24U)
+#define RCC_CSR_FWRSTF_Msk (0x1UL << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk /*!< Mifare Firewall reset flag */
+#define RCC_CSR_OBLRSTF_Pos (25U)
+#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+/* Reference defines */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN_Pos (2U)
+#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
+#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos (3U)
+#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
+#define RNG_CR_IE RNG_CR_IE_Msk
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY_Pos (0U)
+#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
+#define RNG_SR_DRDY RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos (1U)
+#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
+#define RNG_SR_CECS RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos (2U)
+#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
+#define RNG_SR_SECS RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos (5U)
+#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
+#define RNG_SR_CEIS RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos (6U)
+#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
+#define RNG_SR_SEIS RNG_SR_SEIS_Msk
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER1_SUPPORT
+#define RTC_TAMPER2_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk /*!< */
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk /*!< */
+#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk /*!< */
+#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */
+#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */
+#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk /*!< */
+#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk /*!< */
+#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk /*!< */
+#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk /*!< */
+#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */
+#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk /*!< */
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk /*!< */
+#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk /*!< */
+#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk /*!< */
+#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk /*!< */
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */
+#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk /*!< */
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< */
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */
+#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */
+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */
+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */
+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */
+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */
+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */
+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */
+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */
+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */
+#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */
+#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */
+#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */
+#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */
+#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */
+#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */
+#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */
+#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */
+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */
+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */
+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */
+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */
+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */
+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */
+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */
+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */
+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */
+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CALR register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */
+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define RTC_CAL_CALP RTC_CALR_CALP
+#define RTC_CAL_CALW8 RTC_CALR_CALW8
+#define RTC_CAL_CALW16 RTC_CALR_CALW16
+#define RTC_CAL_CALM RTC_CALR_CALM
+#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
+
+/******************** Bits definition for RTC_TAMPCR register ****************/
+#define RTC_TAMPCR_TAMP2MF_Pos (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2IE_Pos (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1MF_Pos (18U)
+#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
+#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1IE_Pos (16U)
+#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */
+#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */
+#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */
+#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos (7U)
+#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */
+#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP2E_Pos (3U)
+#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */
+#define RTC_TAMPCR_TAMPIE_Pos (2U)
+#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
+#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP1E_Pos (0U)
+#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_OR register ****************/
+#define RTC_OR_OUT_RMP_Pos (1U)
+#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */
+#define RTC_OR_ALARMOUTTYPE_Pos (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */
+
+/* Legacy defines */
+#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk /*!< */
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER (0x00000005U) /*!< */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+#define SPI_I2S_SUPPORT /*!< I2S support */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
+#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR1_BOOT_MODE_Pos (8U)
+#define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
+#define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */
+#define SYSCFG_CFGR1_BOOT_MODE_0 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOT_MODE_1 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_FWDISEN_Pos (0U)
+#define SYSCFG_CFGR2_FWDISEN_Msk (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */
+#define SYSCFG_CFGR2_CAPA_Pos (1U)
+#define SYSCFG_CFGR2_CAPA_Msk (0x7UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x0000000E */
+#define SYSCFG_CFGR2_CAPA SYSCFG_CFGR2_CAPA_Msk /*!< Connection of internal Vlcd rail to external capacitors */
+#define SYSCFG_CFGR2_CAPA_0 (0x1UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR2_CAPA_1 (0x2UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000004 */
+#define SYSCFG_CFGR2_CAPA_2 (0x4UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000008 */
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos (8U)
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR2_I2C_PB6_FMP SYSCFG_CFGR2_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos (9U)
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR2_I2C_PB7_FMP SYSCFG_CFGR2_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos (10U)
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
+#define SYSCFG_CFGR2_I2C_PB8_FMP SYSCFG_CFGR2_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos (11U)
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
+#define SYSCFG_CFGR2_I2C_PB9_FMP SYSCFG_CFGR2_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR2_I2C1_FMP_Pos (12U)
+#define SYSCFG_CFGR2_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR2_I2C1_FMP SYSCFG_CFGR2_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR2_I2C2_FMP_Pos (13U)
+#define SYSCFG_CFGR2_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
+#define SYSCFG_CFGR2_I2C2_FMP SYSCFG_CFGR2_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
+
+
+/***************** Bit definition for SYSCFG_CFGR3 register ****************/
+#define SYSCFG_CFGR3_EN_VREFINT_Pos (0U)
+#define SYSCFG_CFGR3_EN_VREFINT_Msk (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_EN_VREFINT SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
+#define SYSCFG_CFGR3_VREF_OUT_Pos (4U)
+#define SYSCFG_CFGR3_VREF_OUT_Msk (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
+#define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */
+#define SYSCFG_CFGR3_VREF_OUT_0 (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
+#define SYSCFG_CFGR3_VREF_OUT_1 (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U)
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U)
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U)
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
+#define SYSCFG_CFGR3_ENREF_HSI48_Pos (13U)
+#define SYSCFG_CFGR3_ENREF_HSI48_Msk (0x1UL << SYSCFG_CFGR3_ENREF_HSI48_Pos) /*!< 0x00002000 */
+#define SYSCFG_CFGR3_ENREF_HSI48 SYSCFG_CFGR3_ENREF_HSI48_Msk /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
+#define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U)
+#define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
+#define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
+#define SYSCFG_CFGR3_REF_LOCK_Pos (31U)
+#define SYSCFG_CFGR3_REF_LOCK_Msk (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
+#define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */
+
+/* Legacy defines */
+
+#define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
+#define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
+#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
+#define SYSCFG_CFGR3_ENREF_RC48MHz SYSCFG_CFGR3_ENREF_HSI48
+#define SYSCFG_CFGR3_REF_RC48MHz_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_REF_HSI48_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+
+/******************************************************************************/
+/* */
+/* Timers (TIM)*/
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
+#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
+ || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#else
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#endif
+
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFUL << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFUL << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM2_OR_ETR_RMP_Pos (0U)
+#define TIM2_OR_ETR_RMP_Msk (0x7UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000007 */
+#define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
+#define TIM2_OR_ETR_RMP_0 (0x1UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM2_OR_ETR_RMP_1 (0x2UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM2_OR_ETR_RMP_2 (0x4UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000004 */
+#define TIM2_OR_TI4_RMP_Pos (3U)
+#define TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000018 */
+#define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
+#define TIM2_OR_TI4_RMP_0 (0x1UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */
+#define TIM2_OR_TI4_RMP_1 (0x2UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000010 */
+
+#define TIM21_OR_ETR_RMP_Pos (0U)
+#define TIM21_OR_ETR_RMP_Msk (0x3UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
+#define TIM21_OR_ETR_RMP_0 (0x1UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM21_OR_ETR_RMP_1 (0x2UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM21_OR_TI1_RMP_Pos (2U)
+#define TIM21_OR_TI1_RMP_Msk (0x7UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x0000001C */
+#define TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
+#define TIM21_OR_TI1_RMP_0 (0x1UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM21_OR_TI1_RMP_1 (0x2UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+#define TIM21_OR_TI1_RMP_2 (0x4UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000010 */
+#define TIM21_OR_TI2_RMP_Pos (5U)
+#define TIM21_OR_TI2_RMP_Msk (0x1UL << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */
+#define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */
+
+#define TIM22_OR_ETR_RMP_Pos (0U)
+#define TIM22_OR_ETR_RMP_Msk (0x3UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM22_OR_ETR_RMP TIM22_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
+#define TIM22_OR_ETR_RMP_0 (0x1UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM22_OR_ETR_RMP_1 (0x2UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM22_OR_TI1_RMP_Pos (2U)
+#define TIM22_OR_TI1_RMP_Msk (0x3UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x0000000C */
+#define TIM22_OR_TI1_RMP TIM22_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
+#define TIM22_OR_TI1_RMP_0 (0x1UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM22_OR_TI1_RMP_1 (0x2UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+
+
+/******************************************************************************/
+/* */
+/* Touch Sensing Controller (TSC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TSC_CR register *********************/
+#define TSC_CR_TSCE_Pos (0U)
+#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
+#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
+#define TSC_CR_START_Pos (1U)
+#define TSC_CR_START_Msk (0x1UL << TSC_CR_START_Pos) /*!< 0x00000002 */
+#define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
+#define TSC_CR_AM_Pos (2U)
+#define TSC_CR_AM_Msk (0x1UL << TSC_CR_AM_Pos) /*!< 0x00000004 */
+#define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL_Pos (3U)
+#define TSC_CR_SYNCPOL_Msk (0x1UL << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
+#define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF_Pos (4U)
+#define TSC_CR_IODEF_Msk (0x1UL << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
+#define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
+
+#define TSC_CR_MCV_Pos (5U)
+#define TSC_CR_MCV_Msk (0x7UL << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
+#define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0 (0x1UL << TSC_CR_MCV_Pos) /*!< 0x00000020 */
+#define TSC_CR_MCV_1 (0x2UL << TSC_CR_MCV_Pos) /*!< 0x00000040 */
+#define TSC_CR_MCV_2 (0x4UL << TSC_CR_MCV_Pos) /*!< 0x00000080 */
+
+#define TSC_CR_PGPSC_Pos (12U)
+#define TSC_CR_PGPSC_Msk (0x7UL << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
+#define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0 (0x1UL << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
+#define TSC_CR_PGPSC_1 (0x2UL << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
+#define TSC_CR_PGPSC_2 (0x4UL << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
+
+#define TSC_CR_SSPSC_Pos (15U)
+#define TSC_CR_SSPSC_Msk (0x1UL << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
+#define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE_Pos (16U)
+#define TSC_CR_SSE_Msk (0x1UL << TSC_CR_SSE_Pos) /*!< 0x00010000 */
+#define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD_Pos (17U)
+#define TSC_CR_SSD_Msk (0x7FUL << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
+#define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0 (0x01UL << TSC_CR_SSD_Pos) /*!< 0x00020000 */
+#define TSC_CR_SSD_1 (0x02UL << TSC_CR_SSD_Pos) /*!< 0x00040000 */
+#define TSC_CR_SSD_2 (0x04UL << TSC_CR_SSD_Pos) /*!< 0x00080000 */
+#define TSC_CR_SSD_3 (0x08UL << TSC_CR_SSD_Pos) /*!< 0x00100000 */
+#define TSC_CR_SSD_4 (0x10UL << TSC_CR_SSD_Pos) /*!< 0x00200000 */
+#define TSC_CR_SSD_5 (0x20UL << TSC_CR_SSD_Pos) /*!< 0x00400000 */
+#define TSC_CR_SSD_6 (0x40UL << TSC_CR_SSD_Pos) /*!< 0x00800000 */
+
+#define TSC_CR_CTPL_Pos (24U)
+#define TSC_CR_CTPL_Msk (0xFUL << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
+#define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0 (0x1UL << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
+#define TSC_CR_CTPL_1 (0x2UL << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
+#define TSC_CR_CTPL_2 (0x4UL << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
+#define TSC_CR_CTPL_3 (0x8UL << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
+
+#define TSC_CR_CTPH_Pos (28U)
+#define TSC_CR_CTPH_Msk (0xFUL << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
+#define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0 (0x1UL << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
+#define TSC_CR_CTPH_1 (0x2UL << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
+#define TSC_CR_CTPH_2 (0x4UL << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
+#define TSC_CR_CTPH_3 (0x8UL << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for TSC_IER register ********************/
+#define TSC_IER_EOAIE_Pos (0U)
+#define TSC_IER_EOAIE_Msk (0x1UL << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
+#define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE_Pos (1U)
+#define TSC_IER_MCEIE_Msk (0x1UL << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
+#define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
+
+/******************* Bit definition for TSC_ICR register ********************/
+#define TSC_ICR_EOAIC_Pos (0U)
+#define TSC_ICR_EOAIC_Msk (0x1UL << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
+#define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC_Pos (1U)
+#define TSC_ICR_MCEIC_Msk (0x1UL << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
+#define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
+
+/******************* Bit definition for TSC_ISR register ********************/
+#define TSC_ISR_EOAF_Pos (0U)
+#define TSC_ISR_EOAF_Msk (0x1UL << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
+#define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
+#define TSC_ISR_MCEF_Pos (1U)
+#define TSC_ISR_MCEF_Msk (0x1UL << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
+#define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
+
+/******************* Bit definition for TSC_IOHCR register ******************/
+#define TSC_IOHCR_G1_IO1_Pos (0U)
+#define TSC_IOHCR_G1_IO1_Msk (0x1UL << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2_Pos (1U)
+#define TSC_IOHCR_G1_IO2_Msk (0x1UL << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3_Pos (2U)
+#define TSC_IOHCR_G1_IO3_Msk (0x1UL << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4_Pos (3U)
+#define TSC_IOHCR_G1_IO4_Msk (0x1UL << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1_Pos (4U)
+#define TSC_IOHCR_G2_IO1_Msk (0x1UL << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2_Pos (5U)
+#define TSC_IOHCR_G2_IO2_Msk (0x1UL << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3_Pos (6U)
+#define TSC_IOHCR_G2_IO3_Msk (0x1UL << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4_Pos (7U)
+#define TSC_IOHCR_G2_IO4_Msk (0x1UL << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1_Pos (8U)
+#define TSC_IOHCR_G3_IO1_Msk (0x1UL << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2_Pos (9U)
+#define TSC_IOHCR_G3_IO2_Msk (0x1UL << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3_Pos (10U)
+#define TSC_IOHCR_G3_IO3_Msk (0x1UL << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4_Pos (11U)
+#define TSC_IOHCR_G3_IO4_Msk (0x1UL << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1_Pos (12U)
+#define TSC_IOHCR_G4_IO1_Msk (0x1UL << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2_Pos (13U)
+#define TSC_IOHCR_G4_IO2_Msk (0x1UL << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3_Pos (14U)
+#define TSC_IOHCR_G4_IO3_Msk (0x1UL << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4_Pos (15U)
+#define TSC_IOHCR_G4_IO4_Msk (0x1UL << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1_Pos (16U)
+#define TSC_IOHCR_G5_IO1_Msk (0x1UL << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2_Pos (17U)
+#define TSC_IOHCR_G5_IO2_Msk (0x1UL << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3_Pos (18U)
+#define TSC_IOHCR_G5_IO3_Msk (0x1UL << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4_Pos (19U)
+#define TSC_IOHCR_G5_IO4_Msk (0x1UL << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1_Pos (20U)
+#define TSC_IOHCR_G6_IO1_Msk (0x1UL << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2_Pos (21U)
+#define TSC_IOHCR_G6_IO2_Msk (0x1UL << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3_Pos (22U)
+#define TSC_IOHCR_G6_IO3_Msk (0x1UL << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4_Pos (23U)
+#define TSC_IOHCR_G6_IO4_Msk (0x1UL << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1_Pos (24U)
+#define TSC_IOHCR_G7_IO1_Msk (0x1UL << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2_Pos (25U)
+#define TSC_IOHCR_G7_IO2_Msk (0x1UL << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3_Pos (26U)
+#define TSC_IOHCR_G7_IO3_Msk (0x1UL << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4_Pos (27U)
+#define TSC_IOHCR_G7_IO4_Msk (0x1UL << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1_Pos (28U)
+#define TSC_IOHCR_G8_IO1_Msk (0x1UL << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2_Pos (29U)
+#define TSC_IOHCR_G8_IO2_Msk (0x1UL << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3_Pos (30U)
+#define TSC_IOHCR_G8_IO3_Msk (0x1UL << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4_Pos (31U)
+#define TSC_IOHCR_G8_IO4_Msk (0x1UL << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+
+/******************* Bit definition for TSC_IOASCR register *****************/
+#define TSC_IOASCR_G1_IO1_Pos (0U)
+#define TSC_IOASCR_G1_IO1_Msk (0x1UL << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2_Pos (1U)
+#define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3_Pos (2U)
+#define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4_Pos (3U)
+#define TSC_IOASCR_G1_IO4_Msk (0x1UL << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1_Pos (4U)
+#define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2_Pos (5U)
+#define TSC_IOASCR_G2_IO2_Msk (0x1UL << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3_Pos (6U)
+#define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4_Pos (7U)
+#define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1_Pos (8U)
+#define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2_Pos (9U)
+#define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3_Pos (10U)
+#define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4_Pos (11U)
+#define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1_Pos (12U)
+#define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2_Pos (13U)
+#define TSC_IOASCR_G4_IO2_Msk (0x1UL << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3_Pos (14U)
+#define TSC_IOASCR_G4_IO3_Msk (0x1UL << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4_Pos (15U)
+#define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1_Pos (16U)
+#define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2_Pos (17U)
+#define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3_Pos (18U)
+#define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4_Pos (19U)
+#define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1_Pos (20U)
+#define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2_Pos (21U)
+#define TSC_IOASCR_G6_IO2_Msk (0x1UL << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3_Pos (22U)
+#define TSC_IOASCR_G6_IO3_Msk (0x1UL << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4_Pos (23U)
+#define TSC_IOASCR_G6_IO4_Msk (0x1UL << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1_Pos (24U)
+#define TSC_IOASCR_G7_IO1_Msk (0x1UL << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2_Pos (25U)
+#define TSC_IOASCR_G7_IO2_Msk (0x1UL << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3_Pos (26U)
+#define TSC_IOASCR_G7_IO3_Msk (0x1UL << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4_Pos (27U)
+#define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1_Pos (28U)
+#define TSC_IOASCR_G8_IO1_Msk (0x1UL << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2_Pos (29U)
+#define TSC_IOASCR_G8_IO2_Msk (0x1UL << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3_Pos (30U)
+#define TSC_IOASCR_G8_IO3_Msk (0x1UL << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4_Pos (31U)
+#define TSC_IOASCR_G8_IO4_Msk (0x1UL << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */
+
+/******************* Bit definition for TSC_IOSCR register ******************/
+#define TSC_IOSCR_G1_IO1_Pos (0U)
+#define TSC_IOSCR_G1_IO1_Msk (0x1UL << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2_Pos (1U)
+#define TSC_IOSCR_G1_IO2_Msk (0x1UL << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3_Pos (2U)
+#define TSC_IOSCR_G1_IO3_Msk (0x1UL << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4_Pos (3U)
+#define TSC_IOSCR_G1_IO4_Msk (0x1UL << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1_Pos (4U)
+#define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2_Pos (5U)
+#define TSC_IOSCR_G2_IO2_Msk (0x1UL << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3_Pos (6U)
+#define TSC_IOSCR_G2_IO3_Msk (0x1UL << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4_Pos (7U)
+#define TSC_IOSCR_G2_IO4_Msk (0x1UL << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1_Pos (8U)
+#define TSC_IOSCR_G3_IO1_Msk (0x1UL << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2_Pos (9U)
+#define TSC_IOSCR_G3_IO2_Msk (0x1UL << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3_Pos (10U)
+#define TSC_IOSCR_G3_IO3_Msk (0x1UL << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4_Pos (11U)
+#define TSC_IOSCR_G3_IO4_Msk (0x1UL << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1_Pos (12U)
+#define TSC_IOSCR_G4_IO1_Msk (0x1UL << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2_Pos (13U)
+#define TSC_IOSCR_G4_IO2_Msk (0x1UL << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3_Pos (14U)
+#define TSC_IOSCR_G4_IO3_Msk (0x1UL << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4_Pos (15U)
+#define TSC_IOSCR_G4_IO4_Msk (0x1UL << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1_Pos (16U)
+#define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2_Pos (17U)
+#define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3_Pos (18U)
+#define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4_Pos (19U)
+#define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1_Pos (20U)
+#define TSC_IOSCR_G6_IO1_Msk (0x1UL << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2_Pos (21U)
+#define TSC_IOSCR_G6_IO2_Msk (0x1UL << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3_Pos (22U)
+#define TSC_IOSCR_G6_IO3_Msk (0x1UL << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4_Pos (23U)
+#define TSC_IOSCR_G6_IO4_Msk (0x1UL << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1_Pos (24U)
+#define TSC_IOSCR_G7_IO1_Msk (0x1UL << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2_Pos (25U)
+#define TSC_IOSCR_G7_IO2_Msk (0x1UL << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3_Pos (26U)
+#define TSC_IOSCR_G7_IO3_Msk (0x1UL << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4_Pos (27U)
+#define TSC_IOSCR_G7_IO4_Msk (0x1UL << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1_Pos (28U)
+#define TSC_IOSCR_G8_IO1_Msk (0x1UL << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2_Pos (29U)
+#define TSC_IOSCR_G8_IO2_Msk (0x1UL << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3_Pos (30U)
+#define TSC_IOSCR_G8_IO3_Msk (0x1UL << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4_Pos (31U)
+#define TSC_IOSCR_G8_IO4_Msk (0x1UL << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */
+
+/******************* Bit definition for TSC_IOCCR register ******************/
+#define TSC_IOCCR_G1_IO1_Pos (0U)
+#define TSC_IOCCR_G1_IO1_Msk (0x1UL << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2_Pos (1U)
+#define TSC_IOCCR_G1_IO2_Msk (0x1UL << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3_Pos (2U)
+#define TSC_IOCCR_G1_IO3_Msk (0x1UL << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4_Pos (3U)
+#define TSC_IOCCR_G1_IO4_Msk (0x1UL << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1_Pos (4U)
+#define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2_Pos (5U)
+#define TSC_IOCCR_G2_IO2_Msk (0x1UL << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3_Pos (6U)
+#define TSC_IOCCR_G2_IO3_Msk (0x1UL << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4_Pos (7U)
+#define TSC_IOCCR_G2_IO4_Msk (0x1UL << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1_Pos (8U)
+#define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2_Pos (9U)
+#define TSC_IOCCR_G3_IO2_Msk (0x1UL << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3_Pos (10U)
+#define TSC_IOCCR_G3_IO3_Msk (0x1UL << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4_Pos (11U)
+#define TSC_IOCCR_G3_IO4_Msk (0x1UL << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1_Pos (12U)
+#define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2_Pos (13U)
+#define TSC_IOCCR_G4_IO2_Msk (0x1UL << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3_Pos (14U)
+#define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4_Pos (15U)
+#define TSC_IOCCR_G4_IO4_Msk (0x1UL << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1_Pos (16U)
+#define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2_Pos (17U)
+#define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3_Pos (18U)
+#define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4_Pos (19U)
+#define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1_Pos (20U)
+#define TSC_IOCCR_G6_IO1_Msk (0x1UL << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2_Pos (21U)
+#define TSC_IOCCR_G6_IO2_Msk (0x1UL << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3_Pos (22U)
+#define TSC_IOCCR_G6_IO3_Msk (0x1UL << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4_Pos (23U)
+#define TSC_IOCCR_G6_IO4_Msk (0x1UL << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1_Pos (24U)
+#define TSC_IOCCR_G7_IO1_Msk (0x1UL << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2_Pos (25U)
+#define TSC_IOCCR_G7_IO2_Msk (0x1UL << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3_Pos (26U)
+#define TSC_IOCCR_G7_IO3_Msk (0x1UL << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4_Pos (27U)
+#define TSC_IOCCR_G7_IO4_Msk (0x1UL << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1_Pos (28U)
+#define TSC_IOCCR_G8_IO1_Msk (0x1UL << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2_Pos (29U)
+#define TSC_IOCCR_G8_IO2_Msk (0x1UL << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3_Pos (30U)
+#define TSC_IOCCR_G8_IO3_Msk (0x1UL << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4_Pos (31U)
+#define TSC_IOCCR_G8_IO4_Msk (0x1UL << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */
+
+/******************* Bit definition for TSC_IOGCSR register *****************/
+#define TSC_IOGCSR_G1E_Pos (0U)
+#define TSC_IOGCSR_G1E_Msk (0x1UL << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
+#define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E_Pos (1U)
+#define TSC_IOGCSR_G2E_Msk (0x1UL << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
+#define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E_Pos (2U)
+#define TSC_IOGCSR_G3E_Msk (0x1UL << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
+#define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E_Pos (3U)
+#define TSC_IOGCSR_G4E_Msk (0x1UL << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
+#define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E_Pos (4U)
+#define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
+#define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E_Pos (5U)
+#define TSC_IOGCSR_G6E_Msk (0x1UL << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
+#define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E_Pos (6U)
+#define TSC_IOGCSR_G7E_Msk (0x1UL << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
+#define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E_Pos (7U)
+#define TSC_IOGCSR_G8E_Msk (0x1UL << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */
+#define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S_Pos (16U)
+#define TSC_IOGCSR_G1S_Msk (0x1UL << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
+#define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S_Pos (17U)
+#define TSC_IOGCSR_G2S_Msk (0x1UL << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
+#define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S_Pos (18U)
+#define TSC_IOGCSR_G3S_Msk (0x1UL << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
+#define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S_Pos (19U)
+#define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
+#define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S_Pos (20U)
+#define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
+#define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S_Pos (21U)
+#define TSC_IOGCSR_G6S_Msk (0x1UL << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
+#define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S_Pos (22U)
+#define TSC_IOGCSR_G7S_Msk (0x1UL << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
+#define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S_Pos (23U)
+#define TSC_IOGCSR_G8S_Msk (0x1UL << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */
+#define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */
+
+/******************* Bit definition for TSC_IOGXCR register *****************/
+#define TSC_IOGXCR_CNT_Pos (0U)
+#define TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
+#define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE_Pos (0U)
+#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+#define USART_CR1_UESM_Pos (1U)
+#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
+#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_M0_Pos (12U)
+#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
+#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos (13U)
+#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos (14U)
+#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos (16U)
+#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
+#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
+#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
+#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
+#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos (21U)
+#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
+#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
+#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
+#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
+#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos (26U)
+#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos (27U)
+#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos (28U)
+#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
+#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7_Pos (4U)
+#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos (15U)
+#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos (16U)
+#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos (17U)
+#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos (18U)
+#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos (19U)
+#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos (20U)
+#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos (21U)
+#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos (23U)
+#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos (24U)
+#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos (12U)
+#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos (13U)
+#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos (14U)
+#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos (15U)
+#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos (17U)
+#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos (20U)
+#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
+#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
+#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos (22U)
+#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
+#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
+#define USART_CR3_UCESM_Pos (23U)
+#define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
+#define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION_Pos (0U)
+#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos (4U)
+#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO_Pos (0U)
+#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos (24U)
+#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ_Pos (0U)
+#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
+#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos (1U)
+#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
+#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos (2U)
+#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
+#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos (3U)
+#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
+#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos (4U)
+#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
+#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE_Pos (0U)
+#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
+#define USART_ISR_FE_Pos (1U)
+#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
+#define USART_ISR_NE_Pos (2U)
+#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos (3U)
+#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos (4U)
+#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos (5U)
+#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos (6U)
+#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos (7U)
+#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
+#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos (8U)
+#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos (9U)
+#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos (10U)
+#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
+#define USART_ISR_RTOF_Pos (11U)
+#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos (12U)
+#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos (14U)
+#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos (15U)
+#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos (16U)
+#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
+#define USART_ISR_CMF_Pos (17U)
+#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos (18U)
+#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos (19U)
+#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos (20U)
+#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
+#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos (21U)
+#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos (22U)
+#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
+#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF_Pos (0U)
+#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos (1U)
+#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos (2U)
+#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */
+#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos (3U)
+#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos (4U)
+#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos (6U)
+#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF_Pos (8U)
+#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos (9U)
+#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos (11U)
+#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos (12U)
+#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos (17U)
+#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos (20U)
+#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
+#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
+
+/* Compatibility defines with other series */
+#define USART_ICR_NECF USART_ICR_NCF
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR_Pos (0U)
+#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR_Pos (0U)
+#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* USB Device General registers */
+/* */
+/******************************************************************************/
+#define USB_BASE (0x40005C00U) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR_Pos (13U)
+#define USB_PMAADDR_Msk (0x20003UL << USB_PMAADDR_Pos) /*!< 0x40006000 */
+#define USB_PMAADDR USB_PMAADDR_Msk /*!< USB_IP Packet Memory Area base address */
+
+#define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
+#define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
+#define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
+#define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
+#define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
+#define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
+#define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
+
+/**************************** ISTR interrupt events *************************/
+#define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
+#define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
+#define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
+#define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
+#define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
+#define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
+#define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
+#define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
+#define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
+
+#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
+#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
+#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
+#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
+#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
+#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
+#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
+#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
+#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
+/************************* CNTR control register bits definitions ***********/
+#define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
+#define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
+#define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
+#define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
+#define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
+#define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
+#define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
+#define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
+#define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
+#define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
+#define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
+#define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
+#define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
+#define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
+/************************* BCDR control register bits definitions ***********/
+#define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
+#define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
+#define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
+#define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
+#define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
+#define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
+#define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
+#define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
+#define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
+/*************************** LPM register bits definitions ******************/
+#define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
+#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
+#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
+/******************** FNR Frame Number Register bit definitions ************/
+#define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
+#define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
+#define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
+#define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
+#define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
+/******************** DADDR Device ADDRess bit definitions ****************/
+#define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */
+#define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */
+/****************************** Endpoint register *************************/
+#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
+#define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
+#define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
+#define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
+#define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
+#define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
+#define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
+#define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
+/* bit positions */
+#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
+#define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
+#define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
+#define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
+#define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+ /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
+#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+/******************************* AES Instances ********************************/
+#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
+
+/******************************* COMP Instances *******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+ ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances *********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOH))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2))
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
+
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SMBUS Instances *****************************/
+#define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/************* LPTIM instances supporting the encoder mode feature ************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM6))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ ((((INSTANCE) == TIM2) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM21) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM22) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/******************* TIM Instances : output(s) OCXEC register *****************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** USART Instances : Auto Baud Rate detection ****************/
+
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/******************************* USB Instances *******************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** LCD Instances ********************************/
+#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32L0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32L0 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+
+#define LPUART1_IRQn AES_RNG_LPUART1_IRQn
+#define AES_LPUART1_IRQn AES_RNG_LPUART1_IRQn
+#define RNG_LPUART1_IRQn AES_RNG_LPUART1_IRQn
+#define TIM6_IRQn TIM6_DAC_IRQn
+#define RCC_IRQn RCC_CRS_IRQn
+#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
+#define ADC1_IRQn ADC1_COMP_IRQn
+
+/* Aliases for __IRQHandler */
+#define LPUART1_IRQHandler AES_RNG_LPUART1_IRQHandler
+#define RNG_LPUART1_IRQHandler AES_RNG_LPUART1_IRQHandler
+#define AES_LPUART1_IRQHandler AES_RNG_LPUART1_IRQHandler
+#define TIM6_IRQHandler TIM6_DAC_IRQHandler
+#define RCC_IRQHandler RCC_CRS_IRQHandler
+#define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
+#define ADC1_IRQHandler ADC1_COMP_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L063xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/CMSIS/device/stm32l071xx.h b/CMSIS/device/stm32l071xx.h
new file mode 100644
index 0000000..b0ece7c
--- /dev/null
+++ b/CMSIS/device/stm32l071xx.h
@@ -0,0 +1,6497 @@
+/**
+ ******************************************************************************
+ * @file stm32l071xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for stm32l071xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright(c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l071xx
+ * @{
+ */
+
+#ifndef __STM32L071xx_H
+#define __STM32L071xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 1U /*!< STM32L0xx provides an MPU */
+#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
+#define __NVIC_PRIO_BITS 2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief stm32l071xx Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+/*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
+
+/****** STM32L-0 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */
+ RCC_IRQn = 4, /*!< RCC Interrupt */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
+ ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
+ LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
+ USART4_5_IRQn = 14, /*!< USART4 and USART5 Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 Interrupt */
+ TIM3_IRQn = 16, /*!< TIM3 Interrupt */
+ TIM6_IRQn = 17, /*!< TIM6 Interrupt */
+ TIM7_IRQn = 18, /*!< TIM7 Interrupt */
+ TIM21_IRQn = 20, /*!< TIM21 Interrupt */
+ I2C3_IRQn = 21, /*!< I2C3 Interrupt */
+ TIM22_IRQn = 22, /*!< TIM22 Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */
+ I2C2_IRQn = 24, /*!< I2C2 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ SPI2_IRQn = 26, /*!< SPI2 Interrupt */
+ USART1_IRQn = 27, /*!< USART1 Interrupt */
+ USART2_IRQn = 28, /*!< USART2 Interrupt */
+ LPUART1_IRQn = 29, /*!< LPUART1 Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0plus.h"
+#include "system_stm32l0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+ uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Comparator
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
+} COMP_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+
+/**
+* @brief CRC calculation unit
+*/
+
+typedef struct
+{
+__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+uint8_t RESERVED0; /*!< Reserved, 0x05 */
+uint16_t RESERVED1; /*!< Reserved, 0x06 */
+__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+uint32_t RESERVED2; /*!< Reserved, 0x0C */
+__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
+} DMA_Request_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
+ __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
+ __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
+ __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
+ __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
+ __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
+ __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
+ __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
+ __IO uint32_t RESERVED1[23]; /*!< Reserved1, Address offset: 0x24 */
+ __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
+ __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
+ __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
+ __IO uint32_t WRP23; /*!< write protection Bytes 2 and 3 Address offset: 0x0C */
+ __IO uint32_t WRP45; /*!< write protection Bytes 4 and 5 Address offset: 0x10 */
+} OB_TypeDef;
+
+
+/**
+ * @brief General Purpose IO
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief LPTIMIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+} LPTIM_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+ * @brief Independent WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief MIFARE Firewall
+ */
+typedef struct
+{
+ __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
+ __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
+ __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
+ __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
+ __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
+ __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
+ __IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x18 */
+ __IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */
+ __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
+
+} FIREWALL_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
+ __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
+ __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
+ __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
+ __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
+ __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
+ __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
+ __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
+ __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
+ __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
+ __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */
+
+#define DATA_EEPROM_BASE (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
+#define DATA_EEPROM_BANK2_BASE (0x08080C00UL) /*!< DATA EEPROM BANK2 base address in the alias region */
+#define DATA_EEPROM_BANK1_END (0x08080BFFUL) /*!< Program end DATA EEPROM BANK1 address */
+#define DATA_EEPROM_BANK2_END (0x080817FFUL) /*!< Program end DATA EEPROM BANK2 address */
+#define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */
+#define SRAM_SIZE_MAX (0x00005000UL) /*!< maximum SRAM size (up to 20KBytes) */
+
+#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000UL)
+
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL)
+#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL)
+#define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL)
+#define TIM7_BASE (APBPERIPH_BASE + 0x00001400UL)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
+#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
+#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800UL)
+#define USART4_BASE (APBPERIPH_BASE + 0x00004C00UL)
+#define USART5_BASE (APBPERIPH_BASE + 0x00005000UL)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
+#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
+#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL)
+#define I2C3_BASE (APBPERIPH_BASE + 0x00007800UL)
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
+#define COMP1_BASE (APBPERIPH_BASE + 0x00010018UL)
+#define COMP2_BASE (APBPERIPH_BASE + 0x0001001CUL)
+#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL)
+#define TIM21_BASE (APBPERIPH_BASE + 0x00010800UL)
+#define TIM22_BASE (APBPERIPH_BASE + 0x00011400UL)
+#define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00UL)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708UL)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
+#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
+#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL)
+
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
+#define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */
+#define FLASHSIZE_BASE (0x1FF8007CUL) /*!< FLASH Size register base address */
+#define UID_BASE (0x1FF80050UL) /*!< Unique device ID register base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
+
+#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL)
+#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL)
+#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL)
+#define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00UL)
+#define GPIOE_BASE (IOPPERIPH_BASE + 0x00001000UL)
+#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00UL)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define USART4 ((USART_TypeDef *) USART4_BASE)
+#define USART5 ((USART_TypeDef *) USART5_BASE)
+
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
+#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
+#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
+/* Legacy defines */
+#define ADC ADC1_COMMON
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_EOCAL_Pos (11U)
+#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
+#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
+#define ADC_ISR_AWD_Pos (7U)
+#define ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
+#define ADC_ISR_EOSEQ_Pos (3U)
+#define ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_EOCALIE_Pos (11U)
+#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
+#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
+#define ADC_IER_AWDIE_Pos (7U)
+#define ADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE_Pos (3U)
+#define ADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH_Pos (26U)
+#define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
+#define ADC_CFGR1_AWDEN_Pos (23U)
+#define ADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL_Pos (22U)
+#define ADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN_Pos (16U)
+#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF_Pos (15U)
+#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
+#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT_Pos (14U)
+#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
+#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT_Pos (13U)
+#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD_Pos (12U)
+#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN_Pos (10U)
+#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
+#define ADC_CFGR1_EXTSEL_Pos (6U)
+#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
+#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
+#define ADC_CFGR1_ALIGN_Pos (5U)
+#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
+#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
+#define ADC_CFGR1_RES_Pos (3U)
+#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
+#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
+#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
+#define ADC_CFGR1_SCANDIR_Pos (2U)
+#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG_Pos (1U)
+#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
+#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN_Pos (0U)
+#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
+#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_TOVS_Pos (9U)
+#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
+#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+#define ADC_CFGR2_OVSR_Pos (2U)
+#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
+#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+#define ADC_CFGR2_OVSE_Pos (0U)
+#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
+#define ADC_CFGR2_CKMODE_Pos (30U)
+#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
+#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
+#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
+#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
+
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP_Pos (0U)
+#define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
+#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
+#define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
+#define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define ADC_SMPR_SMPR ADC_SMPR_SMP
+#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
+#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
+#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT_Pos (16U)
+#define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
+#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
+#define ADC_TR_LT_Pos (0U)
+#define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL_Pos (0U)
+#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
+#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
+#define ADC_CHSELR_CHSEL18_Pos (18U)
+#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17_Pos (17U)
+#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
+#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL15_Pos (15U)
+#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
+#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14_Pos (14U)
+#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
+#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13_Pos (13U)
+#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
+#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12_Pos (12U)
+#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
+#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11_Pos (11U)
+#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
+#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10_Pos (10U)
+#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
+#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9_Pos (9U)
+#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
+#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8_Pos (8U)
+#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
+#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7_Pos (7U)
+#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
+#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6_Pos (6U)
+#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
+#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5_Pos (5U)
+#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
+#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4_Pos (4U)
+#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
+#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3_Pos (3U)
+#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
+#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2_Pos (2U)
+#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
+#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1_Pos (1U)
+#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
+#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0_Pos (0U)
+#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
+#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_CALFACT_Pos (0U)
+#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_LFMEN_Pos (25U)
+#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
+#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
+#define ADC_CCR_TSEN_Pos (23U)
+#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+/************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN_Pos (0U)
+#define COMP_CSR_COMP1EN_Msk (0x1UL << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
+#define COMP_CSR_COMP1INNSEL_Pos (4U)
+#define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
+#define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP1WM_Pos (8U)
+#define COMP_CSR_COMP1WM_Msk (0x1UL << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */
+#define COMP_CSR_COMP1LPTIM1IN1_Pos (12U)
+#define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP1POLARITY_Pos (15U)
+#define COMP_CSR_COMP1POLARITY_Msk (0x1UL << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1VALUE_Pos (30U)
+#define COMP_CSR_COMP1VALUE_Msk (0x1UL << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK_Pos (31U)
+#define COMP_CSR_COMP1LOCK_Msk (0x1UL << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN_Pos (0U)
+#define COMP_CSR_COMP2EN_Msk (0x1UL << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
+#define COMP_CSR_COMP2SPEED_Pos (3U)
+#define COMP_CSR_COMP2SPEED_Msk (0x1UL << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */
+#define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */
+#define COMP_CSR_COMP2INNSEL_Pos (4U)
+#define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */
+#define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
+#define COMP_CSR_COMP2INPSEL_Pos (8U)
+#define COMP_CSR_COMP2INPSEL_Msk (0x7UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */
+#define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2INPSEL_0 (0x1UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP2INPSEL_1 (0x2UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */
+#define COMP_CSR_COMP2INPSEL_2 (0x4UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */
+#define COMP_CSR_COMP2LPTIM1IN2_Pos (12U)
+#define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */
+#define COMP_CSR_COMP2LPTIM1IN1_Pos (13U)
+#define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */
+#define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP2POLARITY_Pos (15U)
+#define COMP_CSR_COMP2POLARITY_Msk (0x1UL << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2VALUE_Pos (30U)
+#define COMP_CSR_COMP2VALUE_Msk (0x1UL << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK_Pos (31U)
+#define COMP_CSR_COMP2LOCK_Msk (0x1UL << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
+
+/********************** Bit definition for COMP_CSR register common ****************/
+#define COMP_CSR_COMPxEN_Pos (0U)
+#define COMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
+#define COMP_CSR_COMPxPOLARITY_Pos (15U)
+#define COMP_CSR_COMPxPOLARITY_Msk (0x1UL << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */
+#define COMP_CSR_COMPxOUTVALUE_Pos (30U)
+#define COMP_CSR_COMPxOUTVALUE_Msk (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK_Pos (31U)
+#define COMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
+
+/* Reference defines */
+#define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR (0xFFU) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos (3U)
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos (5U)
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos (7U)
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT_Pos (0U)
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL_Pos (0U)
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_Pos (0U)
+#define DBGMCU_CR_DBG_Msk (0x7UL << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
+#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos (23U)
+#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1_FZ_DBG_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+
+/******************* Bit definition for DMA_CSELR register *******************/
+#define DMA_CSELR_C1S_Pos (0U)
+#define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
+#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos (4U)
+#define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
+#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos (8U)
+#define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
+#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos (12U)
+#define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
+#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos (16U)
+#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
+#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S_Pos (20U)
+#define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
+#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S_Pos (24U)
+#define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
+#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_IM0_Pos (0U)
+#define EXTI_IMR_IM0_Msk (0x1UL << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_IM1_Pos (1U)
+#define EXTI_IMR_IM1_Msk (0x1UL << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_IM2_Pos (2U)
+#define EXTI_IMR_IM2_Msk (0x1UL << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_IM3_Pos (3U)
+#define EXTI_IMR_IM3_Msk (0x1UL << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_IM4_Pos (4U)
+#define EXTI_IMR_IM4_Msk (0x1UL << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_IM5_Pos (5U)
+#define EXTI_IMR_IM5_Msk (0x1UL << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_IM6_Pos (6U)
+#define EXTI_IMR_IM6_Msk (0x1UL << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_IM7_Pos (7U)
+#define EXTI_IMR_IM7_Msk (0x1UL << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_IM8_Pos (8U)
+#define EXTI_IMR_IM8_Msk (0x1UL << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_IM9_Pos (9U)
+#define EXTI_IMR_IM9_Msk (0x1UL << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_IM10_Pos (10U)
+#define EXTI_IMR_IM10_Msk (0x1UL << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_IM11_Pos (11U)
+#define EXTI_IMR_IM11_Msk (0x1UL << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_IM12_Pos (12U)
+#define EXTI_IMR_IM12_Msk (0x1UL << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_IM13_Pos (13U)
+#define EXTI_IMR_IM13_Msk (0x1UL << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_IM14_Pos (14U)
+#define EXTI_IMR_IM14_Msk (0x1UL << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_IM15_Pos (15U)
+#define EXTI_IMR_IM15_Msk (0x1UL << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_IM16_Pos (16U)
+#define EXTI_IMR_IM16_Msk (0x1UL << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_IM17_Pos (17U)
+#define EXTI_IMR_IM17_Msk (0x1UL << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_IM18_Pos (18U)
+#define EXTI_IMR_IM18_Msk (0x1UL << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_IM19_Pos (19U)
+#define EXTI_IMR_IM19_Msk (0x1UL << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_IM20_Pos (20U)
+#define EXTI_IMR_IM20_Msk (0x1UL << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_IM21_Pos (21U)
+#define EXTI_IMR_IM21_Msk (0x1UL << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_IM22_Pos (22U)
+#define EXTI_IMR_IM22_Msk (0x1UL << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_IM23_Pos (23U)
+#define EXTI_IMR_IM23_Msk (0x1UL << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
+#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_IM24_Pos (24U)
+#define EXTI_IMR_IM24_Msk (0x1UL << EXTI_IMR_IM24_Pos) /*!< 0x01000000 */
+#define EXTI_IMR_IM24 EXTI_IMR_IM24_Msk /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR_IM25_Pos (25U)
+#define EXTI_IMR_IM25_Msk (0x1UL << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */
+#define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_IM26_Pos (26U)
+#define EXTI_IMR_IM26_Msk (0x1UL << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
+#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_IM28_Pos (28U)
+#define EXTI_IMR_IM28_Msk (0x1UL << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
+#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_IM29_Pos (29U)
+#define EXTI_IMR_IM29_Msk (0x1UL << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
+#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
+
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x37FFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x37FFFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_EM0_Pos (0U)
+#define EXTI_EMR_EM0_Msk (0x1UL << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_EM1_Pos (1U)
+#define EXTI_EMR_EM1_Msk (0x1UL << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_EM2_Pos (2U)
+#define EXTI_EMR_EM2_Msk (0x1UL << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_EM3_Pos (3U)
+#define EXTI_EMR_EM3_Msk (0x1UL << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_EM4_Pos (4U)
+#define EXTI_EMR_EM4_Msk (0x1UL << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_EM5_Pos (5U)
+#define EXTI_EMR_EM5_Msk (0x1UL << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_EM6_Pos (6U)
+#define EXTI_EMR_EM6_Msk (0x1UL << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_EM7_Pos (7U)
+#define EXTI_EMR_EM7_Msk (0x1UL << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_EM8_Pos (8U)
+#define EXTI_EMR_EM8_Msk (0x1UL << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_EM9_Pos (9U)
+#define EXTI_EMR_EM9_Msk (0x1UL << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_EM10_Pos (10U)
+#define EXTI_EMR_EM10_Msk (0x1UL << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_EM11_Pos (11U)
+#define EXTI_EMR_EM11_Msk (0x1UL << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_EM12_Pos (12U)
+#define EXTI_EMR_EM12_Msk (0x1UL << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_EM13_Pos (13U)
+#define EXTI_EMR_EM13_Msk (0x1UL << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_EM14_Pos (14U)
+#define EXTI_EMR_EM14_Msk (0x1UL << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_EM15_Pos (15U)
+#define EXTI_EMR_EM15_Msk (0x1UL << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_EM16_Pos (16U)
+#define EXTI_EMR_EM16_Msk (0x1UL << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_EM17_Pos (17U)
+#define EXTI_EMR_EM17_Msk (0x1UL << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_EM18_Pos (18U)
+#define EXTI_EMR_EM18_Msk (0x1UL << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_EM19_Pos (19U)
+#define EXTI_EMR_EM19_Msk (0x1UL << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_EM20_Pos (20U)
+#define EXTI_EMR_EM20_Msk (0x1UL << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_EM21_Pos (21U)
+#define EXTI_EMR_EM21_Msk (0x1UL << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_EM22_Pos (22U)
+#define EXTI_EMR_EM22_Msk (0x1UL << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */
+#define EXTI_EMR_EM23_Pos (23U)
+#define EXTI_EMR_EM23_Msk (0x1UL << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
+#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
+#define EXTI_EMR_EM24_Pos (24U)
+#define EXTI_EMR_EM24_Msk (0x1UL << EXTI_EMR_EM24_Pos) /*!< 0x01000000 */
+#define EXTI_EMR_EM24 EXTI_EMR_EM24_Msk /*!< Event Mask on line 24 */
+#define EXTI_EMR_EM25_Pos (25U)
+#define EXTI_EMR_EM25_Msk (0x1UL << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */
+#define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */
+#define EXTI_EMR_EM26_Pos (26U)
+#define EXTI_EMR_EM26_Msk (0x1UL << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
+#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
+#define EXTI_EMR_EM28_Pos (28U)
+#define EXTI_EMR_EM28_Msk (0x1UL << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
+#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
+#define EXTI_EMR_EM29_Pos (29U)
+#define EXTI_EMR_EM29_Msk (0x1UL << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
+#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_RT0_Pos (0U)
+#define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_RT1_Pos (1U)
+#define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_RT2_Pos (2U)
+#define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_RT3_Pos (3U)
+#define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_RT4_Pos (4U)
+#define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_RT5_Pos (5U)
+#define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_RT6_Pos (6U)
+#define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_RT7_Pos (7U)
+#define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_RT8_Pos (8U)
+#define EXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_RT9_Pos (9U)
+#define EXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_RT10_Pos (10U)
+#define EXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_RT11_Pos (11U)
+#define EXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_RT12_Pos (12U)
+#define EXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_RT13_Pos (13U)
+#define EXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_RT14_Pos (14U)
+#define EXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_RT15_Pos (15U)
+#define EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_RT16_Pos (16U)
+#define EXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_RT17_Pos (17U)
+#define EXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_RT19_Pos (19U)
+#define EXTI_RTSR_RT19_Msk (0x1UL << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_RT20_Pos (20U)
+#define EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_RT21_Pos (21U)
+#define EXTI_RTSR_RT21_Msk (0x1UL << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_RT22_Pos (22U)
+#define EXTI_RTSR_RT22_Msk (0x1UL << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
+#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
+#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
+#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
+#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
+#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
+#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
+#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
+#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
+#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
+#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
+#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
+#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
+#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
+#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
+#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
+#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
+#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
+#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
+#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
+#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
+#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_FT0_Pos (0U)
+#define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_FT1_Pos (1U)
+#define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_FT2_Pos (2U)
+#define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_FT3_Pos (3U)
+#define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_FT4_Pos (4U)
+#define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_FT5_Pos (5U)
+#define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_FT6_Pos (6U)
+#define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_FT7_Pos (7U)
+#define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_FT8_Pos (8U)
+#define EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_FT9_Pos (9U)
+#define EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_FT10_Pos (10U)
+#define EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_FT11_Pos (11U)
+#define EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_FT12_Pos (12U)
+#define EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_FT13_Pos (13U)
+#define EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_FT14_Pos (14U)
+#define EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_FT15_Pos (15U)
+#define EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_FT16_Pos (16U)
+#define EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_FT17_Pos (17U)
+#define EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_FT19_Pos (19U)
+#define EXTI_FTSR_FT19_Msk (0x1UL << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_FT20_Pos (20U)
+#define EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_FT21_Pos (21U)
+#define EXTI_FTSR_FT21_Msk (0x1UL << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_FT22_Pos (22U)
+#define EXTI_FTSR_FT22_Msk (0x1UL << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
+#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
+#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
+#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
+#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
+#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
+#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
+#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
+#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
+#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
+#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
+#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
+#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
+#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
+#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
+#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
+#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
+#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
+#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
+#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
+#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
+#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWI0_Pos (0U)
+#define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWI1_Pos (1U)
+#define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWI2_Pos (2U)
+#define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWI3_Pos (3U)
+#define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWI4_Pos (4U)
+#define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWI5_Pos (5U)
+#define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWI6_Pos (6U)
+#define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWI7_Pos (7U)
+#define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWI8_Pos (8U)
+#define EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWI9_Pos (9U)
+#define EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWI10_Pos (10U)
+#define EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWI11_Pos (11U)
+#define EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWI12_Pos (12U)
+#define EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWI13_Pos (13U)
+#define EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWI14_Pos (14U)
+#define EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWI15_Pos (15U)
+#define EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWI16_Pos (16U)
+#define EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWI17_Pos (17U)
+#define EXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWI19_Pos (19U)
+#define EXTI_SWIER_SWI19_Msk (0x1UL << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWI20_Pos (20U)
+#define EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWI21_Pos (21U)
+#define EXTI_SWIER_SWI21_Msk (0x1UL << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWI22_Pos (22U)
+#define EXTI_SWIER_SWI22_Msk (0x1UL << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
+
+/* Legacy defines */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PIF0_Pos (0U)
+#define EXTI_PR_PIF0_Msk (0x1UL << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
+#define EXTI_PR_PIF1_Pos (1U)
+#define EXTI_PR_PIF1_Msk (0x1UL << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
+#define EXTI_PR_PIF2_Pos (2U)
+#define EXTI_PR_PIF2_Msk (0x1UL << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
+#define EXTI_PR_PIF3_Pos (3U)
+#define EXTI_PR_PIF3_Msk (0x1UL << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
+#define EXTI_PR_PIF4_Pos (4U)
+#define EXTI_PR_PIF4_Msk (0x1UL << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
+#define EXTI_PR_PIF5_Pos (5U)
+#define EXTI_PR_PIF5_Msk (0x1UL << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
+#define EXTI_PR_PIF6_Pos (6U)
+#define EXTI_PR_PIF6_Msk (0x1UL << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
+#define EXTI_PR_PIF7_Pos (7U)
+#define EXTI_PR_PIF7_Msk (0x1UL << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
+#define EXTI_PR_PIF8_Pos (8U)
+#define EXTI_PR_PIF8_Msk (0x1UL << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
+#define EXTI_PR_PIF9_Pos (9U)
+#define EXTI_PR_PIF9_Msk (0x1UL << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
+#define EXTI_PR_PIF10_Pos (10U)
+#define EXTI_PR_PIF10_Msk (0x1UL << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
+#define EXTI_PR_PIF11_Pos (11U)
+#define EXTI_PR_PIF11_Msk (0x1UL << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
+#define EXTI_PR_PIF12_Pos (12U)
+#define EXTI_PR_PIF12_Msk (0x1UL << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
+#define EXTI_PR_PIF13_Pos (13U)
+#define EXTI_PR_PIF13_Msk (0x1UL << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
+#define EXTI_PR_PIF14_Pos (14U)
+#define EXTI_PR_PIF14_Msk (0x1UL << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
+#define EXTI_PR_PIF15_Pos (15U)
+#define EXTI_PR_PIF15_Msk (0x1UL << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
+#define EXTI_PR_PIF16_Pos (16U)
+#define EXTI_PR_PIF16_Msk (0x1UL << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
+#define EXTI_PR_PIF17_Pos (17U)
+#define EXTI_PR_PIF17_Msk (0x1UL << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
+#define EXTI_PR_PIF19_Pos (19U)
+#define EXTI_PR_PIF19_Msk (0x1UL << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
+#define EXTI_PR_PIF20_Pos (20U)
+#define EXTI_PR_PIF20_Msk (0x1UL << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
+#define EXTI_PR_PIF21_Pos (21U)
+#define EXTI_PR_PIF21_Msk (0x1UL << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
+#define EXTI_PR_PIF22_Pos (22U)
+#define EXTI_PR_PIF22_Msk (0x1UL << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
+
+/* Legacy defines */
+#define EXTI_PR_PR0 EXTI_PR_PIF0
+#define EXTI_PR_PR1 EXTI_PR_PIF1
+#define EXTI_PR_PR2 EXTI_PR_PIF2
+#define EXTI_PR_PR3 EXTI_PR_PIF3
+#define EXTI_PR_PR4 EXTI_PR_PIF4
+#define EXTI_PR_PR5 EXTI_PR_PIF5
+#define EXTI_PR_PR6 EXTI_PR_PIF6
+#define EXTI_PR_PR7 EXTI_PR_PIF7
+#define EXTI_PR_PR8 EXTI_PR_PIF8
+#define EXTI_PR_PR9 EXTI_PR_PIF9
+#define EXTI_PR_PR10 EXTI_PR_PIF10
+#define EXTI_PR_PR11 EXTI_PR_PIF11
+#define EXTI_PR_PR12 EXTI_PR_PIF12
+#define EXTI_PR_PR13 EXTI_PR_PIF13
+#define EXTI_PR_PR14 EXTI_PR_PIF14
+#define EXTI_PR_PR15 EXTI_PR_PIF15
+#define EXTI_PR_PR16 EXTI_PR_PIF16
+#define EXTI_PR_PR17 EXTI_PR_PIF17
+#define EXTI_PR_PR19 EXTI_PR_PIF19
+#define EXTI_PR_PR20 EXTI_PR_PIF20
+#define EXTI_PR_PR21 EXTI_PR_PIF21
+#define EXTI_PR_PR22 EXTI_PR_PIF22
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
+#define FLASH_ACR_PRFTEN_Pos (1U)
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_SLEEP_PD_Pos (3U)
+#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD_Pos (4U)
+#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
+#define FLASH_ACR_DISAB_BUF_Pos (5U)
+#define FLASH_ACR_DISAB_BUF_Msk (0x1UL << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
+#define FLASH_ACR_PRE_READ_Pos (6U)
+#define FLASH_ACR_PRE_READ_Msk (0x1UL << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
+#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
+
+/******************* Bit definition for FLASH_PECR register ******************/
+#define FLASH_PECR_PELOCK_Pos (0U)
+#define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
+#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK_Pos (1U)
+#define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
+#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK_Pos (2U)
+#define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
+#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG_Pos (3U)
+#define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
+#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
+#define FLASH_PECR_DATA_Pos (4U)
+#define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
+#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
+#define FLASH_PECR_FIX_Pos (8U)
+#define FLASH_PECR_FIX_Msk (0x1UL << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
+#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE_Pos (9U)
+#define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
+#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
+#define FLASH_PECR_FPRG_Pos (10U)
+#define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
+#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_PARALLBANK_Pos (15U)
+#define FLASH_PECR_PARALLBANK_Msk (0x1UL << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */
+#define FLASH_PECR_PARALLBANK FLASH_PECR_PARALLBANK_Msk /*!< Parallel Bank mode */
+#define FLASH_PECR_EOPIE_Pos (16U)
+#define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
+#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
+#define FLASH_PECR_ERRIE_Pos (17U)
+#define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
+#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
+#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
+#define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
+#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
+#define FLASH_PECR_HALF_ARRAY_Pos (19U)
+#define FLASH_PECR_HALF_ARRAY_Msk (0x1UL << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
+#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
+#define FLASH_PECR_NZDISABLE_Pos (22U)
+#define FLASH_PECR_NZDISABLE_Msk (0x1UL << FLASH_PECR_NZDISABLE_Pos) /*!< 0x00400000 */
+#define FLASH_PECR_NZDISABLE FLASH_PECR_NZDISABLE_Msk /*!< Non-Zero check disable */
+
+/****************** Bit definition for FLASH_PDKEYR register ******************/
+#define FLASH_PDKEYR_PDKEYR_Pos (0U)
+#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PEKEYR register ******************/
+#define FLASH_PEKEYR_PEKEYR_Pos (0U)
+#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PRGKEYR register ******************/
+#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
+#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
+
+/****************** Bit definition for FLASH_OPTKEYR register ******************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_EOP_Pos (1U)
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
+#define FLASH_SR_HVOFF_Pos (2U)
+#define FLASH_SR_HVOFF_Msk (0x1UL << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
+#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
+#define FLASH_SR_READY_Pos (3U)
+#define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */
+#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR_Pos (8U)
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
+#define FLASH_SR_PGAERR_Pos (9U)
+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR_Pos (10U)
+#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
+#define FLASH_SR_OPTVERR_Pos (11U)
+#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
+#define FLASH_SR_RDERR_Pos (13U)
+#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
+#define FLASH_SR_NOTZEROERR_Pos (16U)
+#define FLASH_SR_NOTZEROERR_Msk (0x1UL << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
+#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
+#define FLASH_SR_FWWERR_Pos (17U)
+#define FLASH_SR_FWWERR_Msk (0x1UL << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
+#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
+
+/* Legacy defines */
+#define FLASH_SR_FWWER FLASH_SR_FWWERR
+#define FLASH_SR_ENHV FLASH_SR_HVOFF
+#define FLASH_SR_ENDHV FLASH_SR_HVOFF
+
+/****************** Bit definition for FLASH_OPTR register *******************/
+#define FLASH_OPTR_RDPROT_Pos (0U)
+#define FLASH_OPTR_RDPROT_Msk (0xFFUL << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
+#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
+#define FLASH_OPTR_WPRMOD_Pos (8U)
+#define FLASH_OPTR_WPRMOD_Msk (0x1UL << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
+#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
+#define FLASH_OPTR_BOR_LEV_Pos (16U)
+#define FLASH_OPTR_BOR_LEV_Msk (0xFUL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
+#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OPTR_IWDG_SW_Pos (20U)
+#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
+#define FLASH_OPTR_nRST_STOP_Pos (21U)
+#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OPTR_nRST_STDBY_Pos (22U)
+#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OPTR_BFB2_Pos (23U)
+#define FLASH_OPTR_BFB2_Msk (0x1UL << FLASH_OPTR_BFB2_Pos) /*!< 0x00800000 */
+#define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk /*!< BFB2 */
+#define FLASH_OPTR_USER_Pos (20U)
+#define FLASH_OPTR_USER_Msk (0x7UL << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
+#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OPTR_BOOT1_Pos (31U)
+#define FLASH_OPTR_BOOT1_Msk (0x1UL << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
+#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 (0x00000001U)
+#define GPIO_OTYPER_OT_1 (0x00000002U)
+#define GPIO_OTYPER_OT_2 (0x00000004U)
+#define GPIO_OTYPER_OT_3 (0x00000008U)
+#define GPIO_OTYPER_OT_4 (0x00000010U)
+#define GPIO_OTYPER_OT_5 (0x00000020U)
+#define GPIO_OTYPER_OT_6 (0x00000040U)
+#define GPIO_OTYPER_OT_7 (0x00000080U)
+#define GPIO_OTYPER_OT_8 (0x00000100U)
+#define GPIO_OTYPER_OT_9 (0x00000200U)
+#define GPIO_OTYPER_OT_10 (0x00000400U)
+#define GPIO_OTYPER_OT_11 (0x00000800U)
+#define GPIO_OTYPER_OT_12 (0x00001000U)
+#define GPIO_OTYPER_OT_13 (0x00002000U)
+#define GPIO_OTYPER_OT_14 (0x00004000U)
+#define GPIO_OTYPER_OT_15 (0x00008000U)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDER_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
+#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDER_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
+#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDER_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
+#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDER_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
+#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDER_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
+#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDER_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
+#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDER_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
+#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDER_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
+#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDER_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
+#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDER_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
+#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDER_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
+#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDER_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
+#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDER_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
+#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDER_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
+#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDER_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
+#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDER_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
+#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 (0x00000001U)
+#define GPIO_BSRR_BS_1 (0x00000002U)
+#define GPIO_BSRR_BS_2 (0x00000004U)
+#define GPIO_BSRR_BS_3 (0x00000008U)
+#define GPIO_BSRR_BS_4 (0x00000010U)
+#define GPIO_BSRR_BS_5 (0x00000020U)
+#define GPIO_BSRR_BS_6 (0x00000040U)
+#define GPIO_BSRR_BS_7 (0x00000080U)
+#define GPIO_BSRR_BS_8 (0x00000100U)
+#define GPIO_BSRR_BS_9 (0x00000200U)
+#define GPIO_BSRR_BS_10 (0x00000400U)
+#define GPIO_BSRR_BS_11 (0x00000800U)
+#define GPIO_BSRR_BS_12 (0x00001000U)
+#define GPIO_BSRR_BS_13 (0x00002000U)
+#define GPIO_BSRR_BS_14 (0x00004000U)
+#define GPIO_BSRR_BS_15 (0x00008000U)
+#define GPIO_BSRR_BR_0 (0x00010000U)
+#define GPIO_BSRR_BR_1 (0x00020000U)
+#define GPIO_BSRR_BR_2 (0x00040000U)
+#define GPIO_BSRR_BR_3 (0x00080000U)
+#define GPIO_BSRR_BR_4 (0x00100000U)
+#define GPIO_BSRR_BR_5 (0x00200000U)
+#define GPIO_BSRR_BR_6 (0x00400000U)
+#define GPIO_BSRR_BR_7 (0x00800000U)
+#define GPIO_BSRR_BR_8 (0x01000000U)
+#define GPIO_BSRR_BR_9 (0x02000000U)
+#define GPIO_BSRR_BR_10 (0x04000000U)
+#define GPIO_BSRR_BR_11 (0x08000000U)
+#define GPIO_BSRR_BR_12 (0x10000000U)
+#define GPIO_BSRR_BR_13 (0x20000000U)
+#define GPIO_BSRR_BR_14 (0x40000000U)
+#define GPIO_BSRR_BR_15 (0x80000000U)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 (0x00000001U)
+#define GPIO_BRR_BR_1 (0x00000002U)
+#define GPIO_BRR_BR_2 (0x00000004U)
+#define GPIO_BRR_BR_3 (0x00000008U)
+#define GPIO_BRR_BR_4 (0x00000010U)
+#define GPIO_BRR_BR_5 (0x00000020U)
+#define GPIO_BRR_BR_6 (0x00000040U)
+#define GPIO_BRR_BR_7 (0x00000080U)
+#define GPIO_BRR_BR_8 (0x00000100U)
+#define GPIO_BRR_BR_9 (0x00000200U)
+#define GPIO_BRR_BR_10 (0x00000400U)
+#define GPIO_BRR_BR_11 (0x00000800U)
+#define GPIO_BRR_BR_12 (0x00001000U)
+#define GPIO_BRR_BR_13 (0x00002000U)
+#define GPIO_BRR_BR_14 (0x00004000U)
+#define GPIO_BRR_BR_15 (0x00008000U)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos (1U)
+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos (2U)
+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos (3U)
+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos (4U)
+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos (5U)
+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos (6U)
+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos (7U)
+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos (8U)
+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos (12U)
+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos (14U)
+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos (15U)
+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos (16U)
+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos (17U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos (18U)
+#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos (19U)
+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos (20U)
+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos (21U)
+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos (22U)
+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos (23U)
+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD_Pos (0U)
+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos (10U)
+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos (11U)
+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos (12U)
+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos (13U)
+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
+#define I2C_CR2_STOP_Pos (14U)
+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos (15U)
+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos (16U)
+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos (24U)
+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos (25U)
+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos (26U)
+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1_Pos (0U)
+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos (10U)
+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos (15U)
+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2_Pos (1U)
+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos (8U)
+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos (8U)
+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos (9U)
+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos (8U)
+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos (10U)
+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos (8U)
+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos (9U)
+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos (8U)
+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos (15U)
+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos (0U)
+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos (8U)
+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos (16U)
+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos (20U)
+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos (28U)
+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE_Pos (0U)
+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos (1U)
+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos (2U)
+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos (3U)
+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos (4U)
+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos (5U)
+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos (6U)
+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos (7U)
+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos (8U)
+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
+#define I2C_ISR_ARLO_Pos (9U)
+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos (10U)
+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos (11U)
+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos (12U)
+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos (13U)
+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos (15U)
+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
+#define I2C_ISR_DIR_Pos (16U)
+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos (17U)
+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF_Pos (3U)
+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos (4U)
+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos (5U)
+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos (8U)
+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos (9U)
+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos (10U)
+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos (11U)
+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos (12U)
+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos (13U)
+#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define I2C_PECR_PEC_Pos (0U)
+#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA_Pos (0U)
+#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA_Pos (0U)
+#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos (2U)
+#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN_Pos (0U)
+#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM_Pos (0U)
+#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos (1U)
+#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos (2U)
+#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos (3U)
+#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos (4U)
+#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos (5U)
+#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos (6U)
+#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF_Pos (0U)
+#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos (1U)
+#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos (3U)
+#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos (4U)
+#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos (5U)
+#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos (6U)
+#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos (0U)
+#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos (1U)
+#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos (3U)
+#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos (4U)
+#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos (5U)
+#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos (6U)
+#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos (0U)
+#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos (1U)
+#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos (3U)
+#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos (6U)
+#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos (9U)
+#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos (17U)
+#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos (19U)
+#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos (20U)
+#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos (21U)
+#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos (22U)
+#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos (24U)
+#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE_Pos (0U)
+#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos (1U)
+#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos (2U)
+#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP_Pos (0U)
+#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR_Pos (0U)
+#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT_Pos (0U)
+#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
+
+/******************************************************************************/
+/* */
+/* MIFARE Firewall */
+/* */
+/******************************************************************************/
+
+/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
+#define FW_CSSA_ADD_Pos (8U)
+#define FW_CSSA_ADD_Msk (0xFFFFUL << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
+#define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
+#define FW_CSL_LENG_Pos (8U)
+#define FW_CSL_LENG_Msk (0x3FFFUL << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
+#define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
+#define FW_NVDSSA_ADD_Pos (8U)
+#define FW_NVDSSA_ADD_Msk (0xFFFFUL << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
+#define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
+#define FW_NVDSL_LENG_Pos (8U)
+#define FW_NVDSL_LENG_Msk (0x3FFFUL << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
+#define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
+#define FW_VDSSA_ADD_Pos (6U)
+#define FW_VDSSA_ADD_Msk (0x3FFUL << FW_VDSSA_ADD_Pos) /*!< 0x0000FFC0 */
+#define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
+#define FW_VDSL_LENG_Pos (6U)
+#define FW_VDSL_LENG_Msk (0x3FFUL << FW_VDSL_LENG_Pos) /*!< 0x0000FFC0 */
+#define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
+
+/**************************Bit definition for CR register *********************/
+#define FW_CR_FPA_Pos (0U)
+#define FW_CR_FPA_Msk (0x1UL << FW_CR_FPA_Pos) /*!< 0x00000001 */
+#define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
+#define FW_CR_VDS_Pos (1U)
+#define FW_CR_VDS_Msk (0x1UL << FW_CR_VDS_Pos) /*!< 0x00000002 */
+#define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
+#define FW_CR_VDE_Pos (2U)
+#define FW_CR_VDE_Msk (0x1UL << FW_CR_VDE_Pos) /*!< 0x00000004 */
+#define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
+
+/******************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/******************************************************************************/
+
+#define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPSDSR_Pos (0U)
+#define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP_Pos (9U)
+#define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /*!< 0x00000200 */
+#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
+#define PWR_CR_FWU_Pos (10U)
+#define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /*!< 0x00000400 */
+#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
+
+#define PWR_CR_VOS_Pos (11U)
+#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x00001800 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /*!< 0x00000800 */
+#define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /*!< 0x00001000 */
+#define PWR_CR_DSEEKOFF_Pos (13U)
+#define PWR_CR_DSEEKOFF_Msk (0x1UL << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */
+#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */
+#define PWR_CR_LPRUN_Pos (14U)
+#define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
+#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF_Pos (3U)
+#define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
+#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF_Pos (4U)
+#define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
+#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF_Pos (5U)
+#define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
+#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1_Pos (8U)
+#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2_Pos (9U)
+#define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
+#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP3_Pos (10U)
+#define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
+#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos (1U)
+#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos (2U)
+#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIVEN_Pos (3U)
+#define RCC_CR_HSIDIVEN_Msk (0x1UL << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */
+#define RCC_CR_HSIDIVF_Pos (4U)
+#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */
+#define RCC_CR_HSIOUTEN_Pos (5U)
+#define RCC_CR_HSIOUTEN_Msk (0x1UL << RCC_CR_HSIOUTEN_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_Msk /*!< Internal High Speed clock out enable */
+#define RCC_CR_MSION_Pos (8U)
+#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000100 */
+#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY_Pos (9U)
+#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
+#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON_Pos (19U)
+#define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */
+#define RCC_CR_RTCPRE_Pos (20U)
+#define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
+#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */
+#define RCC_CR_RTCPRE_0 (0x1UL << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */
+#define RCC_CR_RTCPRE_1 (0x2UL << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+/* Reference defines */
+#define RCC_CR_CSSON RCC_CR_CSSHSEON
+
+/******************** Bit definition for RCC_ICSCR register *****************/
+#define RCC_ICSCR_HSICAL_Pos (0U)
+#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
+#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM_Pos (8U)
+#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
+#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE_Pos (13U)
+#define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
+#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
+#define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
+#define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
+#define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
+#define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
+#define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
+#define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
+#define RCC_ICSCR_MSICAL_Pos (16U)
+#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
+#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM_Pos (24U)
+#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
+#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos (15U)
+#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */
+
+/*!< PLL entry clock source*/
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
+
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL_Pos (18U)
+#define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV_Pos (22U)
+#define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
+
+#define RCC_CFGR_PLLDIV2_Pos (22U)
+#define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3_Pos (23U)
+#define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4_Pos (22U)
+#define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCOSEL_Pos (24U)
+#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
+#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
+
+#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
+#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCOSEL_HSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_MSI_Pos (24U)
+#define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
+#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_HSE_Pos (26U)
+#define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCOSEL_PLL_Pos (24U)
+#define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
+#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
+#define RCC_CFGR_MCOSEL_LSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
+#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
+#define RCC_CFGR_MCOSEL_LSE_Pos (24U)
+#define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
+
+#define RCC_CFGR_MCOPRE_Pos (28U)
+#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
+
+#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
+
+/* Legacy defines */
+#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
+#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
+#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
+#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
+#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
+#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
+#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
+#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
+#ifdef RCC_CFGR_MCOSEL_HSI48
+#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48
+#endif
+
+#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
+#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
+
+/*!<****************** Bit definition for RCC_CIER register ********************/
+#define RCC_CIER_LSIRDYIE_Pos (0U)
+#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIER_LSERDYIE_Pos (1U)
+#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIER_HSIRDYIE_Pos (2U)
+#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIER_HSERDYIE_Pos (3U)
+#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIER_PLLRDYIE_Pos (4U)
+#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIER_MSIRDYIE_Pos (5U)
+#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
+#define RCC_CIER_CSSLSE_Pos (7U)
+#define RCC_CIER_CSSLSE_Msk (0x1UL << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */
+
+/* Reference defines */
+#define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
+
+/*!<****************** Bit definition for RCC_CIFR register ********************/
+#define RCC_CIFR_LSIRDYF_Pos (0U)
+#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIFR_LSERDYF_Pos (1U)
+#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIFR_HSIRDYF_Pos (2U)
+#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIFR_HSERDYF_Pos (3U)
+#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIFR_PLLRDYF_Pos (4U)
+#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIFR_MSIRDYF_Pos (5U)
+#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
+#define RCC_CIFR_CSSLSEF_Pos (7U)
+#define RCC_CIFR_CSSLSEF_Msk (0x1UL << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */
+#define RCC_CIFR_CSSHSEF_Pos (8U)
+#define RCC_CIFR_CSSHSEF_Msk (0x1UL << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */
+#define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */
+
+/* Reference defines */
+#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
+#define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
+
+/*!<****************** Bit definition for RCC_CICR register ********************/
+#define RCC_CICR_LSIRDYC_Pos (0U)
+#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CICR_LSERDYC_Pos (1U)
+#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CICR_HSIRDYC_Pos (2U)
+#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CICR_HSERDYC_Pos (3U)
+#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CICR_PLLRDYC_Pos (4U)
+#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CICR_MSIRDYC_Pos (5U)
+#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
+#define RCC_CICR_CSSLSEC_Pos (7U)
+#define RCC_CICR_CSSLSEC_Msk (0x1UL << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */
+#define RCC_CICR_CSSHSEC_Pos (8U)
+#define RCC_CICR_CSSHSEC_Msk (0x1UL << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */
+#define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */
+
+/* Reference defines */
+#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
+#define RCC_CICR_CSSC RCC_CICR_CSSHSEC
+/***************** Bit definition for RCC_IOPRSTR register ******************/
+#define RCC_IOPRSTR_IOPARST_Pos (0U)
+#define RCC_IOPRSTR_IOPARST_Msk (0x1UL << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */
+#define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */
+#define RCC_IOPRSTR_IOPBRST_Pos (1U)
+#define RCC_IOPRSTR_IOPBRST_Msk (0x1UL << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */
+#define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */
+#define RCC_IOPRSTR_IOPCRST_Pos (2U)
+#define RCC_IOPRSTR_IOPCRST_Msk (0x1UL << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */
+#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */
+#define RCC_IOPRSTR_IOPDRST_Pos (3U)
+#define RCC_IOPRSTR_IOPDRST_Msk (0x1UL << RCC_IOPRSTR_IOPDRST_Pos) /*!< 0x00000008 */
+#define RCC_IOPRSTR_IOPDRST RCC_IOPRSTR_IOPDRST_Msk /*!< GPIO port D reset */
+#define RCC_IOPRSTR_IOPERST_Pos (4U)
+#define RCC_IOPRSTR_IOPERST_Msk (0x1UL << RCC_IOPRSTR_IOPERST_Pos) /*!< 0x00000010 */
+#define RCC_IOPRSTR_IOPERST RCC_IOPRSTR_IOPERST_Msk /*!< GPIO port E reset */
+#define RCC_IOPRSTR_IOPHRST_Pos (7U)
+#define RCC_IOPRSTR_IOPHRST_Msk (0x1UL << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */
+#define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */
+
+/* Reference defines */
+#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
+#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
+#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
+#define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_IOPDRST /*!< GPIO port D reset */
+#define RCC_IOPRSTR_GPIOERST RCC_IOPRSTR_IOPERST /*!< GPIO port E reset */
+#define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
+
+
+/****************** Bit definition for RCC_AHBRST register ******************/
+#define RCC_AHBRSTR_DMARST_Pos (0U)
+#define RCC_AHBRSTR_DMARST_Msk (0x1UL << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */
+#define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */
+#define RCC_AHBRSTR_MIFRST_Pos (8U)
+#define RCC_AHBRSTR_MIFRST_Msk (0x1UL << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */
+#define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset */
+#define RCC_AHBRSTR_CRCRST_Pos (12U)
+#define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */
+
+/* Reference defines */
+#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
+#define RCC_APB2RSTR_TIM21RST_Pos (2U)
+#define RCC_APB2RSTR_TIM21RST_Msk (0x1UL << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 reset */
+#define RCC_APB2RSTR_TIM22RST_Pos (5U)
+#define RCC_APB2RSTR_TIM22RST_Msk (0x1UL << RCC_APB2RSTR_TIM22RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk /*!< TIM22 reset */
+#define RCC_APB2RSTR_ADCRST_Pos (9U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
+#define RCC_APB2RSTR_DBGRST_Pos (22U)
+#define RCC_APB2RSTR_DBGRST_Msk (0x1UL << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU reset */
+
+/* Reference defines */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 reset */
+#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU reset */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
+#define RCC_APB1RSTR_TIM7RST_Pos (5U)
+#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_LPUART1RST_Pos (18U)
+#define RCC_APB1RSTR_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 reset */
+#define RCC_APB1RSTR_USART4RST_Pos (19U)
+#define RCC_APB1RSTR_USART4RST_Msk (0x1UL << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART4 reset */
+#define RCC_APB1RSTR_USART5RST_Pos (20U)
+#define RCC_APB1RSTR_USART5RST_Msk (0x1UL << RCC_APB1RSTR_USART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR_USART5RST RCC_APB1RSTR_USART5RST_Msk /*!< USART5 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
+#define RCC_APB1RSTR_I2C3RST_Pos (30U)
+#define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk /*!< I2C3 reset */
+#define RCC_APB1RSTR_LPTIM1RST_Pos (31U)
+#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 reset */
+
+/***************** Bit definition for RCC_IOPENR register ******************/
+#define RCC_IOPENR_IOPAEN_Pos (0U)
+#define RCC_IOPENR_IOPAEN_Msk (0x1UL << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */
+#define RCC_IOPENR_IOPBEN_Pos (1U)
+#define RCC_IOPENR_IOPBEN_Msk (0x1UL << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */
+#define RCC_IOPENR_IOPCEN_Pos (2U)
+#define RCC_IOPENR_IOPCEN_Msk (0x1UL << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */
+#define RCC_IOPENR_IOPDEN_Pos (3U)
+#define RCC_IOPENR_IOPDEN_Msk (0x1UL << RCC_IOPENR_IOPDEN_Pos) /*!< 0x00000008 */
+#define RCC_IOPENR_IOPDEN RCC_IOPENR_IOPDEN_Msk /*!< GPIO port D clock enable */
+#define RCC_IOPENR_IOPEEN_Pos (4U)
+#define RCC_IOPENR_IOPEEN_Msk (0x1UL << RCC_IOPENR_IOPEEN_Pos) /*!< 0x00000010 */
+#define RCC_IOPENR_IOPEEN RCC_IOPENR_IOPEEN_Msk /*!< GPIO port E clock enable */
+#define RCC_IOPENR_IOPHEN_Pos (7U)
+#define RCC_IOPENR_IOPHEN_Msk (0x1UL << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */
+
+/* Reference defines */
+#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
+#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
+#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
+#define RCC_IOPENR_GPIODEN RCC_IOPENR_IOPDEN /*!< GPIO port D clock enable */
+#define RCC_IOPENR_GPIOEEN RCC_IOPENR_IOPEEN /*!< GPIO port E clock enable */
+#define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
+
+/***************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMAEN_Pos (0U)
+#define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_MIFEN_Pos (8U)
+#define RCC_AHBENR_MIFEN_Msk (0x1UL << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */
+#define RCC_AHBENR_CRCEN_Pos (12U)
+#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+
+/* Reference defines */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register ******************/
+#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM21EN_Pos (2U)
+#define RCC_APB2ENR_TIM21EN_Msk (0x1UL << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */
+#define RCC_APB2ENR_TIM22EN_Pos (5U)
+#define RCC_APB2ENR_TIM22EN_Msk (0x1UL << RCC_APB2ENR_TIM22EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk /*!< TIM22 clock enable */
+#define RCC_APB2ENR_FWEN_Pos (7U)
+#define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADCEN_Pos (9U)
+#define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
+#define RCC_APB2ENR_DBGEN_Pos (22U)
+#define RCC_APB2ENR_DBGEN_Msk (0x1UL << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */
+
+/* Reference defines */
+
+#define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN_Pos (5U)
+#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
+#define RCC_APB1ENR_LPUART1EN_Pos (18U)
+#define RCC_APB1ENR_LPUART1EN_Msk (0x1UL << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */
+#define RCC_APB1ENR_USART4EN_Pos (19U)
+#define RCC_APB1ENR_USART4EN_Msk (0x1UL << RCC_APB1ENR_USART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR_USART4EN RCC_APB1ENR_USART4EN_Msk /*!< USART4 clock enable */
+#define RCC_APB1ENR_USART5EN_Pos (20U)
+#define RCC_APB1ENR_USART5EN_Msk (0x1UL << RCC_APB1ENR_USART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR_USART5EN RCC_APB1ENR_USART5EN_Msk /*!< USART5 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
+#define RCC_APB1ENR_I2C3EN_Pos (30U)
+#define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk /*!< I2C3 clock enable */
+#define RCC_APB1ENR_LPTIM1EN_Pos (31U)
+#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */
+
+/****************** Bit definition for RCC_IOPSMENR register ****************/
+#define RCC_IOPSMENR_IOPASMEN_Pos (0U)
+#define RCC_IOPSMENR_IOPASMEN_Msk (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPBSMEN_Pos (1U)
+#define RCC_IOPSMENR_IOPBSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPCSMEN_Pos (2U)
+#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPDSMEN_Pos (3U)
+#define RCC_IOPSMENR_IOPDSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos) /*!< 0x00000008 */
+#define RCC_IOPSMENR_IOPDSMEN RCC_IOPSMENR_IOPDSMEN_Msk /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPESMEN_Pos (4U)
+#define RCC_IOPSMENR_IOPESMEN_Msk (0x1UL << RCC_IOPSMENR_IOPESMEN_Pos) /*!< 0x00000010 */
+#define RCC_IOPSMENR_IOPESMEN RCC_IOPSMENR_IOPESMEN_Msk /*!< GPIO port E clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPHSMEN_Pos (7U)
+#define RCC_IOPSMENR_IOPHSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_IOPDSMEN /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOESMEN RCC_IOPSMENR_IOPESMEN /*!< GPIO port E clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_AHBSMENR register ******************/
+#define RCC_AHBSMENR_DMASMEN_Pos (0U)
+#define RCC_AHBSMENR_DMASMEN_Msk (0x1UL << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */
+#define RCC_AHBSMENR_MIFSMEN_Pos (8U)
+#define RCC_AHBSMENR_MIFSMEN_Msk (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */
+#define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
+#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRCSMEN_Pos (12U)
+#define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB2SMENR register ******************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM21SMEN_Pos (2U)
+#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM22SMEN_Pos (5U)
+#define RCC_APB2SMENR_TIM22SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk /*!< TIM22 clock enabled in sleep mode */
+#define RCC_APB2SMENR_ADCSMEN_Pos (9U)
+#define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
+#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
+#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk /*!< USART1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGSMEN_Pos (22U)
+#define RCC_APB2SMENR_DBGSMEN_Msk (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB1SMENR register ******************/
+#define RCC_APB1SMENR_TIM2SMEN_Pos (0U)
+#define RCC_APB1SMENR_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_TIM3SMEN_Pos (1U)
+#define RCC_APB1SMENR_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM3SMEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1SMENR_TIM3SMEN RCC_APB1SMENR_TIM3SMEN_Msk /*!< Timer 3 clock enabled in sleep mode */
+#define RCC_APB1SMENR_TIM6SMEN_Pos (4U)
+#define RCC_APB1SMENR_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM6SMEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1SMENR_TIM6SMEN RCC_APB1SMENR_TIM6SMEN_Msk /*!< Timer 6 clock enabled in sleep mode */
+#define RCC_APB1SMENR_TIM7SMEN_Pos (5U)
+#define RCC_APB1SMENR_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM7SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1SMENR_TIM7SMEN RCC_APB1SMENR_TIM7SMEN_Msk /*!< Timer 7 clock enabled in sleep mode */
+#define RCC_APB1SMENR_WWDGSMEN_Pos (11U)
+#define RCC_APB1SMENR_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */
+#define RCC_APB1SMENR_SPI2SMEN_Pos (14U)
+#define RCC_APB1SMENR_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR_SPI2SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1SMENR_SPI2SMEN RCC_APB1SMENR_SPI2SMEN_Msk /*!< SPI2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART2SMEN_Pos (17U)
+#define RCC_APB1SMENR_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPUART1SMEN_Pos (18U)
+#define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART4SMEN_Pos (19U)
+#define RCC_APB1SMENR_USART4SMEN_Msk (0x1UL << RCC_APB1SMENR_USART4SMEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1SMENR_USART4SMEN RCC_APB1SMENR_USART4SMEN_Msk /*!< USART4 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART5SMEN_Pos (20U)
+#define RCC_APB1SMENR_USART5SMEN_Msk (0x1UL << RCC_APB1SMENR_USART5SMEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1SMENR_USART5SMEN RCC_APB1SMENR_USART5SMEN_Msk /*!< USART5 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C1SMEN_Pos (21U)
+#define RCC_APB1SMENR_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C2SMEN_Pos (22U)
+#define RCC_APB1SMENR_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1SMENR_I2C2SMEN RCC_APB1SMENR_I2C2SMEN_Msk /*!< I2C2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_PWRSMEN_Pos (28U)
+#define RCC_APB1SMENR_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C3SMEN_Pos (30U)
+#define RCC_APB1SMENR_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C3SMEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1SMENR_I2C3SMEN RCC_APB1SMENR_I2C3SMEN_Msk /*!< I2C3 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U)
+#define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */
+
+/******************* Bit definition for RCC_CCIPR register *******************/
+/*!< USART1 Clock source selection */
+#define RCC_CCIPR_USART1SEL_Pos (0U)
+#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
+#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk /*!< USART1SEL[1:0] bits */
+#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
+
+/*!< USART2 Clock source selection */
+#define RCC_CCIPR_USART2SEL_Pos (2U)
+#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */
+#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+/*!< LPUART1 Clock source selection */
+#define RCC_CCIPR_LPUART1SEL_Pos (10U)
+#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */
+#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */
+#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CCIPR_I2C1SEL_Pos (12U)
+#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */
+#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
+
+/*!< I2C3 Clock source selection */
+#define RCC_CCIPR_I2C3SEL_Pos (16U)
+#define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
+#define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk /*!< I2C3SEL [1:0] bits */
+#define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
+#define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
+
+/*!< LPTIM1 Clock source selection */
+#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
+#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */
+#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+/******************* Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSEON_Pos (8U)
+#define RCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */
+#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_CSR_LSERDY_Pos (9U)
+#define RCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */
+#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP_Pos (10U)
+#define RCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */
+#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_CSR_LSEDRV_Pos (11U)
+#define RCC_CSR_LSEDRV_Msk (0x3UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */
+#define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_CSR_LSEDRV_0 (0x1UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */
+#define RCC_CSR_LSEDRV_1 (0x2UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */
+
+#define RCC_CSR_LSECSSON_Pos (13U)
+#define RCC_CSR_LSECSSON_Msk (0x1UL << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */
+#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */
+#define RCC_CSR_LSECSSD_Pos (14U)
+#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
+#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
+
+/*!< RTC congiguration */
+#define RCC_CSR_RTCSEL_Pos (16U)
+#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
+
+#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CSR_RTCSEL_LSE_Pos (16U)
+#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_LSI_Pos (17U)
+#define RCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */
+#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_HSE_Pos (16U)
+#define RCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */
+
+#define RCC_CSR_RTCEN_Pos (18U)
+#define RCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */
+#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_CSR_RTCRST_Pos (19U)
+#define RCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */
+#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */
+
+#define RCC_CSR_RMVF_Pos (23U)
+#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_FWRSTF_Pos (24U)
+#define RCC_CSR_FWRSTF_Msk (0x1UL << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk /*!< Mifare Firewall reset flag */
+#define RCC_CSR_OBLRSTF_Pos (25U)
+#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+/* Reference defines */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER1_SUPPORT
+#define RTC_TAMPER2_SUPPORT
+#define RTC_TAMPER3_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk /*!< */
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk /*!< */
+#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk /*!< */
+#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */
+#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */
+#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk /*!< */
+#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk /*!< */
+#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk /*!< */
+#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk /*!< */
+#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */
+#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk /*!< */
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk /*!< */
+#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk /*!< */
+#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk /*!< */
+#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk /*!< */
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */
+#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk /*!< */
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< */
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */
+#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */
+#define RTC_ISR_TAMP3F_Pos (15U)
+#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk /*!< */
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */
+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */
+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */
+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */
+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */
+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */
+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */
+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */
+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */
+#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */
+#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */
+#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */
+#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */
+#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */
+#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */
+#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */
+#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */
+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */
+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */
+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */
+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */
+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */
+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */
+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */
+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */
+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */
+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CALR register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */
+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define RTC_CAL_CALP RTC_CALR_CALP
+#define RTC_CAL_CALW8 RTC_CALR_CALW8
+#define RTC_CAL_CALW16 RTC_CALR_CALW16
+#define RTC_CAL_CALM RTC_CALR_CALM
+#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
+
+/******************** Bits definition for RTC_TAMPCR register ****************/
+#define RTC_TAMPCR_TAMP3MF_Pos (24U)
+#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
+#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
+#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
+#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP3IE_Pos (22U)
+#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
+#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2MF_Pos (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2IE_Pos (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1MF_Pos (18U)
+#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
+#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1IE_Pos (16U)
+#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */
+#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */
+#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */
+#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos (7U)
+#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */
+#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
+#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
+#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP3E_Pos (5U)
+#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
+#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk /*!< */
+#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP2E_Pos (3U)
+#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */
+#define RTC_TAMPCR_TAMPIE_Pos (2U)
+#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
+#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP1E_Pos (0U)
+#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_OR register ****************/
+#define RTC_OR_OUT_RMP_Pos (1U)
+#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */
+#define RTC_OR_ALARMOUTTYPE_Pos (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */
+
+/* Legacy defines */
+#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk /*!< */
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER (0x00000005U) /*!< */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+#define SPI_I2S_SUPPORT /*!< I2S support */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
+#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
+#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
+#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR1_UFB_Pos (3U)
+#define SYSCFG_CFGR1_UFB_Msk (0x1UL << SYSCFG_CFGR1_UFB_Pos) /*!< 0x00000008 */
+#define SYSCFG_CFGR1_UFB SYSCFG_CFGR1_UFB_Msk /*!< User bank swapping */
+#define SYSCFG_CFGR1_BOOT_MODE_Pos (8U)
+#define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
+#define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */
+#define SYSCFG_CFGR1_BOOT_MODE_0 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOT_MODE_1 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_FWDISEN_Pos (0U)
+#define SYSCFG_CFGR2_FWDISEN_Msk (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos (8U)
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR2_I2C_PB6_FMP SYSCFG_CFGR2_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos (9U)
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR2_I2C_PB7_FMP SYSCFG_CFGR2_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos (10U)
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
+#define SYSCFG_CFGR2_I2C_PB8_FMP SYSCFG_CFGR2_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos (11U)
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
+#define SYSCFG_CFGR2_I2C_PB9_FMP SYSCFG_CFGR2_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR2_I2C1_FMP_Pos (12U)
+#define SYSCFG_CFGR2_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR2_I2C1_FMP SYSCFG_CFGR2_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR2_I2C2_FMP_Pos (13U)
+#define SYSCFG_CFGR2_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
+#define SYSCFG_CFGR2_I2C2_FMP SYSCFG_CFGR2_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
+#define SYSCFG_CFGR2_I2C3_FMP_Pos (14U)
+#define SYSCFG_CFGR2_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C3_FMP_Pos) /*!< 0x00004000 */
+#define SYSCFG_CFGR2_I2C3_FMP SYSCFG_CFGR2_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH (0x00000050U) /*!< PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH (0x00000500U) /*!< PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
+
+
+/***************** Bit definition for SYSCFG_CFGR3 register ****************/
+#define SYSCFG_CFGR3_EN_VREFINT_Pos (0U)
+#define SYSCFG_CFGR3_EN_VREFINT_Msk (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_EN_VREFINT SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
+#define SYSCFG_CFGR3_VREF_OUT_Pos (4U)
+#define SYSCFG_CFGR3_VREF_OUT_Msk (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
+#define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */
+#define SYSCFG_CFGR3_VREF_OUT_0 (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
+#define SYSCFG_CFGR3_VREF_OUT_1 (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U)
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U)
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U)
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
+#define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U)
+#define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
+#define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
+#define SYSCFG_CFGR3_REF_LOCK_Pos (31U)
+#define SYSCFG_CFGR3_REF_LOCK_Msk (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
+#define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */
+
+/* Legacy defines */
+
+#define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
+#define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
+#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
+#define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+
+/******************************************************************************/
+/* */
+/* Timers (TIM)*/
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
+#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
+ || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#else
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#endif
+
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFUL << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFUL << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM2_OR_ETR_RMP_Pos (0U)
+#define TIM2_OR_ETR_RMP_Msk (0x7UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000007 */
+#define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
+#define TIM2_OR_ETR_RMP_0 (0x1UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM2_OR_ETR_RMP_1 (0x2UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM2_OR_ETR_RMP_2 (0x4UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000004 */
+#define TIM2_OR_TI4_RMP_Pos (3U)
+#define TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000018 */
+#define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
+#define TIM2_OR_TI4_RMP_0 (0x1UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */
+#define TIM2_OR_TI4_RMP_1 (0x2UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000010 */
+
+#define TIM21_OR_ETR_RMP_Pos (0U)
+#define TIM21_OR_ETR_RMP_Msk (0x3UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
+#define TIM21_OR_ETR_RMP_0 (0x1UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM21_OR_ETR_RMP_1 (0x2UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM21_OR_TI1_RMP_Pos (2U)
+#define TIM21_OR_TI1_RMP_Msk (0x7UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x0000001C */
+#define TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
+#define TIM21_OR_TI1_RMP_0 (0x1UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM21_OR_TI1_RMP_1 (0x2UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+#define TIM21_OR_TI1_RMP_2 (0x4UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000010 */
+#define TIM21_OR_TI2_RMP_Pos (5U)
+#define TIM21_OR_TI2_RMP_Msk (0x1UL << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */
+#define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */
+
+#define TIM22_OR_ETR_RMP_Pos (0U)
+#define TIM22_OR_ETR_RMP_Msk (0x3UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM22_OR_ETR_RMP TIM22_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
+#define TIM22_OR_ETR_RMP_0 (0x1UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM22_OR_ETR_RMP_1 (0x2UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM22_OR_TI1_RMP_Pos (2U)
+#define TIM22_OR_TI1_RMP_Msk (0x3UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x0000000C */
+#define TIM22_OR_TI1_RMP TIM22_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
+#define TIM22_OR_TI1_RMP_0 (0x1UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM22_OR_TI1_RMP_1 (0x2UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+
+#define TIM3_OR_ETR_RMP_Pos (0U)
+#define TIM3_OR_ETR_RMP_Msk (0x3UL << TIM3_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM3_OR_ETR_RMP TIM3_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM3 ETR remap) */
+#define TIM3_OR_ETR_RMP_0 (0x1UL << TIM3_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM3_OR_ETR_RMP_1 (0x2UL << TIM3_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM3_OR_TI1_RMP_Pos (2U)
+#define TIM3_OR_TI1_RMP_Msk (0x1UL << TIM3_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM3_OR_TI1_RMP TIM3_OR_TI1_RMP_Msk /*!<TI1_RMP[2] bit */
+#define TIM3_OR_TI2_RMP_Pos (3U)
+#define TIM3_OR_TI2_RMP_Msk (0x1UL << TIM3_OR_TI2_RMP_Pos) /*!< 0x00000008 */
+#define TIM3_OR_TI2_RMP TIM3_OR_TI2_RMP_Msk /*!<TI2_RMP[3] bit */
+#define TIM3_OR_TI4_RMP_Pos (4U)
+#define TIM3_OR_TI4_RMP_Msk (0x1UL << TIM3_OR_TI4_RMP_Pos) /*!< 0x00000010 */
+#define TIM3_OR_TI4_RMP TIM3_OR_TI4_RMP_Msk /*!<TI4_RMP[4] bit */
+
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE_Pos (0U)
+#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+#define USART_CR1_UESM_Pos (1U)
+#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
+#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_M0_Pos (12U)
+#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
+#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos (13U)
+#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos (14U)
+#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos (16U)
+#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
+#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
+#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
+#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
+#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos (21U)
+#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
+#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
+#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
+#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
+#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos (26U)
+#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos (27U)
+#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos (28U)
+#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
+#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7_Pos (4U)
+#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos (15U)
+#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos (16U)
+#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos (17U)
+#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos (18U)
+#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos (19U)
+#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos (20U)
+#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos (21U)
+#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos (23U)
+#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos (24U)
+#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos (12U)
+#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos (13U)
+#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos (14U)
+#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos (15U)
+#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos (17U)
+#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos (20U)
+#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
+#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
+#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos (22U)
+#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
+#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
+#define USART_CR3_UCESM_Pos (23U)
+#define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
+#define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION_Pos (0U)
+#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos (4U)
+#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO_Pos (0U)
+#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos (24U)
+#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ_Pos (0U)
+#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
+#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos (1U)
+#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
+#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos (2U)
+#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
+#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos (3U)
+#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
+#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos (4U)
+#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
+#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE_Pos (0U)
+#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
+#define USART_ISR_FE_Pos (1U)
+#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
+#define USART_ISR_NE_Pos (2U)
+#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos (3U)
+#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos (4U)
+#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos (5U)
+#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos (6U)
+#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos (7U)
+#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
+#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos (8U)
+#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos (9U)
+#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos (10U)
+#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
+#define USART_ISR_RTOF_Pos (11U)
+#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos (12U)
+#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos (14U)
+#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos (15U)
+#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos (16U)
+#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
+#define USART_ISR_CMF_Pos (17U)
+#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos (18U)
+#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos (19U)
+#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos (20U)
+#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
+#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos (21U)
+#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos (22U)
+#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
+#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF_Pos (0U)
+#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos (1U)
+#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos (2U)
+#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */
+#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos (3U)
+#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos (4U)
+#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos (6U)
+#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF_Pos (8U)
+#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos (9U)
+#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos (11U)
+#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos (12U)
+#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos (17U)
+#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos (20U)
+#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
+#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
+
+/* Compatibility defines with other series */
+#define USART_ICR_NECF USART_ICR_NCF
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR_Pos (0U)
+#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR_Pos (0U)
+#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+/******************************* COMP Instances *******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+ ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOH))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C3))
+
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2)
+
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SMBUS Instances *****************************/
+#define IS_SMBUS_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/************* LPTIM instances supporting the encoder mode feature ************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ (((((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3)) \
+ && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM21) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM22) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/******************* TIM Instances : output(s) OCXEC register *****************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART4) || \
+ ((INSTANCE) == USART5))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART4) || \
+ ((INSTANCE) == USART5))
+
+/****************** USART Instances : Auto Baud Rate detection ****************/
+
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART4) || \
+ ((INSTANCE) == USART5) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART4) || \
+ ((INSTANCE) == USART5) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART4) || \
+ ((INSTANCE) == USART5) || \
+ ((INSTANCE) == LPUART1))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32L0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32L0 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+
+#define RNG_LPUART1_IRQn LPUART1_IRQn
+#define AES_LPUART1_IRQn LPUART1_IRQn
+#define AES_RNG_LPUART1_IRQn LPUART1_IRQn
+#define TIM6_DAC_IRQn TIM6_IRQn
+#define RCC_CRS_IRQn RCC_IRQn
+#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
+#define ADC1_IRQn ADC1_COMP_IRQn
+
+/* Aliases for __IRQHandler */
+#define RNG_LPUART1_IRQHandler LPUART1_IRQHandler
+#define AES_LPUART1_IRQHandler LPUART1_IRQHandler
+#define AES_RNG_LPUART1_IRQHandler LPUART1_IRQHandler
+#define TIM6_DAC_IRQHandler TIM6_IRQHandler
+#define RCC_CRS_IRQHandler RCC_IRQHandler
+#define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
+#define ADC1_IRQHandler ADC1_COMP_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L071xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/CMSIS/device/stm32l072xx.h b/CMSIS/device/stm32l072xx.h
new file mode 100644
index 0000000..eb36035
--- /dev/null
+++ b/CMSIS/device/stm32l072xx.h
@@ -0,0 +1,7683 @@
+/**
+ ******************************************************************************
+ * @file stm32l072xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for stm32l072xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright(c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l072xx
+ * @{
+ */
+
+#ifndef __STM32L072xx_H
+#define __STM32L072xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 1U /*!< STM32L0xx provides an MPU */
+#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
+#define __NVIC_PRIO_BITS 2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief stm32l072xx Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+/*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
+
+/****** STM32L-0 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */
+ RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ TSC_IRQn = 8, /*!< TSC Interrupt */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
+ ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
+ LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
+ USART4_5_IRQn = 14, /*!< USART4 and USART5 Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 Interrupt */
+ TIM3_IRQn = 16, /*!< TIM3 Interrupt */
+ TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
+ TIM7_IRQn = 18, /*!< TIM7 Interrupt */
+ TIM21_IRQn = 20, /*!< TIM21 Interrupt */
+ I2C3_IRQn = 21, /*!< I2C3 Interrupt */
+ TIM22_IRQn = 22, /*!< TIM22 Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */
+ I2C2_IRQn = 24, /*!< I2C2 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ SPI2_IRQn = 26, /*!< SPI2 Interrupt */
+ USART1_IRQn = 27, /*!< USART1 Interrupt */
+ USART2_IRQn = 28, /*!< USART2 Interrupt */
+ RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */
+ USB_IRQn = 31, /*!< USB global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0plus.h"
+#include "system_stm32l0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+ uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Comparator
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
+} COMP_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+
+/**
+* @brief CRC calculation unit
+*/
+
+typedef struct
+{
+__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+uint8_t RESERVED0; /*!< Reserved, 0x05 */
+uint16_t RESERVED1; /*!< Reserved, 0x06 */
+__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+uint32_t RESERVED2; /*!< Reserved, 0x0C */
+__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Clock Recovery System
+ */
+
+typedef struct
+{
+__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
+__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
+__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
+__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
+} CRS_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
+} DMA_Request_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
+ __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
+ __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
+ __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
+ __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
+ __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
+ __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
+ __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
+ __IO uint32_t RESERVED1[23]; /*!< Reserved1, Address offset: 0x24 */
+ __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
+ __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
+ __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
+ __IO uint32_t WRP23; /*!< write protection Bytes 2 and 3 Address offset: 0x0C */
+ __IO uint32_t WRP45; /*!< write protection Bytes 4 and 5 Address offset: 0x10 */
+} OB_TypeDef;
+
+
+/**
+ * @brief General Purpose IO
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief LPTIMIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+} LPTIM_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+ * @brief Independent WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief MIFARE Firewall
+ */
+typedef struct
+{
+ __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
+ __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
+ __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
+ __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
+ __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
+ __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
+ __IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x18 */
+ __IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */
+ __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
+
+} FIREWALL_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
+ __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
+ __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
+ __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
+ __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
+ __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
+ __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
+ __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
+ __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
+ __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
+ __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
+} RCC_TypeDef;
+
+/**
+ * @brief Random numbers generator
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Touch Sensing Controller (TSC)
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
+ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
+ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
+ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
+ __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief Universal Serial Bus Full Speed Device
+ */
+typedef struct
+{
+ __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
+ __IO uint16_t RESERVED0; /*!< Reserved */
+ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
+ __IO uint16_t RESERVED1; /*!< Reserved */
+ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
+ __IO uint16_t RESERVED2; /*!< Reserved */
+ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
+ __IO uint16_t RESERVED3; /*!< Reserved */
+ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
+ __IO uint16_t RESERVED4; /*!< Reserved */
+ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
+ __IO uint16_t RESERVED5; /*!< Reserved */
+ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
+ __IO uint16_t RESERVED6; /*!< Reserved */
+ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
+ __IO uint16_t RESERVED7[17]; /*!< Reserved */
+ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
+ __IO uint16_t RESERVED8; /*!< Reserved */
+ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
+ __IO uint16_t RESERVED9; /*!< Reserved */
+ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
+ __IO uint16_t RESERVEDA; /*!< Reserved */
+ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
+ __IO uint16_t RESERVEDB; /*!< Reserved */
+ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
+ __IO uint16_t RESERVEDC; /*!< Reserved */
+ __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
+ __IO uint16_t RESERVEDD; /*!< Reserved */
+ __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
+ __IO uint16_t RESERVEDE; /*!< Reserved */
+} USB_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */
+
+#define DATA_EEPROM_BASE (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
+#define DATA_EEPROM_BANK2_BASE (0x08080C00UL) /*!< DATA EEPROM BANK2 base address in the alias region */
+#define DATA_EEPROM_BANK1_END (0x08080BFFUL) /*!< Program end DATA EEPROM BANK1 address */
+#define DATA_EEPROM_BANK2_END (0x080817FFUL) /*!< Program end DATA EEPROM BANK2 address */
+#define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */
+#define SRAM_SIZE_MAX (0x00005000UL) /*!< maximum SRAM size (up to 20KBytes) */
+
+#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000UL)
+
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL)
+#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL)
+#define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL)
+#define TIM7_BASE (APBPERIPH_BASE + 0x00001400UL)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
+#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
+#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800UL)
+#define USART4_BASE (APBPERIPH_BASE + 0x00004C00UL)
+#define USART5_BASE (APBPERIPH_BASE + 0x00005000UL)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
+#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL)
+#define CRS_BASE (APBPERIPH_BASE + 0x00006C00UL)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
+#define DAC_BASE (APBPERIPH_BASE + 0x00007400UL)
+#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL)
+#define I2C3_BASE (APBPERIPH_BASE + 0x00007800UL)
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
+#define COMP1_BASE (APBPERIPH_BASE + 0x00010018UL)
+#define COMP2_BASE (APBPERIPH_BASE + 0x0001001CUL)
+#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL)
+#define TIM21_BASE (APBPERIPH_BASE + 0x00010800UL)
+#define TIM22_BASE (APBPERIPH_BASE + 0x00011400UL)
+#define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00UL)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708UL)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
+#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
+#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL)
+
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
+#define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */
+#define FLASHSIZE_BASE (0x1FF8007CUL) /*!< FLASH Size register base address */
+#define UID_BASE (0x1FF80050UL) /*!< Unique device ID register base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
+#define TSC_BASE (AHBPERIPH_BASE + 0x00004000UL)
+#define RNG_BASE (AHBPERIPH_BASE + 0x00005000UL)
+
+#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL)
+#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL)
+#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL)
+#define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00UL)
+#define GPIOE_BASE (IOPPERIPH_BASE + 0x00001000UL)
+#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00UL)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CRS ((CRS_TypeDef *) CRS_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define USART4 ((USART_TypeDef *) USART4_BASE)
+#define USART5 ((USART_TypeDef *) USART5_BASE)
+
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
+#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
+#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
+/* Legacy defines */
+#define ADC ADC1_COMMON
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define TSC ((TSC_TypeDef *) TSC_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+
+#define USB ((USB_TypeDef *) USB_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_EOCAL_Pos (11U)
+#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
+#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
+#define ADC_ISR_AWD_Pos (7U)
+#define ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
+#define ADC_ISR_EOSEQ_Pos (3U)
+#define ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_EOCALIE_Pos (11U)
+#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
+#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
+#define ADC_IER_AWDIE_Pos (7U)
+#define ADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE_Pos (3U)
+#define ADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH_Pos (26U)
+#define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
+#define ADC_CFGR1_AWDEN_Pos (23U)
+#define ADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL_Pos (22U)
+#define ADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN_Pos (16U)
+#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF_Pos (15U)
+#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
+#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT_Pos (14U)
+#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
+#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT_Pos (13U)
+#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD_Pos (12U)
+#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN_Pos (10U)
+#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
+#define ADC_CFGR1_EXTSEL_Pos (6U)
+#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
+#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
+#define ADC_CFGR1_ALIGN_Pos (5U)
+#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
+#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
+#define ADC_CFGR1_RES_Pos (3U)
+#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
+#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
+#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
+#define ADC_CFGR1_SCANDIR_Pos (2U)
+#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG_Pos (1U)
+#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
+#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN_Pos (0U)
+#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
+#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_TOVS_Pos (9U)
+#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
+#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+#define ADC_CFGR2_OVSR_Pos (2U)
+#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
+#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+#define ADC_CFGR2_OVSE_Pos (0U)
+#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
+#define ADC_CFGR2_CKMODE_Pos (30U)
+#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
+#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
+#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
+#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
+
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP_Pos (0U)
+#define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
+#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
+#define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
+#define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define ADC_SMPR_SMPR ADC_SMPR_SMP
+#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
+#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
+#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT_Pos (16U)
+#define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
+#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
+#define ADC_TR_LT_Pos (0U)
+#define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL_Pos (0U)
+#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
+#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
+#define ADC_CHSELR_CHSEL18_Pos (18U)
+#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17_Pos (17U)
+#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
+#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL15_Pos (15U)
+#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
+#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14_Pos (14U)
+#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
+#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13_Pos (13U)
+#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
+#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12_Pos (12U)
+#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
+#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11_Pos (11U)
+#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
+#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10_Pos (10U)
+#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
+#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9_Pos (9U)
+#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
+#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8_Pos (8U)
+#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
+#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7_Pos (7U)
+#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
+#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6_Pos (6U)
+#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
+#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5_Pos (5U)
+#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
+#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4_Pos (4U)
+#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
+#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3_Pos (3U)
+#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
+#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2_Pos (2U)
+#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
+#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1_Pos (1U)
+#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
+#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0_Pos (0U)
+#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
+#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_CALFACT_Pos (0U)
+#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_LFMEN_Pos (25U)
+#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
+#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
+#define ADC_CCR_TSEN_Pos (23U)
+#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+/************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN_Pos (0U)
+#define COMP_CSR_COMP1EN_Msk (0x1UL << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
+#define COMP_CSR_COMP1INNSEL_Pos (4U)
+#define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
+#define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP1WM_Pos (8U)
+#define COMP_CSR_COMP1WM_Msk (0x1UL << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */
+#define COMP_CSR_COMP1LPTIM1IN1_Pos (12U)
+#define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP1POLARITY_Pos (15U)
+#define COMP_CSR_COMP1POLARITY_Msk (0x1UL << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1VALUE_Pos (30U)
+#define COMP_CSR_COMP1VALUE_Msk (0x1UL << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK_Pos (31U)
+#define COMP_CSR_COMP1LOCK_Msk (0x1UL << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN_Pos (0U)
+#define COMP_CSR_COMP2EN_Msk (0x1UL << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
+#define COMP_CSR_COMP2SPEED_Pos (3U)
+#define COMP_CSR_COMP2SPEED_Msk (0x1UL << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */
+#define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */
+#define COMP_CSR_COMP2INNSEL_Pos (4U)
+#define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */
+#define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
+#define COMP_CSR_COMP2INPSEL_Pos (8U)
+#define COMP_CSR_COMP2INPSEL_Msk (0x7UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */
+#define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2INPSEL_0 (0x1UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP2INPSEL_1 (0x2UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */
+#define COMP_CSR_COMP2INPSEL_2 (0x4UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */
+#define COMP_CSR_COMP2LPTIM1IN2_Pos (12U)
+#define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */
+#define COMP_CSR_COMP2LPTIM1IN1_Pos (13U)
+#define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */
+#define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP2POLARITY_Pos (15U)
+#define COMP_CSR_COMP2POLARITY_Msk (0x1UL << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2VALUE_Pos (30U)
+#define COMP_CSR_COMP2VALUE_Msk (0x1UL << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK_Pos (31U)
+#define COMP_CSR_COMP2LOCK_Msk (0x1UL << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
+
+/********************** Bit definition for COMP_CSR register common ****************/
+#define COMP_CSR_COMPxEN_Pos (0U)
+#define COMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
+#define COMP_CSR_COMPxPOLARITY_Pos (15U)
+#define COMP_CSR_COMPxPOLARITY_Msk (0x1UL << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */
+#define COMP_CSR_COMPxOUTVALUE_Pos (30U)
+#define COMP_CSR_COMPxOUTVALUE_Msk (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK_Pos (31U)
+#define COMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
+
+/* Reference defines */
+#define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR (0xFFU) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos (3U)
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos (5U)
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos (7U)
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT_Pos (0U)
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL_Pos (0U)
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* CRS Clock Recovery System */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRS_CR register *********************/
+#define CRS_CR_SYNCOKIE_Pos (0U)
+#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
+#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /* SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE_Pos (1U)
+#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
+#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /* SYNC warning interrupt enable */
+#define CRS_CR_ERRIE_Pos (2U)
+#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
+#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /* SYNC error interrupt enable */
+#define CRS_CR_ESYNCIE_Pos (3U)
+#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
+#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /* Expected SYNC(ESYNCF) interrupt Enable*/
+#define CRS_CR_CEN_Pos (5U)
+#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
+#define CRS_CR_CEN CRS_CR_CEN_Msk /* Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN_Pos (6U)
+#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
+#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /* Automatic trimming enable */
+#define CRS_CR_SWSYNC_Pos (7U)
+#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
+#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /* A Software SYNC event is generated */
+#define CRS_CR_TRIM_Pos (8U)
+#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
+#define CRS_CR_TRIM CRS_CR_TRIM_Msk /* HSI48 oscillator smooth trimming */
+
+/******************* Bit definition for CRS_CFGR register *********************/
+#define CRS_CFGR_RELOAD_Pos (0U)
+#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
+#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /* Counter reload value */
+#define CRS_CFGR_FELIM_Pos (16U)
+#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
+#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /* Frequency error limit */
+
+#define CRS_CFGR_SYNCDIV_Pos (24U)
+#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
+#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /* SYNC divider */
+#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
+#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
+#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
+
+#define CRS_CFGR_SYNCSRC_Pos (28U)
+#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
+#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /* SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
+#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
+
+#define CRS_CFGR_SYNCPOL_Pos (31U)
+#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
+#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /* SYNC polarity selection */
+
+/******************* Bit definition for CRS_ISR register *********************/
+#define CRS_ISR_SYNCOKF_Pos (0U)
+#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
+#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /* SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF_Pos (1U)
+#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
+#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /* SYNC warning */
+#define CRS_ISR_ERRF_Pos (2U)
+#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
+#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /* SYNC error flag */
+#define CRS_ISR_ESYNCF_Pos (3U)
+#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
+#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /* Expected SYNC flag */
+#define CRS_ISR_SYNCERR_Pos (8U)
+#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
+#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /* SYNC error */
+#define CRS_ISR_SYNCMISS_Pos (9U)
+#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
+#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /* SYNC missed */
+#define CRS_ISR_TRIMOVF_Pos (10U)
+#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
+#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /* Trimming overflow or underflow */
+#define CRS_ISR_FEDIR_Pos (15U)
+#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
+#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /* Frequency error direction */
+#define CRS_ISR_FECAP_Pos (16U)
+#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
+#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /* Frequency error capture */
+
+/******************* Bit definition for CRS_ICR register *********************/
+#define CRS_ICR_SYNCOKC_Pos (0U)
+#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
+#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /* SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC_Pos (1U)
+#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
+#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /* SYNC warning clear flag */
+#define CRS_ICR_ERRC_Pos (2U)
+#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
+#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /* Error clear flag */
+#define CRS_ICR_ESYNCC_Pos (3U)
+#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
+#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /* Expected SYNC clear flag */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter (DAC) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos (1U)
+#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos (2U)
+#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (3U)
+#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos (13U)
+#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun interrupt enable */
+
+#define DAC_CR_EN2_Pos (16U)
+#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */
+#define DAC_CR_BOFF2_Pos (17U)
+#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
+#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */
+#define DAC_CR_TEN2_Pos (18U)
+#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos (19U)
+#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos (22U)
+#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos (24U)
+#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos (28U)
+#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos (29U)
+#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel12DMA Underrun interrupt enable */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR_Pos (0U)
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1_Pos (13U)
+#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2_Pos (29U)
+#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_DIV_ID_Pos (12U)
+#define DBGMCU_IDCODE_DIV_ID_Msk (0xFUL << DBGMCU_IDCODE_DIV_ID_Pos) /*!< 0x0000F000 */
+#define DBGMCU_IDCODE_DIV_ID DBGMCU_IDCODE_DIV_ID_Msk /*!< Division Identifier */
+#define DBGMCU_IDCODE_MCD_DIV_ID_Pos (13U)
+#define DBGMCU_IDCODE_MCD_DIV_ID_Msk (0x3UL << DBGMCU_IDCODE_MCD_DIV_ID_Pos) /*!< 0x00006000 */
+#define DBGMCU_IDCODE_MCD_DIV_ID DBGMCU_IDCODE_MCD_DIV_ID_Msk /*!< MCD divsion ID is 6 */
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_Pos (0U)
+#define DBGMCU_CR_DBG_Msk (0x7UL << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
+#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos (23U)
+#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1_FZ_DBG_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+
+/******************* Bit definition for DMA_CSELR register *******************/
+#define DMA_CSELR_C1S_Pos (0U)
+#define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
+#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos (4U)
+#define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
+#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos (8U)
+#define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
+#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos (12U)
+#define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
+#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos (16U)
+#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
+#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S_Pos (20U)
+#define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
+#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S_Pos (24U)
+#define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
+#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_IM0_Pos (0U)
+#define EXTI_IMR_IM0_Msk (0x1UL << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_IM1_Pos (1U)
+#define EXTI_IMR_IM1_Msk (0x1UL << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_IM2_Pos (2U)
+#define EXTI_IMR_IM2_Msk (0x1UL << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_IM3_Pos (3U)
+#define EXTI_IMR_IM3_Msk (0x1UL << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_IM4_Pos (4U)
+#define EXTI_IMR_IM4_Msk (0x1UL << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_IM5_Pos (5U)
+#define EXTI_IMR_IM5_Msk (0x1UL << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_IM6_Pos (6U)
+#define EXTI_IMR_IM6_Msk (0x1UL << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_IM7_Pos (7U)
+#define EXTI_IMR_IM7_Msk (0x1UL << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_IM8_Pos (8U)
+#define EXTI_IMR_IM8_Msk (0x1UL << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_IM9_Pos (9U)
+#define EXTI_IMR_IM9_Msk (0x1UL << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_IM10_Pos (10U)
+#define EXTI_IMR_IM10_Msk (0x1UL << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_IM11_Pos (11U)
+#define EXTI_IMR_IM11_Msk (0x1UL << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_IM12_Pos (12U)
+#define EXTI_IMR_IM12_Msk (0x1UL << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_IM13_Pos (13U)
+#define EXTI_IMR_IM13_Msk (0x1UL << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_IM14_Pos (14U)
+#define EXTI_IMR_IM14_Msk (0x1UL << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_IM15_Pos (15U)
+#define EXTI_IMR_IM15_Msk (0x1UL << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_IM16_Pos (16U)
+#define EXTI_IMR_IM16_Msk (0x1UL << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_IM17_Pos (17U)
+#define EXTI_IMR_IM17_Msk (0x1UL << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_IM18_Pos (18U)
+#define EXTI_IMR_IM18_Msk (0x1UL << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_IM19_Pos (19U)
+#define EXTI_IMR_IM19_Msk (0x1UL << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_IM20_Pos (20U)
+#define EXTI_IMR_IM20_Msk (0x1UL << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_IM21_Pos (21U)
+#define EXTI_IMR_IM21_Msk (0x1UL << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_IM22_Pos (22U)
+#define EXTI_IMR_IM22_Msk (0x1UL << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_IM23_Pos (23U)
+#define EXTI_IMR_IM23_Msk (0x1UL << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
+#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_IM24_Pos (24U)
+#define EXTI_IMR_IM24_Msk (0x1UL << EXTI_IMR_IM24_Pos) /*!< 0x01000000 */
+#define EXTI_IMR_IM24 EXTI_IMR_IM24_Msk /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR_IM25_Pos (25U)
+#define EXTI_IMR_IM25_Msk (0x1UL << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */
+#define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_IM26_Pos (26U)
+#define EXTI_IMR_IM26_Msk (0x1UL << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
+#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_IM28_Pos (28U)
+#define EXTI_IMR_IM28_Msk (0x1UL << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
+#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_IM29_Pos (29U)
+#define EXTI_IMR_IM29_Msk (0x1UL << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
+#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
+
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x37FFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x37FFFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_EM0_Pos (0U)
+#define EXTI_EMR_EM0_Msk (0x1UL << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_EM1_Pos (1U)
+#define EXTI_EMR_EM1_Msk (0x1UL << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_EM2_Pos (2U)
+#define EXTI_EMR_EM2_Msk (0x1UL << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_EM3_Pos (3U)
+#define EXTI_EMR_EM3_Msk (0x1UL << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_EM4_Pos (4U)
+#define EXTI_EMR_EM4_Msk (0x1UL << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_EM5_Pos (5U)
+#define EXTI_EMR_EM5_Msk (0x1UL << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_EM6_Pos (6U)
+#define EXTI_EMR_EM6_Msk (0x1UL << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_EM7_Pos (7U)
+#define EXTI_EMR_EM7_Msk (0x1UL << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_EM8_Pos (8U)
+#define EXTI_EMR_EM8_Msk (0x1UL << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_EM9_Pos (9U)
+#define EXTI_EMR_EM9_Msk (0x1UL << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_EM10_Pos (10U)
+#define EXTI_EMR_EM10_Msk (0x1UL << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_EM11_Pos (11U)
+#define EXTI_EMR_EM11_Msk (0x1UL << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_EM12_Pos (12U)
+#define EXTI_EMR_EM12_Msk (0x1UL << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_EM13_Pos (13U)
+#define EXTI_EMR_EM13_Msk (0x1UL << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_EM14_Pos (14U)
+#define EXTI_EMR_EM14_Msk (0x1UL << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_EM15_Pos (15U)
+#define EXTI_EMR_EM15_Msk (0x1UL << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_EM16_Pos (16U)
+#define EXTI_EMR_EM16_Msk (0x1UL << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_EM17_Pos (17U)
+#define EXTI_EMR_EM17_Msk (0x1UL << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_EM18_Pos (18U)
+#define EXTI_EMR_EM18_Msk (0x1UL << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_EM19_Pos (19U)
+#define EXTI_EMR_EM19_Msk (0x1UL << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_EM20_Pos (20U)
+#define EXTI_EMR_EM20_Msk (0x1UL << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_EM21_Pos (21U)
+#define EXTI_EMR_EM21_Msk (0x1UL << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_EM22_Pos (22U)
+#define EXTI_EMR_EM22_Msk (0x1UL << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */
+#define EXTI_EMR_EM23_Pos (23U)
+#define EXTI_EMR_EM23_Msk (0x1UL << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
+#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
+#define EXTI_EMR_EM24_Pos (24U)
+#define EXTI_EMR_EM24_Msk (0x1UL << EXTI_EMR_EM24_Pos) /*!< 0x01000000 */
+#define EXTI_EMR_EM24 EXTI_EMR_EM24_Msk /*!< Event Mask on line 24 */
+#define EXTI_EMR_EM25_Pos (25U)
+#define EXTI_EMR_EM25_Msk (0x1UL << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */
+#define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */
+#define EXTI_EMR_EM26_Pos (26U)
+#define EXTI_EMR_EM26_Msk (0x1UL << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
+#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
+#define EXTI_EMR_EM28_Pos (28U)
+#define EXTI_EMR_EM28_Msk (0x1UL << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
+#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
+#define EXTI_EMR_EM29_Pos (29U)
+#define EXTI_EMR_EM29_Msk (0x1UL << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
+#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_RT0_Pos (0U)
+#define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_RT1_Pos (1U)
+#define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_RT2_Pos (2U)
+#define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_RT3_Pos (3U)
+#define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_RT4_Pos (4U)
+#define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_RT5_Pos (5U)
+#define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_RT6_Pos (6U)
+#define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_RT7_Pos (7U)
+#define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_RT8_Pos (8U)
+#define EXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_RT9_Pos (9U)
+#define EXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_RT10_Pos (10U)
+#define EXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_RT11_Pos (11U)
+#define EXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_RT12_Pos (12U)
+#define EXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_RT13_Pos (13U)
+#define EXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_RT14_Pos (14U)
+#define EXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_RT15_Pos (15U)
+#define EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_RT16_Pos (16U)
+#define EXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_RT17_Pos (17U)
+#define EXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_RT19_Pos (19U)
+#define EXTI_RTSR_RT19_Msk (0x1UL << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_RT20_Pos (20U)
+#define EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_RT21_Pos (21U)
+#define EXTI_RTSR_RT21_Msk (0x1UL << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_RT22_Pos (22U)
+#define EXTI_RTSR_RT22_Msk (0x1UL << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
+#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
+#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
+#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
+#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
+#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
+#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
+#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
+#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
+#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
+#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
+#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
+#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
+#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
+#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
+#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
+#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
+#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
+#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
+#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
+#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
+#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_FT0_Pos (0U)
+#define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_FT1_Pos (1U)
+#define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_FT2_Pos (2U)
+#define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_FT3_Pos (3U)
+#define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_FT4_Pos (4U)
+#define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_FT5_Pos (5U)
+#define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_FT6_Pos (6U)
+#define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_FT7_Pos (7U)
+#define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_FT8_Pos (8U)
+#define EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_FT9_Pos (9U)
+#define EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_FT10_Pos (10U)
+#define EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_FT11_Pos (11U)
+#define EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_FT12_Pos (12U)
+#define EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_FT13_Pos (13U)
+#define EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_FT14_Pos (14U)
+#define EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_FT15_Pos (15U)
+#define EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_FT16_Pos (16U)
+#define EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_FT17_Pos (17U)
+#define EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_FT19_Pos (19U)
+#define EXTI_FTSR_FT19_Msk (0x1UL << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_FT20_Pos (20U)
+#define EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_FT21_Pos (21U)
+#define EXTI_FTSR_FT21_Msk (0x1UL << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_FT22_Pos (22U)
+#define EXTI_FTSR_FT22_Msk (0x1UL << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
+#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
+#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
+#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
+#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
+#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
+#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
+#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
+#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
+#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
+#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
+#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
+#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
+#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
+#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
+#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
+#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
+#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
+#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
+#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
+#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
+#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWI0_Pos (0U)
+#define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWI1_Pos (1U)
+#define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWI2_Pos (2U)
+#define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWI3_Pos (3U)
+#define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWI4_Pos (4U)
+#define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWI5_Pos (5U)
+#define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWI6_Pos (6U)
+#define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWI7_Pos (7U)
+#define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWI8_Pos (8U)
+#define EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWI9_Pos (9U)
+#define EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWI10_Pos (10U)
+#define EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWI11_Pos (11U)
+#define EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWI12_Pos (12U)
+#define EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWI13_Pos (13U)
+#define EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWI14_Pos (14U)
+#define EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWI15_Pos (15U)
+#define EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWI16_Pos (16U)
+#define EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWI17_Pos (17U)
+#define EXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWI19_Pos (19U)
+#define EXTI_SWIER_SWI19_Msk (0x1UL << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWI20_Pos (20U)
+#define EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWI21_Pos (21U)
+#define EXTI_SWIER_SWI21_Msk (0x1UL << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWI22_Pos (22U)
+#define EXTI_SWIER_SWI22_Msk (0x1UL << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
+
+/* Legacy defines */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PIF0_Pos (0U)
+#define EXTI_PR_PIF0_Msk (0x1UL << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
+#define EXTI_PR_PIF1_Pos (1U)
+#define EXTI_PR_PIF1_Msk (0x1UL << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
+#define EXTI_PR_PIF2_Pos (2U)
+#define EXTI_PR_PIF2_Msk (0x1UL << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
+#define EXTI_PR_PIF3_Pos (3U)
+#define EXTI_PR_PIF3_Msk (0x1UL << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
+#define EXTI_PR_PIF4_Pos (4U)
+#define EXTI_PR_PIF4_Msk (0x1UL << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
+#define EXTI_PR_PIF5_Pos (5U)
+#define EXTI_PR_PIF5_Msk (0x1UL << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
+#define EXTI_PR_PIF6_Pos (6U)
+#define EXTI_PR_PIF6_Msk (0x1UL << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
+#define EXTI_PR_PIF7_Pos (7U)
+#define EXTI_PR_PIF7_Msk (0x1UL << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
+#define EXTI_PR_PIF8_Pos (8U)
+#define EXTI_PR_PIF8_Msk (0x1UL << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
+#define EXTI_PR_PIF9_Pos (9U)
+#define EXTI_PR_PIF9_Msk (0x1UL << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
+#define EXTI_PR_PIF10_Pos (10U)
+#define EXTI_PR_PIF10_Msk (0x1UL << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
+#define EXTI_PR_PIF11_Pos (11U)
+#define EXTI_PR_PIF11_Msk (0x1UL << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
+#define EXTI_PR_PIF12_Pos (12U)
+#define EXTI_PR_PIF12_Msk (0x1UL << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
+#define EXTI_PR_PIF13_Pos (13U)
+#define EXTI_PR_PIF13_Msk (0x1UL << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
+#define EXTI_PR_PIF14_Pos (14U)
+#define EXTI_PR_PIF14_Msk (0x1UL << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
+#define EXTI_PR_PIF15_Pos (15U)
+#define EXTI_PR_PIF15_Msk (0x1UL << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
+#define EXTI_PR_PIF16_Pos (16U)
+#define EXTI_PR_PIF16_Msk (0x1UL << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
+#define EXTI_PR_PIF17_Pos (17U)
+#define EXTI_PR_PIF17_Msk (0x1UL << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
+#define EXTI_PR_PIF19_Pos (19U)
+#define EXTI_PR_PIF19_Msk (0x1UL << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
+#define EXTI_PR_PIF20_Pos (20U)
+#define EXTI_PR_PIF20_Msk (0x1UL << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
+#define EXTI_PR_PIF21_Pos (21U)
+#define EXTI_PR_PIF21_Msk (0x1UL << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
+#define EXTI_PR_PIF22_Pos (22U)
+#define EXTI_PR_PIF22_Msk (0x1UL << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
+
+/* Legacy defines */
+#define EXTI_PR_PR0 EXTI_PR_PIF0
+#define EXTI_PR_PR1 EXTI_PR_PIF1
+#define EXTI_PR_PR2 EXTI_PR_PIF2
+#define EXTI_PR_PR3 EXTI_PR_PIF3
+#define EXTI_PR_PR4 EXTI_PR_PIF4
+#define EXTI_PR_PR5 EXTI_PR_PIF5
+#define EXTI_PR_PR6 EXTI_PR_PIF6
+#define EXTI_PR_PR7 EXTI_PR_PIF7
+#define EXTI_PR_PR8 EXTI_PR_PIF8
+#define EXTI_PR_PR9 EXTI_PR_PIF9
+#define EXTI_PR_PR10 EXTI_PR_PIF10
+#define EXTI_PR_PR11 EXTI_PR_PIF11
+#define EXTI_PR_PR12 EXTI_PR_PIF12
+#define EXTI_PR_PR13 EXTI_PR_PIF13
+#define EXTI_PR_PR14 EXTI_PR_PIF14
+#define EXTI_PR_PR15 EXTI_PR_PIF15
+#define EXTI_PR_PR16 EXTI_PR_PIF16
+#define EXTI_PR_PR17 EXTI_PR_PIF17
+#define EXTI_PR_PR19 EXTI_PR_PIF19
+#define EXTI_PR_PR20 EXTI_PR_PIF20
+#define EXTI_PR_PR21 EXTI_PR_PIF21
+#define EXTI_PR_PR22 EXTI_PR_PIF22
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
+#define FLASH_ACR_PRFTEN_Pos (1U)
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_SLEEP_PD_Pos (3U)
+#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD_Pos (4U)
+#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
+#define FLASH_ACR_DISAB_BUF_Pos (5U)
+#define FLASH_ACR_DISAB_BUF_Msk (0x1UL << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
+#define FLASH_ACR_PRE_READ_Pos (6U)
+#define FLASH_ACR_PRE_READ_Msk (0x1UL << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
+#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
+
+/******************* Bit definition for FLASH_PECR register ******************/
+#define FLASH_PECR_PELOCK_Pos (0U)
+#define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
+#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK_Pos (1U)
+#define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
+#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK_Pos (2U)
+#define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
+#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG_Pos (3U)
+#define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
+#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
+#define FLASH_PECR_DATA_Pos (4U)
+#define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
+#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
+#define FLASH_PECR_FIX_Pos (8U)
+#define FLASH_PECR_FIX_Msk (0x1UL << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
+#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE_Pos (9U)
+#define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
+#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
+#define FLASH_PECR_FPRG_Pos (10U)
+#define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
+#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_PARALLBANK_Pos (15U)
+#define FLASH_PECR_PARALLBANK_Msk (0x1UL << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */
+#define FLASH_PECR_PARALLBANK FLASH_PECR_PARALLBANK_Msk /*!< Parallel Bank mode */
+#define FLASH_PECR_EOPIE_Pos (16U)
+#define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
+#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
+#define FLASH_PECR_ERRIE_Pos (17U)
+#define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
+#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
+#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
+#define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
+#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
+#define FLASH_PECR_HALF_ARRAY_Pos (19U)
+#define FLASH_PECR_HALF_ARRAY_Msk (0x1UL << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
+#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
+#define FLASH_PECR_NZDISABLE_Pos (22U)
+#define FLASH_PECR_NZDISABLE_Msk (0x1UL << FLASH_PECR_NZDISABLE_Pos) /*!< 0x00400000 */
+#define FLASH_PECR_NZDISABLE FLASH_PECR_NZDISABLE_Msk /*!< Non-Zero check disable */
+
+/****************** Bit definition for FLASH_PDKEYR register ******************/
+#define FLASH_PDKEYR_PDKEYR_Pos (0U)
+#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PEKEYR register ******************/
+#define FLASH_PEKEYR_PEKEYR_Pos (0U)
+#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PRGKEYR register ******************/
+#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
+#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
+
+/****************** Bit definition for FLASH_OPTKEYR register ******************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_EOP_Pos (1U)
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
+#define FLASH_SR_HVOFF_Pos (2U)
+#define FLASH_SR_HVOFF_Msk (0x1UL << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
+#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
+#define FLASH_SR_READY_Pos (3U)
+#define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */
+#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR_Pos (8U)
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
+#define FLASH_SR_PGAERR_Pos (9U)
+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR_Pos (10U)
+#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
+#define FLASH_SR_OPTVERR_Pos (11U)
+#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
+#define FLASH_SR_RDERR_Pos (13U)
+#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
+#define FLASH_SR_NOTZEROERR_Pos (16U)
+#define FLASH_SR_NOTZEROERR_Msk (0x1UL << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
+#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
+#define FLASH_SR_FWWERR_Pos (17U)
+#define FLASH_SR_FWWERR_Msk (0x1UL << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
+#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
+
+/* Legacy defines */
+#define FLASH_SR_FWWER FLASH_SR_FWWERR
+#define FLASH_SR_ENHV FLASH_SR_HVOFF
+#define FLASH_SR_ENDHV FLASH_SR_HVOFF
+
+/****************** Bit definition for FLASH_OPTR register *******************/
+#define FLASH_OPTR_RDPROT_Pos (0U)
+#define FLASH_OPTR_RDPROT_Msk (0xFFUL << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
+#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
+#define FLASH_OPTR_WPRMOD_Pos (8U)
+#define FLASH_OPTR_WPRMOD_Msk (0x1UL << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
+#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
+#define FLASH_OPTR_BOR_LEV_Pos (16U)
+#define FLASH_OPTR_BOR_LEV_Msk (0xFUL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
+#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OPTR_IWDG_SW_Pos (20U)
+#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
+#define FLASH_OPTR_nRST_STOP_Pos (21U)
+#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OPTR_nRST_STDBY_Pos (22U)
+#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OPTR_BFB2_Pos (23U)
+#define FLASH_OPTR_BFB2_Msk (0x1UL << FLASH_OPTR_BFB2_Pos) /*!< 0x00800000 */
+#define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk /*!< BFB2 */
+#define FLASH_OPTR_USER_Pos (20U)
+#define FLASH_OPTR_USER_Msk (0x7UL << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
+#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OPTR_BOOT1_Pos (31U)
+#define FLASH_OPTR_BOOT1_Msk (0x1UL << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
+#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 (0x00000001U)
+#define GPIO_OTYPER_OT_1 (0x00000002U)
+#define GPIO_OTYPER_OT_2 (0x00000004U)
+#define GPIO_OTYPER_OT_3 (0x00000008U)
+#define GPIO_OTYPER_OT_4 (0x00000010U)
+#define GPIO_OTYPER_OT_5 (0x00000020U)
+#define GPIO_OTYPER_OT_6 (0x00000040U)
+#define GPIO_OTYPER_OT_7 (0x00000080U)
+#define GPIO_OTYPER_OT_8 (0x00000100U)
+#define GPIO_OTYPER_OT_9 (0x00000200U)
+#define GPIO_OTYPER_OT_10 (0x00000400U)
+#define GPIO_OTYPER_OT_11 (0x00000800U)
+#define GPIO_OTYPER_OT_12 (0x00001000U)
+#define GPIO_OTYPER_OT_13 (0x00002000U)
+#define GPIO_OTYPER_OT_14 (0x00004000U)
+#define GPIO_OTYPER_OT_15 (0x00008000U)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDER_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
+#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDER_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
+#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDER_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
+#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDER_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
+#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDER_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
+#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDER_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
+#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDER_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
+#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDER_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
+#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDER_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
+#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDER_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
+#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDER_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
+#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDER_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
+#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDER_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
+#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDER_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
+#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDER_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
+#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDER_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
+#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 (0x00000001U)
+#define GPIO_BSRR_BS_1 (0x00000002U)
+#define GPIO_BSRR_BS_2 (0x00000004U)
+#define GPIO_BSRR_BS_3 (0x00000008U)
+#define GPIO_BSRR_BS_4 (0x00000010U)
+#define GPIO_BSRR_BS_5 (0x00000020U)
+#define GPIO_BSRR_BS_6 (0x00000040U)
+#define GPIO_BSRR_BS_7 (0x00000080U)
+#define GPIO_BSRR_BS_8 (0x00000100U)
+#define GPIO_BSRR_BS_9 (0x00000200U)
+#define GPIO_BSRR_BS_10 (0x00000400U)
+#define GPIO_BSRR_BS_11 (0x00000800U)
+#define GPIO_BSRR_BS_12 (0x00001000U)
+#define GPIO_BSRR_BS_13 (0x00002000U)
+#define GPIO_BSRR_BS_14 (0x00004000U)
+#define GPIO_BSRR_BS_15 (0x00008000U)
+#define GPIO_BSRR_BR_0 (0x00010000U)
+#define GPIO_BSRR_BR_1 (0x00020000U)
+#define GPIO_BSRR_BR_2 (0x00040000U)
+#define GPIO_BSRR_BR_3 (0x00080000U)
+#define GPIO_BSRR_BR_4 (0x00100000U)
+#define GPIO_BSRR_BR_5 (0x00200000U)
+#define GPIO_BSRR_BR_6 (0x00400000U)
+#define GPIO_BSRR_BR_7 (0x00800000U)
+#define GPIO_BSRR_BR_8 (0x01000000U)
+#define GPIO_BSRR_BR_9 (0x02000000U)
+#define GPIO_BSRR_BR_10 (0x04000000U)
+#define GPIO_BSRR_BR_11 (0x08000000U)
+#define GPIO_BSRR_BR_12 (0x10000000U)
+#define GPIO_BSRR_BR_13 (0x20000000U)
+#define GPIO_BSRR_BR_14 (0x40000000U)
+#define GPIO_BSRR_BR_15 (0x80000000U)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 (0x00000001U)
+#define GPIO_BRR_BR_1 (0x00000002U)
+#define GPIO_BRR_BR_2 (0x00000004U)
+#define GPIO_BRR_BR_3 (0x00000008U)
+#define GPIO_BRR_BR_4 (0x00000010U)
+#define GPIO_BRR_BR_5 (0x00000020U)
+#define GPIO_BRR_BR_6 (0x00000040U)
+#define GPIO_BRR_BR_7 (0x00000080U)
+#define GPIO_BRR_BR_8 (0x00000100U)
+#define GPIO_BRR_BR_9 (0x00000200U)
+#define GPIO_BRR_BR_10 (0x00000400U)
+#define GPIO_BRR_BR_11 (0x00000800U)
+#define GPIO_BRR_BR_12 (0x00001000U)
+#define GPIO_BRR_BR_13 (0x00002000U)
+#define GPIO_BRR_BR_14 (0x00004000U)
+#define GPIO_BRR_BR_15 (0x00008000U)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos (1U)
+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos (2U)
+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos (3U)
+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos (4U)
+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos (5U)
+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos (6U)
+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos (7U)
+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos (8U)
+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos (12U)
+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos (14U)
+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos (15U)
+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos (16U)
+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos (17U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos (18U)
+#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos (19U)
+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos (20U)
+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos (21U)
+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos (22U)
+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos (23U)
+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD_Pos (0U)
+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos (10U)
+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos (11U)
+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos (12U)
+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos (13U)
+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
+#define I2C_CR2_STOP_Pos (14U)
+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos (15U)
+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos (16U)
+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos (24U)
+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos (25U)
+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos (26U)
+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1_Pos (0U)
+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos (10U)
+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos (15U)
+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2_Pos (1U)
+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos (8U)
+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos (8U)
+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos (9U)
+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos (8U)
+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos (10U)
+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos (8U)
+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos (9U)
+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos (8U)
+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos (15U)
+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos (0U)
+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos (8U)
+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos (16U)
+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos (20U)
+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos (28U)
+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE_Pos (0U)
+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos (1U)
+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos (2U)
+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos (3U)
+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos (4U)
+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos (5U)
+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos (6U)
+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos (7U)
+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos (8U)
+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
+#define I2C_ISR_ARLO_Pos (9U)
+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos (10U)
+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos (11U)
+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos (12U)
+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos (13U)
+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos (15U)
+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
+#define I2C_ISR_DIR_Pos (16U)
+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos (17U)
+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF_Pos (3U)
+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos (4U)
+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos (5U)
+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos (8U)
+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos (9U)
+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos (10U)
+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos (11U)
+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos (12U)
+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos (13U)
+#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define I2C_PECR_PEC_Pos (0U)
+#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA_Pos (0U)
+#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA_Pos (0U)
+#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos (2U)
+#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN_Pos (0U)
+#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM_Pos (0U)
+#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos (1U)
+#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos (2U)
+#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos (3U)
+#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos (4U)
+#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos (5U)
+#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos (6U)
+#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF_Pos (0U)
+#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos (1U)
+#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos (3U)
+#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos (4U)
+#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos (5U)
+#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos (6U)
+#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos (0U)
+#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos (1U)
+#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos (3U)
+#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos (4U)
+#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos (5U)
+#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos (6U)
+#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos (0U)
+#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos (1U)
+#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos (3U)
+#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos (6U)
+#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos (9U)
+#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos (17U)
+#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos (19U)
+#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos (20U)
+#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos (21U)
+#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos (22U)
+#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos (24U)
+#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE_Pos (0U)
+#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos (1U)
+#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos (2U)
+#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP_Pos (0U)
+#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR_Pos (0U)
+#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT_Pos (0U)
+#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
+
+/******************************************************************************/
+/* */
+/* MIFARE Firewall */
+/* */
+/******************************************************************************/
+
+/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
+#define FW_CSSA_ADD_Pos (8U)
+#define FW_CSSA_ADD_Msk (0xFFFFUL << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
+#define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
+#define FW_CSL_LENG_Pos (8U)
+#define FW_CSL_LENG_Msk (0x3FFFUL << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
+#define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
+#define FW_NVDSSA_ADD_Pos (8U)
+#define FW_NVDSSA_ADD_Msk (0xFFFFUL << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
+#define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
+#define FW_NVDSL_LENG_Pos (8U)
+#define FW_NVDSL_LENG_Msk (0x3FFFUL << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
+#define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
+#define FW_VDSSA_ADD_Pos (6U)
+#define FW_VDSSA_ADD_Msk (0x3FFUL << FW_VDSSA_ADD_Pos) /*!< 0x0000FFC0 */
+#define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
+#define FW_VDSL_LENG_Pos (6U)
+#define FW_VDSL_LENG_Msk (0x3FFUL << FW_VDSL_LENG_Pos) /*!< 0x0000FFC0 */
+#define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
+
+/**************************Bit definition for CR register *********************/
+#define FW_CR_FPA_Pos (0U)
+#define FW_CR_FPA_Msk (0x1UL << FW_CR_FPA_Pos) /*!< 0x00000001 */
+#define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
+#define FW_CR_VDS_Pos (1U)
+#define FW_CR_VDS_Msk (0x1UL << FW_CR_VDS_Pos) /*!< 0x00000002 */
+#define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
+#define FW_CR_VDE_Pos (2U)
+#define FW_CR_VDE_Msk (0x1UL << FW_CR_VDE_Pos) /*!< 0x00000004 */
+#define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
+
+/******************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/******************************************************************************/
+
+#define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPSDSR_Pos (0U)
+#define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP_Pos (9U)
+#define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /*!< 0x00000200 */
+#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
+#define PWR_CR_FWU_Pos (10U)
+#define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /*!< 0x00000400 */
+#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
+
+#define PWR_CR_VOS_Pos (11U)
+#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x00001800 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /*!< 0x00000800 */
+#define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /*!< 0x00001000 */
+#define PWR_CR_DSEEKOFF_Pos (13U)
+#define PWR_CR_DSEEKOFF_Msk (0x1UL << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */
+#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */
+#define PWR_CR_LPRUN_Pos (14U)
+#define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
+#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF_Pos (3U)
+#define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
+#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF_Pos (4U)
+#define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
+#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF_Pos (5U)
+#define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
+#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1_Pos (8U)
+#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2_Pos (9U)
+#define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
+#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP3_Pos (10U)
+#define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
+#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+#define RCC_HSI48_SUPPORT /*!< HSI48 feature support */
+#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos (1U)
+#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos (2U)
+#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIVEN_Pos (3U)
+#define RCC_CR_HSIDIVEN_Msk (0x1UL << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */
+#define RCC_CR_HSIDIVF_Pos (4U)
+#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */
+#define RCC_CR_HSIOUTEN_Pos (5U)
+#define RCC_CR_HSIOUTEN_Msk (0x1UL << RCC_CR_HSIOUTEN_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_Msk /*!< Internal High Speed clock out enable */
+#define RCC_CR_MSION_Pos (8U)
+#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000100 */
+#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY_Pos (9U)
+#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
+#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON_Pos (19U)
+#define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */
+#define RCC_CR_RTCPRE_Pos (20U)
+#define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
+#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */
+#define RCC_CR_RTCPRE_0 (0x1UL << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */
+#define RCC_CR_RTCPRE_1 (0x2UL << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+/* Reference defines */
+#define RCC_CR_CSSON RCC_CR_CSSHSEON
+
+/******************** Bit definition for RCC_ICSCR register *****************/
+#define RCC_ICSCR_HSICAL_Pos (0U)
+#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
+#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM_Pos (8U)
+#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
+#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE_Pos (13U)
+#define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
+#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
+#define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
+#define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
+#define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
+#define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
+#define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
+#define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
+#define RCC_ICSCR_MSICAL_Pos (16U)
+#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
+#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM_Pos (24U)
+#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
+#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
+
+/******************** Bit definition for RCC_CRRCR register *****************/
+#define RCC_CRRCR_HSI48ON_Pos (0U)
+#define RCC_CRRCR_HSI48ON_Msk (0x1UL << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
+#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk /*!< HSI 48MHz clock enable */
+#define RCC_CRRCR_HSI48RDY_Pos (1U)
+#define RCC_CRRCR_HSI48RDY_Msk (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
+#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk /*!< HSI 48MHz clock ready flag */
+#define RCC_CRRCR_HSI48DIV6OUTEN_Pos (2U)
+#define RCC_CRRCR_HSI48DIV6OUTEN_Msk (0x1UL << RCC_CRRCR_HSI48DIV6OUTEN_Pos) /*!< 0x00000004 */
+#define RCC_CRRCR_HSI48DIV6OUTEN RCC_CRRCR_HSI48DIV6OUTEN_Msk /*!< HSI 48MHz DIV6 out enable */
+#define RCC_CRRCR_HSI48CAL_Pos (8U)
+#define RCC_CRRCR_HSI48CAL_Msk (0xFFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI 48MHz clock Calibration */
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos (15U)
+#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */
+
+/*!< PLL entry clock source*/
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
+
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL_Pos (18U)
+#define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV_Pos (22U)
+#define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
+
+#define RCC_CFGR_PLLDIV2_Pos (22U)
+#define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3_Pos (23U)
+#define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4_Pos (22U)
+#define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCOSEL_Pos (24U)
+#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
+#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
+
+#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
+#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCOSEL_HSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_MSI_Pos (24U)
+#define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
+#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_HSE_Pos (26U)
+#define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCOSEL_PLL_Pos (24U)
+#define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
+#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
+#define RCC_CFGR_MCOSEL_LSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
+#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
+#define RCC_CFGR_MCOSEL_LSE_Pos (24U)
+#define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
+#define RCC_CFGR_MCOSEL_HSI48_Pos (27U)
+#define RCC_CFGR_MCOSEL_HSI48_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */
+#define RCC_CFGR_MCOSEL_HSI48 RCC_CFGR_MCOSEL_HSI48_Msk /*!< HSI48 clock selected as MCO source */
+
+#define RCC_CFGR_MCOPRE_Pos (28U)
+#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
+
+#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
+
+/* Legacy defines */
+#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
+#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
+#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
+#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
+#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
+#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
+#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
+#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
+#ifdef RCC_CFGR_MCOSEL_HSI48
+#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48
+#endif
+
+#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
+#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
+
+/*!<****************** Bit definition for RCC_CIER register ********************/
+#define RCC_CIER_LSIRDYIE_Pos (0U)
+#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIER_LSERDYIE_Pos (1U)
+#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIER_HSIRDYIE_Pos (2U)
+#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIER_HSERDYIE_Pos (3U)
+#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIER_PLLRDYIE_Pos (4U)
+#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIER_MSIRDYIE_Pos (5U)
+#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
+#define RCC_CIER_HSI48RDYIE_Pos (6U)
+#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000040 */
+#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk /*!< HSI48 Ready Interrupt Enable */
+#define RCC_CIER_CSSLSE_Pos (7U)
+#define RCC_CIER_CSSLSE_Msk (0x1UL << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */
+
+/* Reference defines */
+#define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
+
+/*!<****************** Bit definition for RCC_CIFR register ********************/
+#define RCC_CIFR_LSIRDYF_Pos (0U)
+#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIFR_LSERDYF_Pos (1U)
+#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIFR_HSIRDYF_Pos (2U)
+#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIFR_HSERDYF_Pos (3U)
+#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIFR_PLLRDYF_Pos (4U)
+#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIFR_MSIRDYF_Pos (5U)
+#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
+#define RCC_CIFR_HSI48RDYF_Pos (6U)
+#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk /*!< HSI48 Ready Interrupt flag */
+#define RCC_CIFR_CSSLSEF_Pos (7U)
+#define RCC_CIFR_CSSLSEF_Msk (0x1UL << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */
+#define RCC_CIFR_CSSHSEF_Pos (8U)
+#define RCC_CIFR_CSSHSEF_Msk (0x1UL << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */
+#define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */
+
+/* Reference defines */
+#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
+#define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
+
+/*!<****************** Bit definition for RCC_CICR register ********************/
+#define RCC_CICR_LSIRDYC_Pos (0U)
+#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CICR_LSERDYC_Pos (1U)
+#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CICR_HSIRDYC_Pos (2U)
+#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CICR_HSERDYC_Pos (3U)
+#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CICR_PLLRDYC_Pos (4U)
+#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CICR_MSIRDYC_Pos (5U)
+#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
+#define RCC_CICR_HSI48RDYC_Pos (6U)
+#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000040 */
+#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk /*!< HSI48 Ready Interrupt Clear */
+#define RCC_CICR_CSSLSEC_Pos (7U)
+#define RCC_CICR_CSSLSEC_Msk (0x1UL << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */
+#define RCC_CICR_CSSHSEC_Pos (8U)
+#define RCC_CICR_CSSHSEC_Msk (0x1UL << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */
+#define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */
+
+/* Reference defines */
+#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
+#define RCC_CICR_CSSC RCC_CICR_CSSHSEC
+/***************** Bit definition for RCC_IOPRSTR register ******************/
+#define RCC_IOPRSTR_IOPARST_Pos (0U)
+#define RCC_IOPRSTR_IOPARST_Msk (0x1UL << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */
+#define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */
+#define RCC_IOPRSTR_IOPBRST_Pos (1U)
+#define RCC_IOPRSTR_IOPBRST_Msk (0x1UL << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */
+#define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */
+#define RCC_IOPRSTR_IOPCRST_Pos (2U)
+#define RCC_IOPRSTR_IOPCRST_Msk (0x1UL << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */
+#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */
+#define RCC_IOPRSTR_IOPDRST_Pos (3U)
+#define RCC_IOPRSTR_IOPDRST_Msk (0x1UL << RCC_IOPRSTR_IOPDRST_Pos) /*!< 0x00000008 */
+#define RCC_IOPRSTR_IOPDRST RCC_IOPRSTR_IOPDRST_Msk /*!< GPIO port D reset */
+#define RCC_IOPRSTR_IOPERST_Pos (4U)
+#define RCC_IOPRSTR_IOPERST_Msk (0x1UL << RCC_IOPRSTR_IOPERST_Pos) /*!< 0x00000010 */
+#define RCC_IOPRSTR_IOPERST RCC_IOPRSTR_IOPERST_Msk /*!< GPIO port E reset */
+#define RCC_IOPRSTR_IOPHRST_Pos (7U)
+#define RCC_IOPRSTR_IOPHRST_Msk (0x1UL << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */
+#define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */
+
+/* Reference defines */
+#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
+#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
+#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
+#define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_IOPDRST /*!< GPIO port D reset */
+#define RCC_IOPRSTR_GPIOERST RCC_IOPRSTR_IOPERST /*!< GPIO port E reset */
+#define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
+
+
+/****************** Bit definition for RCC_AHBRST register ******************/
+#define RCC_AHBRSTR_DMARST_Pos (0U)
+#define RCC_AHBRSTR_DMARST_Msk (0x1UL << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */
+#define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */
+#define RCC_AHBRSTR_MIFRST_Pos (8U)
+#define RCC_AHBRSTR_MIFRST_Msk (0x1UL << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */
+#define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset */
+#define RCC_AHBRSTR_CRCRST_Pos (12U)
+#define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */
+#define RCC_AHBRSTR_TSCRST_Pos (16U)
+#define RCC_AHBRSTR_TSCRST_Msk (0x1UL << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x00010000 */
+#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TSC reset */
+#define RCC_AHBRSTR_RNGRST_Pos (20U)
+#define RCC_AHBRSTR_RNGRST_Msk (0x1UL << RCC_AHBRSTR_RNGRST_Pos) /*!< 0x00100000 */
+#define RCC_AHBRSTR_RNGRST RCC_AHBRSTR_RNGRST_Msk /*!< RNG reset */
+
+/* Reference defines */
+#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
+#define RCC_APB2RSTR_TIM21RST_Pos (2U)
+#define RCC_APB2RSTR_TIM21RST_Msk (0x1UL << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 reset */
+#define RCC_APB2RSTR_TIM22RST_Pos (5U)
+#define RCC_APB2RSTR_TIM22RST_Msk (0x1UL << RCC_APB2RSTR_TIM22RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk /*!< TIM22 reset */
+#define RCC_APB2RSTR_ADCRST_Pos (9U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
+#define RCC_APB2RSTR_DBGRST_Pos (22U)
+#define RCC_APB2RSTR_DBGRST_Msk (0x1UL << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU reset */
+
+/* Reference defines */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 reset */
+#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU reset */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
+#define RCC_APB1RSTR_TIM7RST_Pos (5U)
+#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_LPUART1RST_Pos (18U)
+#define RCC_APB1RSTR_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 reset */
+#define RCC_APB1RSTR_USART4RST_Pos (19U)
+#define RCC_APB1RSTR_USART4RST_Msk (0x1UL << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART4 reset */
+#define RCC_APB1RSTR_USART5RST_Pos (20U)
+#define RCC_APB1RSTR_USART5RST_Msk (0x1UL << RCC_APB1RSTR_USART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR_USART5RST RCC_APB1RSTR_USART5RST_Msk /*!< USART5 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
+#define RCC_APB1RSTR_USBRST_Pos (23U)
+#define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */
+#define RCC_APB1RSTR_CRSRST_Pos (27U)
+#define RCC_APB1RSTR_CRSRST_Msk (0x1UL << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
+#define RCC_APB1RSTR_DACRST_Pos (29U)
+#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC reset */
+#define RCC_APB1RSTR_I2C3RST_Pos (30U)
+#define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk /*!< I2C3 reset */
+#define RCC_APB1RSTR_LPTIM1RST_Pos (31U)
+#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 reset */
+
+/***************** Bit definition for RCC_IOPENR register ******************/
+#define RCC_IOPENR_IOPAEN_Pos (0U)
+#define RCC_IOPENR_IOPAEN_Msk (0x1UL << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */
+#define RCC_IOPENR_IOPBEN_Pos (1U)
+#define RCC_IOPENR_IOPBEN_Msk (0x1UL << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */
+#define RCC_IOPENR_IOPCEN_Pos (2U)
+#define RCC_IOPENR_IOPCEN_Msk (0x1UL << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */
+#define RCC_IOPENR_IOPDEN_Pos (3U)
+#define RCC_IOPENR_IOPDEN_Msk (0x1UL << RCC_IOPENR_IOPDEN_Pos) /*!< 0x00000008 */
+#define RCC_IOPENR_IOPDEN RCC_IOPENR_IOPDEN_Msk /*!< GPIO port D clock enable */
+#define RCC_IOPENR_IOPEEN_Pos (4U)
+#define RCC_IOPENR_IOPEEN_Msk (0x1UL << RCC_IOPENR_IOPEEN_Pos) /*!< 0x00000010 */
+#define RCC_IOPENR_IOPEEN RCC_IOPENR_IOPEEN_Msk /*!< GPIO port E clock enable */
+#define RCC_IOPENR_IOPHEN_Pos (7U)
+#define RCC_IOPENR_IOPHEN_Msk (0x1UL << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */
+
+/* Reference defines */
+#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
+#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
+#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
+#define RCC_IOPENR_GPIODEN RCC_IOPENR_IOPDEN /*!< GPIO port D clock enable */
+#define RCC_IOPENR_GPIOEEN RCC_IOPENR_IOPEEN /*!< GPIO port E clock enable */
+#define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
+
+/***************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMAEN_Pos (0U)
+#define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_MIFEN_Pos (8U)
+#define RCC_AHBENR_MIFEN_Msk (0x1UL << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */
+#define RCC_AHBENR_CRCEN_Pos (12U)
+#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+#define RCC_AHBENR_TSCEN_Pos (16U)
+#define RCC_AHBENR_TSCEN_Msk (0x1UL << RCC_AHBENR_TSCEN_Pos) /*!< 0x00010000 */
+#define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TSC clock enable */
+#define RCC_AHBENR_RNGEN_Pos (20U)
+#define RCC_AHBENR_RNGEN_Msk (0x1UL << RCC_AHBENR_RNGEN_Pos) /*!< 0x00100000 */
+#define RCC_AHBENR_RNGEN RCC_AHBENR_RNGEN_Msk /*!< RNG clock enable */
+
+/* Reference defines */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register ******************/
+#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM21EN_Pos (2U)
+#define RCC_APB2ENR_TIM21EN_Msk (0x1UL << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */
+#define RCC_APB2ENR_TIM22EN_Pos (5U)
+#define RCC_APB2ENR_TIM22EN_Msk (0x1UL << RCC_APB2ENR_TIM22EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk /*!< TIM22 clock enable */
+#define RCC_APB2ENR_FWEN_Pos (7U)
+#define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADCEN_Pos (9U)
+#define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
+#define RCC_APB2ENR_DBGEN_Pos (22U)
+#define RCC_APB2ENR_DBGEN_Msk (0x1UL << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */
+
+/* Reference defines */
+
+#define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN_Pos (5U)
+#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
+#define RCC_APB1ENR_LPUART1EN_Pos (18U)
+#define RCC_APB1ENR_LPUART1EN_Msk (0x1UL << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */
+#define RCC_APB1ENR_USART4EN_Pos (19U)
+#define RCC_APB1ENR_USART4EN_Msk (0x1UL << RCC_APB1ENR_USART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR_USART4EN RCC_APB1ENR_USART4EN_Msk /*!< USART4 clock enable */
+#define RCC_APB1ENR_USART5EN_Pos (20U)
+#define RCC_APB1ENR_USART5EN_Msk (0x1UL << RCC_APB1ENR_USART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR_USART5EN RCC_APB1ENR_USART5EN_Msk /*!< USART5 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */
+#define RCC_APB1ENR_USBEN_Pos (23U)
+#define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */
+#define RCC_APB1ENR_CRSEN_Pos (27U)
+#define RCC_APB1ENR_CRSEN_Msk (0x1UL << RCC_APB1ENR_CRSEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
+#define RCC_APB1ENR_DACEN_Pos (29U)
+#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC clock enable */
+#define RCC_APB1ENR_I2C3EN_Pos (30U)
+#define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk /*!< I2C3 clock enable */
+#define RCC_APB1ENR_LPTIM1EN_Pos (31U)
+#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */
+
+/****************** Bit definition for RCC_IOPSMENR register ****************/
+#define RCC_IOPSMENR_IOPASMEN_Pos (0U)
+#define RCC_IOPSMENR_IOPASMEN_Msk (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPBSMEN_Pos (1U)
+#define RCC_IOPSMENR_IOPBSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPCSMEN_Pos (2U)
+#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPDSMEN_Pos (3U)
+#define RCC_IOPSMENR_IOPDSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos) /*!< 0x00000008 */
+#define RCC_IOPSMENR_IOPDSMEN RCC_IOPSMENR_IOPDSMEN_Msk /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPESMEN_Pos (4U)
+#define RCC_IOPSMENR_IOPESMEN_Msk (0x1UL << RCC_IOPSMENR_IOPESMEN_Pos) /*!< 0x00000010 */
+#define RCC_IOPSMENR_IOPESMEN RCC_IOPSMENR_IOPESMEN_Msk /*!< GPIO port E clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPHSMEN_Pos (7U)
+#define RCC_IOPSMENR_IOPHSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_IOPDSMEN /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOESMEN RCC_IOPSMENR_IOPESMEN /*!< GPIO port E clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_AHBSMENR register ******************/
+#define RCC_AHBSMENR_DMASMEN_Pos (0U)
+#define RCC_AHBSMENR_DMASMEN_Msk (0x1UL << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */
+#define RCC_AHBSMENR_MIFSMEN_Pos (8U)
+#define RCC_AHBSMENR_MIFSMEN_Msk (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */
+#define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
+#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRCSMEN_Pos (12U)
+#define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */
+#define RCC_AHBSMENR_TSCSMEN_Pos (16U)
+#define RCC_AHBSMENR_TSCSMEN_Msk (0x1UL << RCC_AHBSMENR_TSCSMEN_Pos) /*!< 0x00010000 */
+#define RCC_AHBSMENR_TSCSMEN RCC_AHBSMENR_TSCSMEN_Msk /*!< TSC clock enabled in sleep mode */
+#define RCC_AHBSMENR_RNGSMEN_Pos (20U)
+#define RCC_AHBSMENR_RNGSMEN_Msk (0x1UL << RCC_AHBSMENR_RNGSMEN_Pos) /*!< 0x00100000 */
+#define RCC_AHBSMENR_RNGSMEN RCC_AHBSMENR_RNGSMEN_Msk /*!< RNG clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB2SMENR register ******************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM21SMEN_Pos (2U)
+#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM22SMEN_Pos (5U)
+#define RCC_APB2SMENR_TIM22SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk /*!< TIM22 clock enabled in sleep mode */
+#define RCC_APB2SMENR_ADCSMEN_Pos (9U)
+#define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
+#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
+#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk /*!< USART1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGSMEN_Pos (22U)
+#define RCC_APB2SMENR_DBGSMEN_Msk (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB1SMENR register ******************/
+#define RCC_APB1SMENR_TIM2SMEN_Pos (0U)
+#define RCC_APB1SMENR_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_TIM3SMEN_Pos (1U)
+#define RCC_APB1SMENR_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM3SMEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1SMENR_TIM3SMEN RCC_APB1SMENR_TIM3SMEN_Msk /*!< Timer 3 clock enabled in sleep mode */
+#define RCC_APB1SMENR_TIM6SMEN_Pos (4U)
+#define RCC_APB1SMENR_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM6SMEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1SMENR_TIM6SMEN RCC_APB1SMENR_TIM6SMEN_Msk /*!< Timer 6 clock enabled in sleep mode */
+#define RCC_APB1SMENR_TIM7SMEN_Pos (5U)
+#define RCC_APB1SMENR_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM7SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1SMENR_TIM7SMEN RCC_APB1SMENR_TIM7SMEN_Msk /*!< Timer 7 clock enabled in sleep mode */
+#define RCC_APB1SMENR_WWDGSMEN_Pos (11U)
+#define RCC_APB1SMENR_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */
+#define RCC_APB1SMENR_SPI2SMEN_Pos (14U)
+#define RCC_APB1SMENR_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR_SPI2SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1SMENR_SPI2SMEN RCC_APB1SMENR_SPI2SMEN_Msk /*!< SPI2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART2SMEN_Pos (17U)
+#define RCC_APB1SMENR_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPUART1SMEN_Pos (18U)
+#define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART4SMEN_Pos (19U)
+#define RCC_APB1SMENR_USART4SMEN_Msk (0x1UL << RCC_APB1SMENR_USART4SMEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1SMENR_USART4SMEN RCC_APB1SMENR_USART4SMEN_Msk /*!< USART4 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART5SMEN_Pos (20U)
+#define RCC_APB1SMENR_USART5SMEN_Msk (0x1UL << RCC_APB1SMENR_USART5SMEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1SMENR_USART5SMEN RCC_APB1SMENR_USART5SMEN_Msk /*!< USART5 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C1SMEN_Pos (21U)
+#define RCC_APB1SMENR_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C2SMEN_Pos (22U)
+#define RCC_APB1SMENR_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1SMENR_I2C2SMEN RCC_APB1SMENR_I2C2SMEN_Msk /*!< I2C2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USBSMEN_Pos (23U)
+#define RCC_APB1SMENR_USBSMEN_Msk (0x1UL << RCC_APB1SMENR_USBSMEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1SMENR_USBSMEN RCC_APB1SMENR_USBSMEN_Msk /*!< USB clock enabled in sleep mode */
+#define RCC_APB1SMENR_CRSSMEN_Pos (27U)
+#define RCC_APB1SMENR_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR_CRSSMEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1SMENR_CRSSMEN RCC_APB1SMENR_CRSSMEN_Msk /*!< CRS clock enabled in sleep mode */
+#define RCC_APB1SMENR_PWRSMEN_Pos (28U)
+#define RCC_APB1SMENR_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */
+#define RCC_APB1SMENR_DACSMEN_Pos (29U)
+#define RCC_APB1SMENR_DACSMEN_Msk (0x1UL << RCC_APB1SMENR_DACSMEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1SMENR_DACSMEN RCC_APB1SMENR_DACSMEN_Msk /*!< DAC clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C3SMEN_Pos (30U)
+#define RCC_APB1SMENR_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C3SMEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1SMENR_I2C3SMEN RCC_APB1SMENR_I2C3SMEN_Msk /*!< I2C3 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U)
+#define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */
+
+/******************* Bit definition for RCC_CCIPR register *******************/
+/*!< USART1 Clock source selection */
+#define RCC_CCIPR_USART1SEL_Pos (0U)
+#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
+#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk /*!< USART1SEL[1:0] bits */
+#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
+
+/*!< USART2 Clock source selection */
+#define RCC_CCIPR_USART2SEL_Pos (2U)
+#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */
+#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+/*!< LPUART1 Clock source selection */
+#define RCC_CCIPR_LPUART1SEL_Pos (10U)
+#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */
+#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */
+#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CCIPR_I2C1SEL_Pos (12U)
+#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */
+#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
+
+/*!< I2C3 Clock source selection */
+#define RCC_CCIPR_I2C3SEL_Pos (16U)
+#define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
+#define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk /*!< I2C3SEL [1:0] bits */
+#define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
+#define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
+
+/*!< LPTIM1 Clock source selection */
+#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
+#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */
+#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+/*!< HSI48 Clock source selection */
+#define RCC_CCIPR_HSI48SEL_Pos (26U)
+#define RCC_CCIPR_HSI48SEL_Msk (0x1UL << RCC_CCIPR_HSI48SEL_Pos) /*!< 0x04000000 */
+#define RCC_CCIPR_HSI48SEL RCC_CCIPR_HSI48SEL_Msk /*!< HSI48 RC clock source selection bit for USB and RNG*/
+
+/* Legacy defines */
+#define RCC_CCIPR_HSI48MSEL RCC_CCIPR_HSI48SEL
+
+/******************* Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSEON_Pos (8U)
+#define RCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */
+#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_CSR_LSERDY_Pos (9U)
+#define RCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */
+#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP_Pos (10U)
+#define RCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */
+#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_CSR_LSEDRV_Pos (11U)
+#define RCC_CSR_LSEDRV_Msk (0x3UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */
+#define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_CSR_LSEDRV_0 (0x1UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */
+#define RCC_CSR_LSEDRV_1 (0x2UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */
+
+#define RCC_CSR_LSECSSON_Pos (13U)
+#define RCC_CSR_LSECSSON_Msk (0x1UL << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */
+#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */
+#define RCC_CSR_LSECSSD_Pos (14U)
+#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
+#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
+
+/*!< RTC congiguration */
+#define RCC_CSR_RTCSEL_Pos (16U)
+#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
+
+#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CSR_RTCSEL_LSE_Pos (16U)
+#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_LSI_Pos (17U)
+#define RCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */
+#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_HSE_Pos (16U)
+#define RCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */
+
+#define RCC_CSR_RTCEN_Pos (18U)
+#define RCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */
+#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_CSR_RTCRST_Pos (19U)
+#define RCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */
+#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */
+
+#define RCC_CSR_RMVF_Pos (23U)
+#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_FWRSTF_Pos (24U)
+#define RCC_CSR_FWRSTF_Msk (0x1UL << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk /*!< Mifare Firewall reset flag */
+#define RCC_CSR_OBLRSTF_Pos (25U)
+#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+/* Reference defines */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN_Pos (2U)
+#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
+#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos (3U)
+#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
+#define RNG_CR_IE RNG_CR_IE_Msk
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY_Pos (0U)
+#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
+#define RNG_SR_DRDY RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos (1U)
+#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
+#define RNG_SR_CECS RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos (2U)
+#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
+#define RNG_SR_SECS RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos (5U)
+#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
+#define RNG_SR_CEIS RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos (6U)
+#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
+#define RNG_SR_SEIS RNG_SR_SEIS_Msk
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER1_SUPPORT
+#define RTC_TAMPER2_SUPPORT
+#define RTC_TAMPER3_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk /*!< */
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk /*!< */
+#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk /*!< */
+#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */
+#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */
+#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk /*!< */
+#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk /*!< */
+#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk /*!< */
+#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk /*!< */
+#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */
+#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk /*!< */
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk /*!< */
+#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk /*!< */
+#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk /*!< */
+#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk /*!< */
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */
+#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk /*!< */
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< */
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */
+#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */
+#define RTC_ISR_TAMP3F_Pos (15U)
+#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk /*!< */
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */
+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */
+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */
+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */
+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */
+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */
+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */
+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */
+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */
+#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */
+#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */
+#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */
+#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */
+#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */
+#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */
+#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */
+#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */
+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */
+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */
+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */
+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */
+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */
+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */
+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */
+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */
+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */
+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CALR register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */
+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define RTC_CAL_CALP RTC_CALR_CALP
+#define RTC_CAL_CALW8 RTC_CALR_CALW8
+#define RTC_CAL_CALW16 RTC_CALR_CALW16
+#define RTC_CAL_CALM RTC_CALR_CALM
+#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
+
+/******************** Bits definition for RTC_TAMPCR register ****************/
+#define RTC_TAMPCR_TAMP3MF_Pos (24U)
+#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
+#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
+#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
+#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP3IE_Pos (22U)
+#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
+#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2MF_Pos (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2IE_Pos (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1MF_Pos (18U)
+#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
+#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1IE_Pos (16U)
+#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */
+#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */
+#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */
+#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos (7U)
+#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */
+#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
+#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
+#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP3E_Pos (5U)
+#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
+#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk /*!< */
+#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP2E_Pos (3U)
+#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */
+#define RTC_TAMPCR_TAMPIE_Pos (2U)
+#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
+#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP1E_Pos (0U)
+#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_OR register ****************/
+#define RTC_OR_OUT_RMP_Pos (1U)
+#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */
+#define RTC_OR_ALARMOUTTYPE_Pos (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */
+
+/* Legacy defines */
+#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk /*!< */
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER (0x00000005U) /*!< */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+#define SPI_I2S_SUPPORT /*!< I2S support */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
+#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
+#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
+#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR1_UFB_Pos (3U)
+#define SYSCFG_CFGR1_UFB_Msk (0x1UL << SYSCFG_CFGR1_UFB_Pos) /*!< 0x00000008 */
+#define SYSCFG_CFGR1_UFB SYSCFG_CFGR1_UFB_Msk /*!< User bank swapping */
+#define SYSCFG_CFGR1_BOOT_MODE_Pos (8U)
+#define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
+#define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */
+#define SYSCFG_CFGR1_BOOT_MODE_0 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOT_MODE_1 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_FWDISEN_Pos (0U)
+#define SYSCFG_CFGR2_FWDISEN_Msk (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos (8U)
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR2_I2C_PB6_FMP SYSCFG_CFGR2_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos (9U)
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR2_I2C_PB7_FMP SYSCFG_CFGR2_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos (10U)
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
+#define SYSCFG_CFGR2_I2C_PB8_FMP SYSCFG_CFGR2_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos (11U)
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
+#define SYSCFG_CFGR2_I2C_PB9_FMP SYSCFG_CFGR2_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR2_I2C1_FMP_Pos (12U)
+#define SYSCFG_CFGR2_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR2_I2C1_FMP SYSCFG_CFGR2_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR2_I2C2_FMP_Pos (13U)
+#define SYSCFG_CFGR2_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
+#define SYSCFG_CFGR2_I2C2_FMP SYSCFG_CFGR2_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
+#define SYSCFG_CFGR2_I2C3_FMP_Pos (14U)
+#define SYSCFG_CFGR2_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C3_FMP_Pos) /*!< 0x00004000 */
+#define SYSCFG_CFGR2_I2C3_FMP SYSCFG_CFGR2_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH (0x00000050U) /*!< PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH (0x00000500U) /*!< PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
+
+
+/***************** Bit definition for SYSCFG_CFGR3 register ****************/
+#define SYSCFG_CFGR3_EN_VREFINT_Pos (0U)
+#define SYSCFG_CFGR3_EN_VREFINT_Msk (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_EN_VREFINT SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
+#define SYSCFG_CFGR3_VREF_OUT_Pos (4U)
+#define SYSCFG_CFGR3_VREF_OUT_Msk (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
+#define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */
+#define SYSCFG_CFGR3_VREF_OUT_0 (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
+#define SYSCFG_CFGR3_VREF_OUT_1 (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U)
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U)
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U)
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
+#define SYSCFG_CFGR3_ENREF_HSI48_Pos (13U)
+#define SYSCFG_CFGR3_ENREF_HSI48_Msk (0x1UL << SYSCFG_CFGR3_ENREF_HSI48_Pos) /*!< 0x00002000 */
+#define SYSCFG_CFGR3_ENREF_HSI48 SYSCFG_CFGR3_ENREF_HSI48_Msk /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
+#define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U)
+#define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
+#define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
+#define SYSCFG_CFGR3_REF_LOCK_Pos (31U)
+#define SYSCFG_CFGR3_REF_LOCK_Msk (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
+#define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */
+
+/* Legacy defines */
+
+#define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
+#define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
+#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
+#define SYSCFG_CFGR3_ENREF_RC48MHz SYSCFG_CFGR3_ENREF_HSI48
+#define SYSCFG_CFGR3_REF_RC48MHz_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_REF_HSI48_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+
+/******************************************************************************/
+/* */
+/* Timers (TIM)*/
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
+#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
+ || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#else
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#endif
+
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFUL << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFUL << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM2_OR_ETR_RMP_Pos (0U)
+#define TIM2_OR_ETR_RMP_Msk (0x7UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000007 */
+#define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
+#define TIM2_OR_ETR_RMP_0 (0x1UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM2_OR_ETR_RMP_1 (0x2UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM2_OR_ETR_RMP_2 (0x4UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000004 */
+#define TIM2_OR_TI4_RMP_Pos (3U)
+#define TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000018 */
+#define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
+#define TIM2_OR_TI4_RMP_0 (0x1UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */
+#define TIM2_OR_TI4_RMP_1 (0x2UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000010 */
+
+#define TIM21_OR_ETR_RMP_Pos (0U)
+#define TIM21_OR_ETR_RMP_Msk (0x3UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
+#define TIM21_OR_ETR_RMP_0 (0x1UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM21_OR_ETR_RMP_1 (0x2UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM21_OR_TI1_RMP_Pos (2U)
+#define TIM21_OR_TI1_RMP_Msk (0x7UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x0000001C */
+#define TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
+#define TIM21_OR_TI1_RMP_0 (0x1UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM21_OR_TI1_RMP_1 (0x2UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+#define TIM21_OR_TI1_RMP_2 (0x4UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000010 */
+#define TIM21_OR_TI2_RMP_Pos (5U)
+#define TIM21_OR_TI2_RMP_Msk (0x1UL << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */
+#define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */
+
+#define TIM22_OR_ETR_RMP_Pos (0U)
+#define TIM22_OR_ETR_RMP_Msk (0x3UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM22_OR_ETR_RMP TIM22_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
+#define TIM22_OR_ETR_RMP_0 (0x1UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM22_OR_ETR_RMP_1 (0x2UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM22_OR_TI1_RMP_Pos (2U)
+#define TIM22_OR_TI1_RMP_Msk (0x3UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x0000000C */
+#define TIM22_OR_TI1_RMP TIM22_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
+#define TIM22_OR_TI1_RMP_0 (0x1UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM22_OR_TI1_RMP_1 (0x2UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+
+#define TIM3_OR_ETR_RMP_Pos (0U)
+#define TIM3_OR_ETR_RMP_Msk (0x3UL << TIM3_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM3_OR_ETR_RMP TIM3_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM3 ETR remap) */
+#define TIM3_OR_ETR_RMP_0 (0x1UL << TIM3_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM3_OR_ETR_RMP_1 (0x2UL << TIM3_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM3_OR_TI1_RMP_Pos (2U)
+#define TIM3_OR_TI1_RMP_Msk (0x1UL << TIM3_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM3_OR_TI1_RMP TIM3_OR_TI1_RMP_Msk /*!<TI1_RMP[2] bit */
+#define TIM3_OR_TI2_RMP_Pos (3U)
+#define TIM3_OR_TI2_RMP_Msk (0x1UL << TIM3_OR_TI2_RMP_Pos) /*!< 0x00000008 */
+#define TIM3_OR_TI2_RMP TIM3_OR_TI2_RMP_Msk /*!<TI2_RMP[3] bit */
+#define TIM3_OR_TI4_RMP_Pos (4U)
+#define TIM3_OR_TI4_RMP_Msk (0x1UL << TIM3_OR_TI4_RMP_Pos) /*!< 0x00000010 */
+#define TIM3_OR_TI4_RMP TIM3_OR_TI4_RMP_Msk /*!<TI4_RMP[4] bit */
+
+
+/******************************************************************************/
+/* */
+/* Touch Sensing Controller (TSC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TSC_CR register *********************/
+#define TSC_CR_TSCE_Pos (0U)
+#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
+#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
+#define TSC_CR_START_Pos (1U)
+#define TSC_CR_START_Msk (0x1UL << TSC_CR_START_Pos) /*!< 0x00000002 */
+#define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
+#define TSC_CR_AM_Pos (2U)
+#define TSC_CR_AM_Msk (0x1UL << TSC_CR_AM_Pos) /*!< 0x00000004 */
+#define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL_Pos (3U)
+#define TSC_CR_SYNCPOL_Msk (0x1UL << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
+#define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF_Pos (4U)
+#define TSC_CR_IODEF_Msk (0x1UL << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
+#define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
+
+#define TSC_CR_MCV_Pos (5U)
+#define TSC_CR_MCV_Msk (0x7UL << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
+#define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0 (0x1UL << TSC_CR_MCV_Pos) /*!< 0x00000020 */
+#define TSC_CR_MCV_1 (0x2UL << TSC_CR_MCV_Pos) /*!< 0x00000040 */
+#define TSC_CR_MCV_2 (0x4UL << TSC_CR_MCV_Pos) /*!< 0x00000080 */
+
+#define TSC_CR_PGPSC_Pos (12U)
+#define TSC_CR_PGPSC_Msk (0x7UL << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
+#define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0 (0x1UL << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
+#define TSC_CR_PGPSC_1 (0x2UL << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
+#define TSC_CR_PGPSC_2 (0x4UL << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
+
+#define TSC_CR_SSPSC_Pos (15U)
+#define TSC_CR_SSPSC_Msk (0x1UL << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
+#define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE_Pos (16U)
+#define TSC_CR_SSE_Msk (0x1UL << TSC_CR_SSE_Pos) /*!< 0x00010000 */
+#define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD_Pos (17U)
+#define TSC_CR_SSD_Msk (0x7FUL << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
+#define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0 (0x01UL << TSC_CR_SSD_Pos) /*!< 0x00020000 */
+#define TSC_CR_SSD_1 (0x02UL << TSC_CR_SSD_Pos) /*!< 0x00040000 */
+#define TSC_CR_SSD_2 (0x04UL << TSC_CR_SSD_Pos) /*!< 0x00080000 */
+#define TSC_CR_SSD_3 (0x08UL << TSC_CR_SSD_Pos) /*!< 0x00100000 */
+#define TSC_CR_SSD_4 (0x10UL << TSC_CR_SSD_Pos) /*!< 0x00200000 */
+#define TSC_CR_SSD_5 (0x20UL << TSC_CR_SSD_Pos) /*!< 0x00400000 */
+#define TSC_CR_SSD_6 (0x40UL << TSC_CR_SSD_Pos) /*!< 0x00800000 */
+
+#define TSC_CR_CTPL_Pos (24U)
+#define TSC_CR_CTPL_Msk (0xFUL << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
+#define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0 (0x1UL << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
+#define TSC_CR_CTPL_1 (0x2UL << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
+#define TSC_CR_CTPL_2 (0x4UL << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
+#define TSC_CR_CTPL_3 (0x8UL << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
+
+#define TSC_CR_CTPH_Pos (28U)
+#define TSC_CR_CTPH_Msk (0xFUL << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
+#define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0 (0x1UL << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
+#define TSC_CR_CTPH_1 (0x2UL << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
+#define TSC_CR_CTPH_2 (0x4UL << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
+#define TSC_CR_CTPH_3 (0x8UL << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for TSC_IER register ********************/
+#define TSC_IER_EOAIE_Pos (0U)
+#define TSC_IER_EOAIE_Msk (0x1UL << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
+#define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE_Pos (1U)
+#define TSC_IER_MCEIE_Msk (0x1UL << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
+#define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
+
+/******************* Bit definition for TSC_ICR register ********************/
+#define TSC_ICR_EOAIC_Pos (0U)
+#define TSC_ICR_EOAIC_Msk (0x1UL << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
+#define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC_Pos (1U)
+#define TSC_ICR_MCEIC_Msk (0x1UL << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
+#define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
+
+/******************* Bit definition for TSC_ISR register ********************/
+#define TSC_ISR_EOAF_Pos (0U)
+#define TSC_ISR_EOAF_Msk (0x1UL << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
+#define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
+#define TSC_ISR_MCEF_Pos (1U)
+#define TSC_ISR_MCEF_Msk (0x1UL << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
+#define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
+
+/******************* Bit definition for TSC_IOHCR register ******************/
+#define TSC_IOHCR_G1_IO1_Pos (0U)
+#define TSC_IOHCR_G1_IO1_Msk (0x1UL << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2_Pos (1U)
+#define TSC_IOHCR_G1_IO2_Msk (0x1UL << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3_Pos (2U)
+#define TSC_IOHCR_G1_IO3_Msk (0x1UL << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4_Pos (3U)
+#define TSC_IOHCR_G1_IO4_Msk (0x1UL << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1_Pos (4U)
+#define TSC_IOHCR_G2_IO1_Msk (0x1UL << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2_Pos (5U)
+#define TSC_IOHCR_G2_IO2_Msk (0x1UL << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3_Pos (6U)
+#define TSC_IOHCR_G2_IO3_Msk (0x1UL << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4_Pos (7U)
+#define TSC_IOHCR_G2_IO4_Msk (0x1UL << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1_Pos (8U)
+#define TSC_IOHCR_G3_IO1_Msk (0x1UL << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2_Pos (9U)
+#define TSC_IOHCR_G3_IO2_Msk (0x1UL << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3_Pos (10U)
+#define TSC_IOHCR_G3_IO3_Msk (0x1UL << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4_Pos (11U)
+#define TSC_IOHCR_G3_IO4_Msk (0x1UL << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1_Pos (12U)
+#define TSC_IOHCR_G4_IO1_Msk (0x1UL << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2_Pos (13U)
+#define TSC_IOHCR_G4_IO2_Msk (0x1UL << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3_Pos (14U)
+#define TSC_IOHCR_G4_IO3_Msk (0x1UL << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4_Pos (15U)
+#define TSC_IOHCR_G4_IO4_Msk (0x1UL << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1_Pos (16U)
+#define TSC_IOHCR_G5_IO1_Msk (0x1UL << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2_Pos (17U)
+#define TSC_IOHCR_G5_IO2_Msk (0x1UL << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3_Pos (18U)
+#define TSC_IOHCR_G5_IO3_Msk (0x1UL << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4_Pos (19U)
+#define TSC_IOHCR_G5_IO4_Msk (0x1UL << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1_Pos (20U)
+#define TSC_IOHCR_G6_IO1_Msk (0x1UL << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2_Pos (21U)
+#define TSC_IOHCR_G6_IO2_Msk (0x1UL << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3_Pos (22U)
+#define TSC_IOHCR_G6_IO3_Msk (0x1UL << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4_Pos (23U)
+#define TSC_IOHCR_G6_IO4_Msk (0x1UL << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1_Pos (24U)
+#define TSC_IOHCR_G7_IO1_Msk (0x1UL << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2_Pos (25U)
+#define TSC_IOHCR_G7_IO2_Msk (0x1UL << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3_Pos (26U)
+#define TSC_IOHCR_G7_IO3_Msk (0x1UL << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4_Pos (27U)
+#define TSC_IOHCR_G7_IO4_Msk (0x1UL << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1_Pos (28U)
+#define TSC_IOHCR_G8_IO1_Msk (0x1UL << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2_Pos (29U)
+#define TSC_IOHCR_G8_IO2_Msk (0x1UL << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3_Pos (30U)
+#define TSC_IOHCR_G8_IO3_Msk (0x1UL << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4_Pos (31U)
+#define TSC_IOHCR_G8_IO4_Msk (0x1UL << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+
+/******************* Bit definition for TSC_IOASCR register *****************/
+#define TSC_IOASCR_G1_IO1_Pos (0U)
+#define TSC_IOASCR_G1_IO1_Msk (0x1UL << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2_Pos (1U)
+#define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3_Pos (2U)
+#define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4_Pos (3U)
+#define TSC_IOASCR_G1_IO4_Msk (0x1UL << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1_Pos (4U)
+#define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2_Pos (5U)
+#define TSC_IOASCR_G2_IO2_Msk (0x1UL << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3_Pos (6U)
+#define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4_Pos (7U)
+#define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1_Pos (8U)
+#define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2_Pos (9U)
+#define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3_Pos (10U)
+#define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4_Pos (11U)
+#define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1_Pos (12U)
+#define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2_Pos (13U)
+#define TSC_IOASCR_G4_IO2_Msk (0x1UL << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3_Pos (14U)
+#define TSC_IOASCR_G4_IO3_Msk (0x1UL << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4_Pos (15U)
+#define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1_Pos (16U)
+#define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2_Pos (17U)
+#define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3_Pos (18U)
+#define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4_Pos (19U)
+#define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1_Pos (20U)
+#define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2_Pos (21U)
+#define TSC_IOASCR_G6_IO2_Msk (0x1UL << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3_Pos (22U)
+#define TSC_IOASCR_G6_IO3_Msk (0x1UL << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4_Pos (23U)
+#define TSC_IOASCR_G6_IO4_Msk (0x1UL << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1_Pos (24U)
+#define TSC_IOASCR_G7_IO1_Msk (0x1UL << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2_Pos (25U)
+#define TSC_IOASCR_G7_IO2_Msk (0x1UL << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3_Pos (26U)
+#define TSC_IOASCR_G7_IO3_Msk (0x1UL << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4_Pos (27U)
+#define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1_Pos (28U)
+#define TSC_IOASCR_G8_IO1_Msk (0x1UL << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2_Pos (29U)
+#define TSC_IOASCR_G8_IO2_Msk (0x1UL << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3_Pos (30U)
+#define TSC_IOASCR_G8_IO3_Msk (0x1UL << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4_Pos (31U)
+#define TSC_IOASCR_G8_IO4_Msk (0x1UL << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */
+
+/******************* Bit definition for TSC_IOSCR register ******************/
+#define TSC_IOSCR_G1_IO1_Pos (0U)
+#define TSC_IOSCR_G1_IO1_Msk (0x1UL << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2_Pos (1U)
+#define TSC_IOSCR_G1_IO2_Msk (0x1UL << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3_Pos (2U)
+#define TSC_IOSCR_G1_IO3_Msk (0x1UL << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4_Pos (3U)
+#define TSC_IOSCR_G1_IO4_Msk (0x1UL << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1_Pos (4U)
+#define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2_Pos (5U)
+#define TSC_IOSCR_G2_IO2_Msk (0x1UL << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3_Pos (6U)
+#define TSC_IOSCR_G2_IO3_Msk (0x1UL << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4_Pos (7U)
+#define TSC_IOSCR_G2_IO4_Msk (0x1UL << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1_Pos (8U)
+#define TSC_IOSCR_G3_IO1_Msk (0x1UL << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2_Pos (9U)
+#define TSC_IOSCR_G3_IO2_Msk (0x1UL << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3_Pos (10U)
+#define TSC_IOSCR_G3_IO3_Msk (0x1UL << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4_Pos (11U)
+#define TSC_IOSCR_G3_IO4_Msk (0x1UL << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1_Pos (12U)
+#define TSC_IOSCR_G4_IO1_Msk (0x1UL << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2_Pos (13U)
+#define TSC_IOSCR_G4_IO2_Msk (0x1UL << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3_Pos (14U)
+#define TSC_IOSCR_G4_IO3_Msk (0x1UL << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4_Pos (15U)
+#define TSC_IOSCR_G4_IO4_Msk (0x1UL << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1_Pos (16U)
+#define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2_Pos (17U)
+#define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3_Pos (18U)
+#define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4_Pos (19U)
+#define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1_Pos (20U)
+#define TSC_IOSCR_G6_IO1_Msk (0x1UL << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2_Pos (21U)
+#define TSC_IOSCR_G6_IO2_Msk (0x1UL << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3_Pos (22U)
+#define TSC_IOSCR_G6_IO3_Msk (0x1UL << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4_Pos (23U)
+#define TSC_IOSCR_G6_IO4_Msk (0x1UL << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1_Pos (24U)
+#define TSC_IOSCR_G7_IO1_Msk (0x1UL << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2_Pos (25U)
+#define TSC_IOSCR_G7_IO2_Msk (0x1UL << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3_Pos (26U)
+#define TSC_IOSCR_G7_IO3_Msk (0x1UL << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4_Pos (27U)
+#define TSC_IOSCR_G7_IO4_Msk (0x1UL << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1_Pos (28U)
+#define TSC_IOSCR_G8_IO1_Msk (0x1UL << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2_Pos (29U)
+#define TSC_IOSCR_G8_IO2_Msk (0x1UL << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3_Pos (30U)
+#define TSC_IOSCR_G8_IO3_Msk (0x1UL << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4_Pos (31U)
+#define TSC_IOSCR_G8_IO4_Msk (0x1UL << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */
+
+/******************* Bit definition for TSC_IOCCR register ******************/
+#define TSC_IOCCR_G1_IO1_Pos (0U)
+#define TSC_IOCCR_G1_IO1_Msk (0x1UL << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2_Pos (1U)
+#define TSC_IOCCR_G1_IO2_Msk (0x1UL << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3_Pos (2U)
+#define TSC_IOCCR_G1_IO3_Msk (0x1UL << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4_Pos (3U)
+#define TSC_IOCCR_G1_IO4_Msk (0x1UL << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1_Pos (4U)
+#define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2_Pos (5U)
+#define TSC_IOCCR_G2_IO2_Msk (0x1UL << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3_Pos (6U)
+#define TSC_IOCCR_G2_IO3_Msk (0x1UL << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4_Pos (7U)
+#define TSC_IOCCR_G2_IO4_Msk (0x1UL << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1_Pos (8U)
+#define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2_Pos (9U)
+#define TSC_IOCCR_G3_IO2_Msk (0x1UL << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3_Pos (10U)
+#define TSC_IOCCR_G3_IO3_Msk (0x1UL << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4_Pos (11U)
+#define TSC_IOCCR_G3_IO4_Msk (0x1UL << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1_Pos (12U)
+#define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2_Pos (13U)
+#define TSC_IOCCR_G4_IO2_Msk (0x1UL << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3_Pos (14U)
+#define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4_Pos (15U)
+#define TSC_IOCCR_G4_IO4_Msk (0x1UL << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1_Pos (16U)
+#define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2_Pos (17U)
+#define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3_Pos (18U)
+#define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4_Pos (19U)
+#define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1_Pos (20U)
+#define TSC_IOCCR_G6_IO1_Msk (0x1UL << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2_Pos (21U)
+#define TSC_IOCCR_G6_IO2_Msk (0x1UL << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3_Pos (22U)
+#define TSC_IOCCR_G6_IO3_Msk (0x1UL << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4_Pos (23U)
+#define TSC_IOCCR_G6_IO4_Msk (0x1UL << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1_Pos (24U)
+#define TSC_IOCCR_G7_IO1_Msk (0x1UL << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2_Pos (25U)
+#define TSC_IOCCR_G7_IO2_Msk (0x1UL << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3_Pos (26U)
+#define TSC_IOCCR_G7_IO3_Msk (0x1UL << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4_Pos (27U)
+#define TSC_IOCCR_G7_IO4_Msk (0x1UL << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1_Pos (28U)
+#define TSC_IOCCR_G8_IO1_Msk (0x1UL << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2_Pos (29U)
+#define TSC_IOCCR_G8_IO2_Msk (0x1UL << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3_Pos (30U)
+#define TSC_IOCCR_G8_IO3_Msk (0x1UL << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4_Pos (31U)
+#define TSC_IOCCR_G8_IO4_Msk (0x1UL << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */
+
+/******************* Bit definition for TSC_IOGCSR register *****************/
+#define TSC_IOGCSR_G1E_Pos (0U)
+#define TSC_IOGCSR_G1E_Msk (0x1UL << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
+#define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E_Pos (1U)
+#define TSC_IOGCSR_G2E_Msk (0x1UL << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
+#define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E_Pos (2U)
+#define TSC_IOGCSR_G3E_Msk (0x1UL << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
+#define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E_Pos (3U)
+#define TSC_IOGCSR_G4E_Msk (0x1UL << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
+#define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E_Pos (4U)
+#define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
+#define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E_Pos (5U)
+#define TSC_IOGCSR_G6E_Msk (0x1UL << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
+#define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E_Pos (6U)
+#define TSC_IOGCSR_G7E_Msk (0x1UL << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
+#define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E_Pos (7U)
+#define TSC_IOGCSR_G8E_Msk (0x1UL << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */
+#define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S_Pos (16U)
+#define TSC_IOGCSR_G1S_Msk (0x1UL << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
+#define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S_Pos (17U)
+#define TSC_IOGCSR_G2S_Msk (0x1UL << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
+#define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S_Pos (18U)
+#define TSC_IOGCSR_G3S_Msk (0x1UL << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
+#define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S_Pos (19U)
+#define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
+#define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S_Pos (20U)
+#define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
+#define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S_Pos (21U)
+#define TSC_IOGCSR_G6S_Msk (0x1UL << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
+#define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S_Pos (22U)
+#define TSC_IOGCSR_G7S_Msk (0x1UL << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
+#define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S_Pos (23U)
+#define TSC_IOGCSR_G8S_Msk (0x1UL << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */
+#define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */
+
+/******************* Bit definition for TSC_IOGXCR register *****************/
+#define TSC_IOGXCR_CNT_Pos (0U)
+#define TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
+#define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE_Pos (0U)
+#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+#define USART_CR1_UESM_Pos (1U)
+#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
+#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_M0_Pos (12U)
+#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
+#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos (13U)
+#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos (14U)
+#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos (16U)
+#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
+#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
+#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
+#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
+#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos (21U)
+#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
+#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
+#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
+#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
+#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos (26U)
+#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos (27U)
+#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos (28U)
+#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
+#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7_Pos (4U)
+#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos (15U)
+#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos (16U)
+#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos (17U)
+#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos (18U)
+#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos (19U)
+#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos (20U)
+#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos (21U)
+#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos (23U)
+#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos (24U)
+#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos (12U)
+#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos (13U)
+#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos (14U)
+#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos (15U)
+#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos (17U)
+#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos (20U)
+#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
+#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
+#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos (22U)
+#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
+#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
+#define USART_CR3_UCESM_Pos (23U)
+#define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
+#define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION_Pos (0U)
+#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos (4U)
+#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO_Pos (0U)
+#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos (24U)
+#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ_Pos (0U)
+#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
+#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos (1U)
+#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
+#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos (2U)
+#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
+#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos (3U)
+#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
+#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos (4U)
+#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
+#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE_Pos (0U)
+#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
+#define USART_ISR_FE_Pos (1U)
+#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
+#define USART_ISR_NE_Pos (2U)
+#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos (3U)
+#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos (4U)
+#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos (5U)
+#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos (6U)
+#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos (7U)
+#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
+#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos (8U)
+#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos (9U)
+#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos (10U)
+#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
+#define USART_ISR_RTOF_Pos (11U)
+#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos (12U)
+#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos (14U)
+#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos (15U)
+#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos (16U)
+#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
+#define USART_ISR_CMF_Pos (17U)
+#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos (18U)
+#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos (19U)
+#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos (20U)
+#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
+#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos (21U)
+#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos (22U)
+#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
+#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF_Pos (0U)
+#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos (1U)
+#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos (2U)
+#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */
+#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos (3U)
+#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos (4U)
+#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos (6U)
+#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF_Pos (8U)
+#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos (9U)
+#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos (11U)
+#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos (12U)
+#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos (17U)
+#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos (20U)
+#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
+#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
+
+/* Compatibility defines with other series */
+#define USART_ICR_NECF USART_ICR_NCF
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR_Pos (0U)
+#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR_Pos (0U)
+#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* USB Device General registers */
+/* */
+/******************************************************************************/
+#define USB_BASE (0x40005C00U) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR_Pos (13U)
+#define USB_PMAADDR_Msk (0x20003UL << USB_PMAADDR_Pos) /*!< 0x40006000 */
+#define USB_PMAADDR USB_PMAADDR_Msk /*!< USB_IP Packet Memory Area base address */
+
+#define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
+#define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
+#define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
+#define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
+#define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
+#define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
+#define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
+
+/**************************** ISTR interrupt events *************************/
+#define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
+#define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
+#define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
+#define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
+#define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
+#define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
+#define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
+#define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
+#define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
+
+#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
+#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
+#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
+#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
+#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
+#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
+#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
+#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
+#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
+/************************* CNTR control register bits definitions ***********/
+#define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
+#define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
+#define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
+#define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
+#define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
+#define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
+#define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
+#define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
+#define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
+#define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
+#define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
+#define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
+#define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
+#define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
+/************************* BCDR control register bits definitions ***********/
+#define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
+#define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
+#define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
+#define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
+#define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
+#define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
+#define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
+#define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
+#define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
+/*************************** LPM register bits definitions ******************/
+#define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
+#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
+#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
+/******************** FNR Frame Number Register bit definitions ************/
+#define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
+#define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
+#define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
+#define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
+#define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
+/******************** DADDR Device ADDRess bit definitions ****************/
+#define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */
+#define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */
+/****************************** Endpoint register *************************/
+#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
+#define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
+#define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
+#define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
+#define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
+#define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
+#define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
+#define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
+/* bit positions */
+#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
+#define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
+#define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
+#define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
+#define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+ /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
+#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+/******************************* COMP Instances *******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+ ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances *********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOH))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C3))
+
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SMBUS Instances *****************************/
+#define IS_SMBUS_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/************* LPTIM instances supporting the encoder mode feature ************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ (((((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3)) \
+ && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM21) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM22) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/******************* TIM Instances : output(s) OCXEC register *****************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART4) || \
+ ((INSTANCE) == USART5))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART4) || \
+ ((INSTANCE) == USART5))
+
+/****************** USART Instances : Auto Baud Rate detection ****************/
+
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART4) || \
+ ((INSTANCE) == USART5) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART4) || \
+ ((INSTANCE) == USART5) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART4) || \
+ ((INSTANCE) == USART5) || \
+ ((INSTANCE) == LPUART1))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/******************************* USB Instances *******************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32L0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32L0 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+
+#define LPUART1_IRQn RNG_LPUART1_IRQn
+#define AES_LPUART1_IRQn RNG_LPUART1_IRQn
+#define AES_RNG_LPUART1_IRQn RNG_LPUART1_IRQn
+#define TIM6_IRQn TIM6_DAC_IRQn
+#define RCC_IRQn RCC_CRS_IRQn
+#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
+#define ADC1_IRQn ADC1_COMP_IRQn
+
+/* Aliases for __IRQHandler */
+#define LPUART1_IRQHandler RNG_LPUART1_IRQHandler
+#define AES_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
+#define AES_RNG_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
+#define TIM6_IRQHandler TIM6_DAC_IRQHandler
+#define RCC_IRQHandler RCC_CRS_IRQHandler
+#define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
+#define ADC1_IRQHandler ADC1_COMP_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L072xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/CMSIS/device/stm32l073xx.h b/CMSIS/device/stm32l073xx.h
new file mode 100644
index 0000000..4d6ad5e
--- /dev/null
+++ b/CMSIS/device/stm32l073xx.h
@@ -0,0 +1,7845 @@
+/**
+ ******************************************************************************
+ * @file stm32l073xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for stm32l073xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright(c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l073xx
+ * @{
+ */
+
+#ifndef __STM32L073xx_H
+#define __STM32L073xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 1U /*!< STM32L0xx provides an MPU */
+#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
+#define __NVIC_PRIO_BITS 2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief stm32l073xx Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+/*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
+
+/****** STM32L-0 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */
+ RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ TSC_IRQn = 8, /*!< TSC Interrupt */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
+ ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
+ LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
+ USART4_5_IRQn = 14, /*!< USART4 and USART5 Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 Interrupt */
+ TIM3_IRQn = 16, /*!< TIM3 Interrupt */
+ TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
+ TIM7_IRQn = 18, /*!< TIM7 Interrupt */
+ TIM21_IRQn = 20, /*!< TIM21 Interrupt */
+ I2C3_IRQn = 21, /*!< I2C3 Interrupt */
+ TIM22_IRQn = 22, /*!< TIM22 Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */
+ I2C2_IRQn = 24, /*!< I2C2 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ SPI2_IRQn = 26, /*!< SPI2 Interrupt */
+ USART1_IRQn = 27, /*!< USART1 Interrupt */
+ USART2_IRQn = 28, /*!< USART2 Interrupt */
+ RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */
+ LCD_IRQn = 30, /*!< LCD Interrupt */
+ USB_IRQn = 31, /*!< USB global Interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0plus.h"
+#include "system_stm32l0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+ uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Comparator
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
+} COMP_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+
+/**
+* @brief CRC calculation unit
+*/
+
+typedef struct
+{
+__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+uint8_t RESERVED0; /*!< Reserved, 0x05 */
+uint16_t RESERVED1; /*!< Reserved, 0x06 */
+__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+uint32_t RESERVED2; /*!< Reserved, 0x0C */
+__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Clock Recovery System
+ */
+
+typedef struct
+{
+__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
+__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
+__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
+__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
+} CRS_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
+} DMA_Request_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
+ __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
+ __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
+ __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
+ __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
+ __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
+ __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
+ __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
+ __IO uint32_t RESERVED1[23]; /*!< Reserved1, Address offset: 0x24 */
+ __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
+ __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
+ __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
+ __IO uint32_t WRP23; /*!< write protection Bytes 2 and 3 Address offset: 0x0C */
+ __IO uint32_t WRP45; /*!< write protection Bytes 4 and 5 Address offset: 0x10 */
+} OB_TypeDef;
+
+
+/**
+ * @brief General Purpose IO
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief LPTIMIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+} LPTIM_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+ * @brief Independent WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief LCD
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
+ __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
+ __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
+ __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
+} LCD_TypeDef;
+
+/**
+ * @brief MIFARE Firewall
+ */
+typedef struct
+{
+ __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
+ __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
+ __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
+ __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
+ __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
+ __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
+ __IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x18 */
+ __IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */
+ __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
+
+} FIREWALL_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
+ __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
+ __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
+ __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
+ __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
+ __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
+ __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
+ __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
+ __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
+ __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
+ __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
+} RCC_TypeDef;
+
+/**
+ * @brief Random numbers generator
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Touch Sensing Controller (TSC)
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
+ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
+ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
+ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
+ __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
+} TSC_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief Universal Serial Bus Full Speed Device
+ */
+typedef struct
+{
+ __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
+ __IO uint16_t RESERVED0; /*!< Reserved */
+ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
+ __IO uint16_t RESERVED1; /*!< Reserved */
+ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
+ __IO uint16_t RESERVED2; /*!< Reserved */
+ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
+ __IO uint16_t RESERVED3; /*!< Reserved */
+ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
+ __IO uint16_t RESERVED4; /*!< Reserved */
+ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
+ __IO uint16_t RESERVED5; /*!< Reserved */
+ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
+ __IO uint16_t RESERVED6; /*!< Reserved */
+ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
+ __IO uint16_t RESERVED7[17]; /*!< Reserved */
+ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
+ __IO uint16_t RESERVED8; /*!< Reserved */
+ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
+ __IO uint16_t RESERVED9; /*!< Reserved */
+ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
+ __IO uint16_t RESERVEDA; /*!< Reserved */
+ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
+ __IO uint16_t RESERVEDB; /*!< Reserved */
+ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
+ __IO uint16_t RESERVEDC; /*!< Reserved */
+ __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
+ __IO uint16_t RESERVEDD; /*!< Reserved */
+ __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
+ __IO uint16_t RESERVEDE; /*!< Reserved */
+} USB_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */
+
+#define DATA_EEPROM_BASE (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
+#define DATA_EEPROM_BANK2_BASE (0x08080C00UL) /*!< DATA EEPROM BANK2 base address in the alias region */
+#define DATA_EEPROM_BANK1_END (0x08080BFFUL) /*!< Program end DATA EEPROM BANK1 address */
+#define DATA_EEPROM_BANK2_END (0x080817FFUL) /*!< Program end DATA EEPROM BANK2 address */
+#define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */
+#define SRAM_SIZE_MAX (0x00005000UL) /*!< maximum SRAM size (up to 20KBytes) */
+
+#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000UL)
+
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL)
+#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL)
+#define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL)
+#define TIM7_BASE (APBPERIPH_BASE + 0x00001400UL)
+#define LCD_BASE (APBPERIPH_BASE + 0x00002400UL)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
+#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
+#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800UL)
+#define USART4_BASE (APBPERIPH_BASE + 0x00004C00UL)
+#define USART5_BASE (APBPERIPH_BASE + 0x00005000UL)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
+#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL)
+#define CRS_BASE (APBPERIPH_BASE + 0x00006C00UL)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
+#define DAC_BASE (APBPERIPH_BASE + 0x00007400UL)
+#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL)
+#define I2C3_BASE (APBPERIPH_BASE + 0x00007800UL)
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
+#define COMP1_BASE (APBPERIPH_BASE + 0x00010018UL)
+#define COMP2_BASE (APBPERIPH_BASE + 0x0001001CUL)
+#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL)
+#define TIM21_BASE (APBPERIPH_BASE + 0x00010800UL)
+#define TIM22_BASE (APBPERIPH_BASE + 0x00011400UL)
+#define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00UL)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708UL)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
+#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
+#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL)
+
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
+#define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */
+#define FLASHSIZE_BASE (0x1FF8007CUL) /*!< FLASH Size register base address */
+#define UID_BASE (0x1FF80050UL) /*!< Unique device ID register base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
+#define TSC_BASE (AHBPERIPH_BASE + 0x00004000UL)
+#define RNG_BASE (AHBPERIPH_BASE + 0x00005000UL)
+
+#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL)
+#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL)
+#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL)
+#define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00UL)
+#define GPIOE_BASE (IOPPERIPH_BASE + 0x00001000UL)
+#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00UL)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CRS ((CRS_TypeDef *) CRS_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define LCD ((LCD_TypeDef *) LCD_BASE)
+#define USART4 ((USART_TypeDef *) USART4_BASE)
+#define USART5 ((USART_TypeDef *) USART5_BASE)
+
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
+#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
+#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
+/* Legacy defines */
+#define ADC ADC1_COMMON
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define TSC ((TSC_TypeDef *) TSC_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+
+#define USB ((USB_TypeDef *) USB_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_EOCAL_Pos (11U)
+#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
+#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
+#define ADC_ISR_AWD_Pos (7U)
+#define ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
+#define ADC_ISR_EOSEQ_Pos (3U)
+#define ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_EOCALIE_Pos (11U)
+#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
+#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
+#define ADC_IER_AWDIE_Pos (7U)
+#define ADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE_Pos (3U)
+#define ADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH_Pos (26U)
+#define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
+#define ADC_CFGR1_AWDEN_Pos (23U)
+#define ADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL_Pos (22U)
+#define ADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN_Pos (16U)
+#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF_Pos (15U)
+#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
+#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT_Pos (14U)
+#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
+#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT_Pos (13U)
+#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD_Pos (12U)
+#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN_Pos (10U)
+#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
+#define ADC_CFGR1_EXTSEL_Pos (6U)
+#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
+#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
+#define ADC_CFGR1_ALIGN_Pos (5U)
+#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
+#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
+#define ADC_CFGR1_RES_Pos (3U)
+#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
+#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
+#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
+#define ADC_CFGR1_SCANDIR_Pos (2U)
+#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG_Pos (1U)
+#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
+#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN_Pos (0U)
+#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
+#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_TOVS_Pos (9U)
+#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
+#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+#define ADC_CFGR2_OVSR_Pos (2U)
+#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
+#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+#define ADC_CFGR2_OVSE_Pos (0U)
+#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
+#define ADC_CFGR2_CKMODE_Pos (30U)
+#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
+#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
+#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
+#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
+
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP_Pos (0U)
+#define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
+#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
+#define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
+#define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define ADC_SMPR_SMPR ADC_SMPR_SMP
+#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
+#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
+#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT_Pos (16U)
+#define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
+#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
+#define ADC_TR_LT_Pos (0U)
+#define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL_Pos (0U)
+#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
+#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
+#define ADC_CHSELR_CHSEL18_Pos (18U)
+#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17_Pos (17U)
+#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
+#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL16_Pos (16U)
+#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */
+#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< Channel 16 selection */
+#define ADC_CHSELR_CHSEL15_Pos (15U)
+#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
+#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14_Pos (14U)
+#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
+#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13_Pos (13U)
+#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
+#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12_Pos (12U)
+#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
+#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11_Pos (11U)
+#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
+#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10_Pos (10U)
+#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
+#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9_Pos (9U)
+#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
+#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8_Pos (8U)
+#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
+#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7_Pos (7U)
+#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
+#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6_Pos (6U)
+#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
+#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5_Pos (5U)
+#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
+#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4_Pos (4U)
+#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
+#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3_Pos (3U)
+#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
+#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2_Pos (2U)
+#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
+#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1_Pos (1U)
+#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
+#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0_Pos (0U)
+#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
+#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_CALFACT_Pos (0U)
+#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_LFMEN_Pos (25U)
+#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
+#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
+#define ADC_CCR_VLCDEN_Pos (24U)
+#define ADC_CCR_VLCDEN_Msk (0x1UL << ADC_CCR_VLCDEN_Pos) /*!< 0x01000000 */
+#define ADC_CCR_VLCDEN ADC_CCR_VLCDEN_Msk /*!< Voltage LCD enable */
+#define ADC_CCR_TSEN_Pos (23U)
+#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+/************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN_Pos (0U)
+#define COMP_CSR_COMP1EN_Msk (0x1UL << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
+#define COMP_CSR_COMP1INNSEL_Pos (4U)
+#define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
+#define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP1WM_Pos (8U)
+#define COMP_CSR_COMP1WM_Msk (0x1UL << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */
+#define COMP_CSR_COMP1LPTIM1IN1_Pos (12U)
+#define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP1POLARITY_Pos (15U)
+#define COMP_CSR_COMP1POLARITY_Msk (0x1UL << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1VALUE_Pos (30U)
+#define COMP_CSR_COMP1VALUE_Msk (0x1UL << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK_Pos (31U)
+#define COMP_CSR_COMP1LOCK_Msk (0x1UL << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN_Pos (0U)
+#define COMP_CSR_COMP2EN_Msk (0x1UL << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
+#define COMP_CSR_COMP2SPEED_Pos (3U)
+#define COMP_CSR_COMP2SPEED_Msk (0x1UL << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */
+#define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */
+#define COMP_CSR_COMP2INNSEL_Pos (4U)
+#define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */
+#define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
+#define COMP_CSR_COMP2INPSEL_Pos (8U)
+#define COMP_CSR_COMP2INPSEL_Msk (0x7UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */
+#define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2INPSEL_0 (0x1UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP2INPSEL_1 (0x2UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */
+#define COMP_CSR_COMP2INPSEL_2 (0x4UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */
+#define COMP_CSR_COMP2LPTIM1IN2_Pos (12U)
+#define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */
+#define COMP_CSR_COMP2LPTIM1IN1_Pos (13U)
+#define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */
+#define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP2POLARITY_Pos (15U)
+#define COMP_CSR_COMP2POLARITY_Msk (0x1UL << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2VALUE_Pos (30U)
+#define COMP_CSR_COMP2VALUE_Msk (0x1UL << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK_Pos (31U)
+#define COMP_CSR_COMP2LOCK_Msk (0x1UL << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
+
+/********************** Bit definition for COMP_CSR register common ****************/
+#define COMP_CSR_COMPxEN_Pos (0U)
+#define COMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
+#define COMP_CSR_COMPxPOLARITY_Pos (15U)
+#define COMP_CSR_COMPxPOLARITY_Msk (0x1UL << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */
+#define COMP_CSR_COMPxOUTVALUE_Pos (30U)
+#define COMP_CSR_COMPxOUTVALUE_Msk (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK_Pos (31U)
+#define COMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
+
+/* Reference defines */
+#define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR (0xFFU) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos (3U)
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos (5U)
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos (7U)
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT_Pos (0U)
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL_Pos (0U)
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* CRS Clock Recovery System */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRS_CR register *********************/
+#define CRS_CR_SYNCOKIE_Pos (0U)
+#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
+#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /* SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE_Pos (1U)
+#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
+#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /* SYNC warning interrupt enable */
+#define CRS_CR_ERRIE_Pos (2U)
+#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
+#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /* SYNC error interrupt enable */
+#define CRS_CR_ESYNCIE_Pos (3U)
+#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
+#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /* Expected SYNC(ESYNCF) interrupt Enable*/
+#define CRS_CR_CEN_Pos (5U)
+#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
+#define CRS_CR_CEN CRS_CR_CEN_Msk /* Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN_Pos (6U)
+#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
+#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /* Automatic trimming enable */
+#define CRS_CR_SWSYNC_Pos (7U)
+#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
+#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /* A Software SYNC event is generated */
+#define CRS_CR_TRIM_Pos (8U)
+#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
+#define CRS_CR_TRIM CRS_CR_TRIM_Msk /* HSI48 oscillator smooth trimming */
+
+/******************* Bit definition for CRS_CFGR register *********************/
+#define CRS_CFGR_RELOAD_Pos (0U)
+#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
+#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /* Counter reload value */
+#define CRS_CFGR_FELIM_Pos (16U)
+#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
+#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /* Frequency error limit */
+
+#define CRS_CFGR_SYNCDIV_Pos (24U)
+#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
+#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /* SYNC divider */
+#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
+#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
+#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
+
+#define CRS_CFGR_SYNCSRC_Pos (28U)
+#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
+#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /* SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
+#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
+
+#define CRS_CFGR_SYNCPOL_Pos (31U)
+#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
+#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /* SYNC polarity selection */
+
+/******************* Bit definition for CRS_ISR register *********************/
+#define CRS_ISR_SYNCOKF_Pos (0U)
+#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
+#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /* SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF_Pos (1U)
+#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
+#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /* SYNC warning */
+#define CRS_ISR_ERRF_Pos (2U)
+#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
+#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /* SYNC error flag */
+#define CRS_ISR_ESYNCF_Pos (3U)
+#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
+#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /* Expected SYNC flag */
+#define CRS_ISR_SYNCERR_Pos (8U)
+#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
+#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /* SYNC error */
+#define CRS_ISR_SYNCMISS_Pos (9U)
+#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
+#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /* SYNC missed */
+#define CRS_ISR_TRIMOVF_Pos (10U)
+#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
+#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /* Trimming overflow or underflow */
+#define CRS_ISR_FEDIR_Pos (15U)
+#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
+#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /* Frequency error direction */
+#define CRS_ISR_FECAP_Pos (16U)
+#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
+#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /* Frequency error capture */
+
+/******************* Bit definition for CRS_ICR register *********************/
+#define CRS_ICR_SYNCOKC_Pos (0U)
+#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
+#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /* SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC_Pos (1U)
+#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
+#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /* SYNC warning clear flag */
+#define CRS_ICR_ERRC_Pos (2U)
+#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
+#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /* Error clear flag */
+#define CRS_ICR_ESYNCC_Pos (3U)
+#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
+#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /* Expected SYNC clear flag */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter (DAC) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1_Pos (0U)
+#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos (1U)
+#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos (2U)
+#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos (3U)
+#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos (6U)
+#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos (8U)
+#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos (12U)
+#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos (13U)
+#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA Underrun interrupt enable */
+
+#define DAC_CR_EN2_Pos (16U)
+#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */
+#define DAC_CR_BOFF2_Pos (17U)
+#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
+#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */
+#define DAC_CR_TEN2_Pos (18U)
+#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos (19U)
+#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos (22U)
+#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos (24U)
+#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos (28U)
+#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos (29U)
+#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel12DMA Underrun interrupt enable */
+
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR_Pos (0U)
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR_Pos (0U)
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1_Pos (13U)
+#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2_Pos (29U)
+#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_DIV_ID_Pos (12U)
+#define DBGMCU_IDCODE_DIV_ID_Msk (0xFUL << DBGMCU_IDCODE_DIV_ID_Pos) /*!< 0x0000F000 */
+#define DBGMCU_IDCODE_DIV_ID DBGMCU_IDCODE_DIV_ID_Msk /*!< Division Identifier */
+#define DBGMCU_IDCODE_MCD_DIV_ID_Pos (13U)
+#define DBGMCU_IDCODE_MCD_DIV_ID_Msk (0x3UL << DBGMCU_IDCODE_MCD_DIV_ID_Pos) /*!< 0x00006000 */
+#define DBGMCU_IDCODE_MCD_DIV_ID DBGMCU_IDCODE_MCD_DIV_ID_Msk /*!< MCD divsion ID is 6 */
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_Pos (0U)
+#define DBGMCU_CR_DBG_Msk (0x7UL << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
+#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos (23U)
+#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1_FZ_DBG_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+
+/******************* Bit definition for DMA_CSELR register *******************/
+#define DMA_CSELR_C1S_Pos (0U)
+#define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
+#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos (4U)
+#define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
+#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos (8U)
+#define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
+#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos (12U)
+#define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
+#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos (16U)
+#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
+#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S_Pos (20U)
+#define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
+#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S_Pos (24U)
+#define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
+#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_IM0_Pos (0U)
+#define EXTI_IMR_IM0_Msk (0x1UL << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_IM1_Pos (1U)
+#define EXTI_IMR_IM1_Msk (0x1UL << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_IM2_Pos (2U)
+#define EXTI_IMR_IM2_Msk (0x1UL << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_IM3_Pos (3U)
+#define EXTI_IMR_IM3_Msk (0x1UL << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_IM4_Pos (4U)
+#define EXTI_IMR_IM4_Msk (0x1UL << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_IM5_Pos (5U)
+#define EXTI_IMR_IM5_Msk (0x1UL << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_IM6_Pos (6U)
+#define EXTI_IMR_IM6_Msk (0x1UL << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_IM7_Pos (7U)
+#define EXTI_IMR_IM7_Msk (0x1UL << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_IM8_Pos (8U)
+#define EXTI_IMR_IM8_Msk (0x1UL << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_IM9_Pos (9U)
+#define EXTI_IMR_IM9_Msk (0x1UL << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_IM10_Pos (10U)
+#define EXTI_IMR_IM10_Msk (0x1UL << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_IM11_Pos (11U)
+#define EXTI_IMR_IM11_Msk (0x1UL << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_IM12_Pos (12U)
+#define EXTI_IMR_IM12_Msk (0x1UL << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_IM13_Pos (13U)
+#define EXTI_IMR_IM13_Msk (0x1UL << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_IM14_Pos (14U)
+#define EXTI_IMR_IM14_Msk (0x1UL << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_IM15_Pos (15U)
+#define EXTI_IMR_IM15_Msk (0x1UL << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_IM16_Pos (16U)
+#define EXTI_IMR_IM16_Msk (0x1UL << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_IM17_Pos (17U)
+#define EXTI_IMR_IM17_Msk (0x1UL << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_IM18_Pos (18U)
+#define EXTI_IMR_IM18_Msk (0x1UL << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_IM19_Pos (19U)
+#define EXTI_IMR_IM19_Msk (0x1UL << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_IM20_Pos (20U)
+#define EXTI_IMR_IM20_Msk (0x1UL << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_IM21_Pos (21U)
+#define EXTI_IMR_IM21_Msk (0x1UL << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_IM22_Pos (22U)
+#define EXTI_IMR_IM22_Msk (0x1UL << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_IM23_Pos (23U)
+#define EXTI_IMR_IM23_Msk (0x1UL << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
+#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_IM24_Pos (24U)
+#define EXTI_IMR_IM24_Msk (0x1UL << EXTI_IMR_IM24_Pos) /*!< 0x01000000 */
+#define EXTI_IMR_IM24 EXTI_IMR_IM24_Msk /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR_IM25_Pos (25U)
+#define EXTI_IMR_IM25_Msk (0x1UL << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */
+#define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_IM26_Pos (26U)
+#define EXTI_IMR_IM26_Msk (0x1UL << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
+#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_IM28_Pos (28U)
+#define EXTI_IMR_IM28_Msk (0x1UL << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
+#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_IM29_Pos (29U)
+#define EXTI_IMR_IM29_Msk (0x1UL << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
+#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
+
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x37FFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x37FFFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_EM0_Pos (0U)
+#define EXTI_EMR_EM0_Msk (0x1UL << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_EM1_Pos (1U)
+#define EXTI_EMR_EM1_Msk (0x1UL << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_EM2_Pos (2U)
+#define EXTI_EMR_EM2_Msk (0x1UL << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_EM3_Pos (3U)
+#define EXTI_EMR_EM3_Msk (0x1UL << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_EM4_Pos (4U)
+#define EXTI_EMR_EM4_Msk (0x1UL << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_EM5_Pos (5U)
+#define EXTI_EMR_EM5_Msk (0x1UL << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_EM6_Pos (6U)
+#define EXTI_EMR_EM6_Msk (0x1UL << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_EM7_Pos (7U)
+#define EXTI_EMR_EM7_Msk (0x1UL << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_EM8_Pos (8U)
+#define EXTI_EMR_EM8_Msk (0x1UL << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_EM9_Pos (9U)
+#define EXTI_EMR_EM9_Msk (0x1UL << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_EM10_Pos (10U)
+#define EXTI_EMR_EM10_Msk (0x1UL << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_EM11_Pos (11U)
+#define EXTI_EMR_EM11_Msk (0x1UL << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_EM12_Pos (12U)
+#define EXTI_EMR_EM12_Msk (0x1UL << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_EM13_Pos (13U)
+#define EXTI_EMR_EM13_Msk (0x1UL << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_EM14_Pos (14U)
+#define EXTI_EMR_EM14_Msk (0x1UL << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_EM15_Pos (15U)
+#define EXTI_EMR_EM15_Msk (0x1UL << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_EM16_Pos (16U)
+#define EXTI_EMR_EM16_Msk (0x1UL << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_EM17_Pos (17U)
+#define EXTI_EMR_EM17_Msk (0x1UL << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_EM18_Pos (18U)
+#define EXTI_EMR_EM18_Msk (0x1UL << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_EM19_Pos (19U)
+#define EXTI_EMR_EM19_Msk (0x1UL << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_EM20_Pos (20U)
+#define EXTI_EMR_EM20_Msk (0x1UL << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_EM21_Pos (21U)
+#define EXTI_EMR_EM21_Msk (0x1UL << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_EM22_Pos (22U)
+#define EXTI_EMR_EM22_Msk (0x1UL << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */
+#define EXTI_EMR_EM23_Pos (23U)
+#define EXTI_EMR_EM23_Msk (0x1UL << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
+#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
+#define EXTI_EMR_EM24_Pos (24U)
+#define EXTI_EMR_EM24_Msk (0x1UL << EXTI_EMR_EM24_Pos) /*!< 0x01000000 */
+#define EXTI_EMR_EM24 EXTI_EMR_EM24_Msk /*!< Event Mask on line 24 */
+#define EXTI_EMR_EM25_Pos (25U)
+#define EXTI_EMR_EM25_Msk (0x1UL << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */
+#define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */
+#define EXTI_EMR_EM26_Pos (26U)
+#define EXTI_EMR_EM26_Msk (0x1UL << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
+#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
+#define EXTI_EMR_EM28_Pos (28U)
+#define EXTI_EMR_EM28_Msk (0x1UL << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
+#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
+#define EXTI_EMR_EM29_Pos (29U)
+#define EXTI_EMR_EM29_Msk (0x1UL << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
+#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_RT0_Pos (0U)
+#define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_RT1_Pos (1U)
+#define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_RT2_Pos (2U)
+#define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_RT3_Pos (3U)
+#define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_RT4_Pos (4U)
+#define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_RT5_Pos (5U)
+#define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_RT6_Pos (6U)
+#define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_RT7_Pos (7U)
+#define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_RT8_Pos (8U)
+#define EXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_RT9_Pos (9U)
+#define EXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_RT10_Pos (10U)
+#define EXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_RT11_Pos (11U)
+#define EXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_RT12_Pos (12U)
+#define EXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_RT13_Pos (13U)
+#define EXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_RT14_Pos (14U)
+#define EXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_RT15_Pos (15U)
+#define EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_RT16_Pos (16U)
+#define EXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_RT17_Pos (17U)
+#define EXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_RT19_Pos (19U)
+#define EXTI_RTSR_RT19_Msk (0x1UL << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_RT20_Pos (20U)
+#define EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_RT21_Pos (21U)
+#define EXTI_RTSR_RT21_Msk (0x1UL << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_RT22_Pos (22U)
+#define EXTI_RTSR_RT22_Msk (0x1UL << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
+#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
+#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
+#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
+#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
+#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
+#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
+#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
+#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
+#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
+#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
+#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
+#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
+#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
+#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
+#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
+#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
+#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
+#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
+#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
+#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
+#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_FT0_Pos (0U)
+#define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_FT1_Pos (1U)
+#define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_FT2_Pos (2U)
+#define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_FT3_Pos (3U)
+#define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_FT4_Pos (4U)
+#define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_FT5_Pos (5U)
+#define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_FT6_Pos (6U)
+#define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_FT7_Pos (7U)
+#define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_FT8_Pos (8U)
+#define EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_FT9_Pos (9U)
+#define EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_FT10_Pos (10U)
+#define EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_FT11_Pos (11U)
+#define EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_FT12_Pos (12U)
+#define EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_FT13_Pos (13U)
+#define EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_FT14_Pos (14U)
+#define EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_FT15_Pos (15U)
+#define EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_FT16_Pos (16U)
+#define EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_FT17_Pos (17U)
+#define EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_FT19_Pos (19U)
+#define EXTI_FTSR_FT19_Msk (0x1UL << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_FT20_Pos (20U)
+#define EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_FT21_Pos (21U)
+#define EXTI_FTSR_FT21_Msk (0x1UL << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_FT22_Pos (22U)
+#define EXTI_FTSR_FT22_Msk (0x1UL << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
+#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
+#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
+#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
+#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
+#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
+#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
+#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
+#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
+#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
+#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
+#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
+#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
+#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
+#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
+#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
+#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
+#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
+#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
+#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
+#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
+#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWI0_Pos (0U)
+#define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWI1_Pos (1U)
+#define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWI2_Pos (2U)
+#define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWI3_Pos (3U)
+#define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWI4_Pos (4U)
+#define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWI5_Pos (5U)
+#define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWI6_Pos (6U)
+#define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWI7_Pos (7U)
+#define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWI8_Pos (8U)
+#define EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWI9_Pos (9U)
+#define EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWI10_Pos (10U)
+#define EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWI11_Pos (11U)
+#define EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWI12_Pos (12U)
+#define EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWI13_Pos (13U)
+#define EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWI14_Pos (14U)
+#define EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWI15_Pos (15U)
+#define EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWI16_Pos (16U)
+#define EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWI17_Pos (17U)
+#define EXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWI19_Pos (19U)
+#define EXTI_SWIER_SWI19_Msk (0x1UL << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWI20_Pos (20U)
+#define EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWI21_Pos (21U)
+#define EXTI_SWIER_SWI21_Msk (0x1UL << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWI22_Pos (22U)
+#define EXTI_SWIER_SWI22_Msk (0x1UL << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
+
+/* Legacy defines */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PIF0_Pos (0U)
+#define EXTI_PR_PIF0_Msk (0x1UL << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
+#define EXTI_PR_PIF1_Pos (1U)
+#define EXTI_PR_PIF1_Msk (0x1UL << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
+#define EXTI_PR_PIF2_Pos (2U)
+#define EXTI_PR_PIF2_Msk (0x1UL << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
+#define EXTI_PR_PIF3_Pos (3U)
+#define EXTI_PR_PIF3_Msk (0x1UL << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
+#define EXTI_PR_PIF4_Pos (4U)
+#define EXTI_PR_PIF4_Msk (0x1UL << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
+#define EXTI_PR_PIF5_Pos (5U)
+#define EXTI_PR_PIF5_Msk (0x1UL << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
+#define EXTI_PR_PIF6_Pos (6U)
+#define EXTI_PR_PIF6_Msk (0x1UL << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
+#define EXTI_PR_PIF7_Pos (7U)
+#define EXTI_PR_PIF7_Msk (0x1UL << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
+#define EXTI_PR_PIF8_Pos (8U)
+#define EXTI_PR_PIF8_Msk (0x1UL << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
+#define EXTI_PR_PIF9_Pos (9U)
+#define EXTI_PR_PIF9_Msk (0x1UL << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
+#define EXTI_PR_PIF10_Pos (10U)
+#define EXTI_PR_PIF10_Msk (0x1UL << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
+#define EXTI_PR_PIF11_Pos (11U)
+#define EXTI_PR_PIF11_Msk (0x1UL << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
+#define EXTI_PR_PIF12_Pos (12U)
+#define EXTI_PR_PIF12_Msk (0x1UL << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
+#define EXTI_PR_PIF13_Pos (13U)
+#define EXTI_PR_PIF13_Msk (0x1UL << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
+#define EXTI_PR_PIF14_Pos (14U)
+#define EXTI_PR_PIF14_Msk (0x1UL << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
+#define EXTI_PR_PIF15_Pos (15U)
+#define EXTI_PR_PIF15_Msk (0x1UL << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
+#define EXTI_PR_PIF16_Pos (16U)
+#define EXTI_PR_PIF16_Msk (0x1UL << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
+#define EXTI_PR_PIF17_Pos (17U)
+#define EXTI_PR_PIF17_Msk (0x1UL << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
+#define EXTI_PR_PIF19_Pos (19U)
+#define EXTI_PR_PIF19_Msk (0x1UL << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
+#define EXTI_PR_PIF20_Pos (20U)
+#define EXTI_PR_PIF20_Msk (0x1UL << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
+#define EXTI_PR_PIF21_Pos (21U)
+#define EXTI_PR_PIF21_Msk (0x1UL << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
+#define EXTI_PR_PIF22_Pos (22U)
+#define EXTI_PR_PIF22_Msk (0x1UL << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
+
+/* Legacy defines */
+#define EXTI_PR_PR0 EXTI_PR_PIF0
+#define EXTI_PR_PR1 EXTI_PR_PIF1
+#define EXTI_PR_PR2 EXTI_PR_PIF2
+#define EXTI_PR_PR3 EXTI_PR_PIF3
+#define EXTI_PR_PR4 EXTI_PR_PIF4
+#define EXTI_PR_PR5 EXTI_PR_PIF5
+#define EXTI_PR_PR6 EXTI_PR_PIF6
+#define EXTI_PR_PR7 EXTI_PR_PIF7
+#define EXTI_PR_PR8 EXTI_PR_PIF8
+#define EXTI_PR_PR9 EXTI_PR_PIF9
+#define EXTI_PR_PR10 EXTI_PR_PIF10
+#define EXTI_PR_PR11 EXTI_PR_PIF11
+#define EXTI_PR_PR12 EXTI_PR_PIF12
+#define EXTI_PR_PR13 EXTI_PR_PIF13
+#define EXTI_PR_PR14 EXTI_PR_PIF14
+#define EXTI_PR_PR15 EXTI_PR_PIF15
+#define EXTI_PR_PR16 EXTI_PR_PIF16
+#define EXTI_PR_PR17 EXTI_PR_PIF17
+#define EXTI_PR_PR19 EXTI_PR_PIF19
+#define EXTI_PR_PR20 EXTI_PR_PIF20
+#define EXTI_PR_PR21 EXTI_PR_PIF21
+#define EXTI_PR_PR22 EXTI_PR_PIF22
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
+#define FLASH_ACR_PRFTEN_Pos (1U)
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_SLEEP_PD_Pos (3U)
+#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD_Pos (4U)
+#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
+#define FLASH_ACR_DISAB_BUF_Pos (5U)
+#define FLASH_ACR_DISAB_BUF_Msk (0x1UL << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
+#define FLASH_ACR_PRE_READ_Pos (6U)
+#define FLASH_ACR_PRE_READ_Msk (0x1UL << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
+#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
+
+/******************* Bit definition for FLASH_PECR register ******************/
+#define FLASH_PECR_PELOCK_Pos (0U)
+#define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
+#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK_Pos (1U)
+#define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
+#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK_Pos (2U)
+#define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
+#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG_Pos (3U)
+#define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
+#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
+#define FLASH_PECR_DATA_Pos (4U)
+#define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
+#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
+#define FLASH_PECR_FIX_Pos (8U)
+#define FLASH_PECR_FIX_Msk (0x1UL << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
+#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE_Pos (9U)
+#define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
+#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
+#define FLASH_PECR_FPRG_Pos (10U)
+#define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
+#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_PARALLBANK_Pos (15U)
+#define FLASH_PECR_PARALLBANK_Msk (0x1UL << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */
+#define FLASH_PECR_PARALLBANK FLASH_PECR_PARALLBANK_Msk /*!< Parallel Bank mode */
+#define FLASH_PECR_EOPIE_Pos (16U)
+#define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
+#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
+#define FLASH_PECR_ERRIE_Pos (17U)
+#define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
+#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
+#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
+#define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
+#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
+#define FLASH_PECR_HALF_ARRAY_Pos (19U)
+#define FLASH_PECR_HALF_ARRAY_Msk (0x1UL << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
+#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
+#define FLASH_PECR_NZDISABLE_Pos (22U)
+#define FLASH_PECR_NZDISABLE_Msk (0x1UL << FLASH_PECR_NZDISABLE_Pos) /*!< 0x00400000 */
+#define FLASH_PECR_NZDISABLE FLASH_PECR_NZDISABLE_Msk /*!< Non-Zero check disable */
+
+/****************** Bit definition for FLASH_PDKEYR register ******************/
+#define FLASH_PDKEYR_PDKEYR_Pos (0U)
+#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PEKEYR register ******************/
+#define FLASH_PEKEYR_PEKEYR_Pos (0U)
+#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PRGKEYR register ******************/
+#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
+#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
+
+/****************** Bit definition for FLASH_OPTKEYR register ******************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_EOP_Pos (1U)
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
+#define FLASH_SR_HVOFF_Pos (2U)
+#define FLASH_SR_HVOFF_Msk (0x1UL << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
+#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
+#define FLASH_SR_READY_Pos (3U)
+#define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */
+#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR_Pos (8U)
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
+#define FLASH_SR_PGAERR_Pos (9U)
+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR_Pos (10U)
+#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
+#define FLASH_SR_OPTVERR_Pos (11U)
+#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
+#define FLASH_SR_RDERR_Pos (13U)
+#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
+#define FLASH_SR_NOTZEROERR_Pos (16U)
+#define FLASH_SR_NOTZEROERR_Msk (0x1UL << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
+#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
+#define FLASH_SR_FWWERR_Pos (17U)
+#define FLASH_SR_FWWERR_Msk (0x1UL << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
+#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
+
+/* Legacy defines */
+#define FLASH_SR_FWWER FLASH_SR_FWWERR
+#define FLASH_SR_ENHV FLASH_SR_HVOFF
+#define FLASH_SR_ENDHV FLASH_SR_HVOFF
+
+/****************** Bit definition for FLASH_OPTR register *******************/
+#define FLASH_OPTR_RDPROT_Pos (0U)
+#define FLASH_OPTR_RDPROT_Msk (0xFFUL << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
+#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
+#define FLASH_OPTR_WPRMOD_Pos (8U)
+#define FLASH_OPTR_WPRMOD_Msk (0x1UL << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
+#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
+#define FLASH_OPTR_BOR_LEV_Pos (16U)
+#define FLASH_OPTR_BOR_LEV_Msk (0xFUL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
+#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OPTR_IWDG_SW_Pos (20U)
+#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
+#define FLASH_OPTR_nRST_STOP_Pos (21U)
+#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OPTR_nRST_STDBY_Pos (22U)
+#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OPTR_BFB2_Pos (23U)
+#define FLASH_OPTR_BFB2_Msk (0x1UL << FLASH_OPTR_BFB2_Pos) /*!< 0x00800000 */
+#define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk /*!< BFB2 */
+#define FLASH_OPTR_USER_Pos (20U)
+#define FLASH_OPTR_USER_Msk (0x7UL << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
+#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OPTR_BOOT1_Pos (31U)
+#define FLASH_OPTR_BOOT1_Msk (0x1UL << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
+#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 (0x00000001U)
+#define GPIO_OTYPER_OT_1 (0x00000002U)
+#define GPIO_OTYPER_OT_2 (0x00000004U)
+#define GPIO_OTYPER_OT_3 (0x00000008U)
+#define GPIO_OTYPER_OT_4 (0x00000010U)
+#define GPIO_OTYPER_OT_5 (0x00000020U)
+#define GPIO_OTYPER_OT_6 (0x00000040U)
+#define GPIO_OTYPER_OT_7 (0x00000080U)
+#define GPIO_OTYPER_OT_8 (0x00000100U)
+#define GPIO_OTYPER_OT_9 (0x00000200U)
+#define GPIO_OTYPER_OT_10 (0x00000400U)
+#define GPIO_OTYPER_OT_11 (0x00000800U)
+#define GPIO_OTYPER_OT_12 (0x00001000U)
+#define GPIO_OTYPER_OT_13 (0x00002000U)
+#define GPIO_OTYPER_OT_14 (0x00004000U)
+#define GPIO_OTYPER_OT_15 (0x00008000U)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDER_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
+#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDER_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
+#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDER_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
+#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDER_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
+#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDER_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
+#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDER_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
+#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDER_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
+#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDER_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
+#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDER_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
+#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDER_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
+#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDER_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
+#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDER_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
+#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDER_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
+#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDER_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
+#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDER_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
+#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDER_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
+#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 (0x00000001U)
+#define GPIO_BSRR_BS_1 (0x00000002U)
+#define GPIO_BSRR_BS_2 (0x00000004U)
+#define GPIO_BSRR_BS_3 (0x00000008U)
+#define GPIO_BSRR_BS_4 (0x00000010U)
+#define GPIO_BSRR_BS_5 (0x00000020U)
+#define GPIO_BSRR_BS_6 (0x00000040U)
+#define GPIO_BSRR_BS_7 (0x00000080U)
+#define GPIO_BSRR_BS_8 (0x00000100U)
+#define GPIO_BSRR_BS_9 (0x00000200U)
+#define GPIO_BSRR_BS_10 (0x00000400U)
+#define GPIO_BSRR_BS_11 (0x00000800U)
+#define GPIO_BSRR_BS_12 (0x00001000U)
+#define GPIO_BSRR_BS_13 (0x00002000U)
+#define GPIO_BSRR_BS_14 (0x00004000U)
+#define GPIO_BSRR_BS_15 (0x00008000U)
+#define GPIO_BSRR_BR_0 (0x00010000U)
+#define GPIO_BSRR_BR_1 (0x00020000U)
+#define GPIO_BSRR_BR_2 (0x00040000U)
+#define GPIO_BSRR_BR_3 (0x00080000U)
+#define GPIO_BSRR_BR_4 (0x00100000U)
+#define GPIO_BSRR_BR_5 (0x00200000U)
+#define GPIO_BSRR_BR_6 (0x00400000U)
+#define GPIO_BSRR_BR_7 (0x00800000U)
+#define GPIO_BSRR_BR_8 (0x01000000U)
+#define GPIO_BSRR_BR_9 (0x02000000U)
+#define GPIO_BSRR_BR_10 (0x04000000U)
+#define GPIO_BSRR_BR_11 (0x08000000U)
+#define GPIO_BSRR_BR_12 (0x10000000U)
+#define GPIO_BSRR_BR_13 (0x20000000U)
+#define GPIO_BSRR_BR_14 (0x40000000U)
+#define GPIO_BSRR_BR_15 (0x80000000U)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 (0x00000001U)
+#define GPIO_BRR_BR_1 (0x00000002U)
+#define GPIO_BRR_BR_2 (0x00000004U)
+#define GPIO_BRR_BR_3 (0x00000008U)
+#define GPIO_BRR_BR_4 (0x00000010U)
+#define GPIO_BRR_BR_5 (0x00000020U)
+#define GPIO_BRR_BR_6 (0x00000040U)
+#define GPIO_BRR_BR_7 (0x00000080U)
+#define GPIO_BRR_BR_8 (0x00000100U)
+#define GPIO_BRR_BR_9 (0x00000200U)
+#define GPIO_BRR_BR_10 (0x00000400U)
+#define GPIO_BRR_BR_11 (0x00000800U)
+#define GPIO_BRR_BR_12 (0x00001000U)
+#define GPIO_BRR_BR_13 (0x00002000U)
+#define GPIO_BRR_BR_14 (0x00004000U)
+#define GPIO_BRR_BR_15 (0x00008000U)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos (1U)
+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos (2U)
+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos (3U)
+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos (4U)
+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos (5U)
+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos (6U)
+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos (7U)
+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos (8U)
+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos (12U)
+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos (14U)
+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos (15U)
+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos (16U)
+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos (17U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos (18U)
+#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos (19U)
+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos (20U)
+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos (21U)
+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos (22U)
+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos (23U)
+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD_Pos (0U)
+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos (10U)
+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos (11U)
+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos (12U)
+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos (13U)
+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
+#define I2C_CR2_STOP_Pos (14U)
+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos (15U)
+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos (16U)
+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos (24U)
+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos (25U)
+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos (26U)
+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1_Pos (0U)
+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos (10U)
+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos (15U)
+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2_Pos (1U)
+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos (8U)
+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos (8U)
+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos (9U)
+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos (8U)
+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos (10U)
+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos (8U)
+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos (9U)
+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos (8U)
+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos (15U)
+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos (0U)
+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos (8U)
+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos (16U)
+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos (20U)
+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos (28U)
+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE_Pos (0U)
+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos (1U)
+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos (2U)
+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos (3U)
+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos (4U)
+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos (5U)
+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos (6U)
+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos (7U)
+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos (8U)
+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
+#define I2C_ISR_ARLO_Pos (9U)
+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos (10U)
+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos (11U)
+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos (12U)
+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos (13U)
+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos (15U)
+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
+#define I2C_ISR_DIR_Pos (16U)
+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos (17U)
+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF_Pos (3U)
+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos (4U)
+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos (5U)
+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos (8U)
+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos (9U)
+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos (10U)
+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos (11U)
+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos (12U)
+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos (13U)
+#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define I2C_PECR_PEC_Pos (0U)
+#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA_Pos (0U)
+#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA_Pos (0U)
+#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos (2U)
+#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN_Pos (0U)
+#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* LCD Controller (LCD) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for LCD_CR register *********************/
+#define LCD_CR_LCDEN_Pos (0U)
+#define LCD_CR_LCDEN_Msk (0x1UL << LCD_CR_LCDEN_Pos) /*!< 0x00000001 */
+#define LCD_CR_LCDEN LCD_CR_LCDEN_Msk /*!< LCD Enable Bit */
+#define LCD_CR_VSEL_Pos (1U)
+#define LCD_CR_VSEL_Msk (0x1UL << LCD_CR_VSEL_Pos) /*!< 0x00000002 */
+#define LCD_CR_VSEL LCD_CR_VSEL_Msk /*!< Voltage source selector Bit */
+
+#define LCD_CR_DUTY_Pos (2U)
+#define LCD_CR_DUTY_Msk (0x7UL << LCD_CR_DUTY_Pos) /*!< 0x0000001C */
+#define LCD_CR_DUTY LCD_CR_DUTY_Msk /*!< DUTY[2:0] bits (Duty selector) */
+#define LCD_CR_DUTY_0 (0x1UL << LCD_CR_DUTY_Pos) /*!< 0x00000004 */
+#define LCD_CR_DUTY_1 (0x2UL << LCD_CR_DUTY_Pos) /*!< 0x00000008 */
+#define LCD_CR_DUTY_2 (0x4UL << LCD_CR_DUTY_Pos) /*!< 0x00000010 */
+
+#define LCD_CR_BIAS_Pos (5U)
+#define LCD_CR_BIAS_Msk (0x3UL << LCD_CR_BIAS_Pos) /*!< 0x00000060 */
+#define LCD_CR_BIAS LCD_CR_BIAS_Msk /*!< BIAS[1:0] bits (Bias selector) */
+#define LCD_CR_BIAS_0 (0x1UL << LCD_CR_BIAS_Pos) /*!< 0x00000020 */
+#define LCD_CR_BIAS_1 (0x2UL << LCD_CR_BIAS_Pos) /*!< 0x00000040 */
+
+#define LCD_CR_MUX_SEG_Pos (7U)
+#define LCD_CR_MUX_SEG_Msk (0x1UL << LCD_CR_MUX_SEG_Pos) /*!< 0x00000080 */
+#define LCD_CR_MUX_SEG LCD_CR_MUX_SEG_Msk /*!< Mux Segment Enable Bit */
+
+#define LCD_CR_BUFEN_Pos (8U)
+#define LCD_CR_BUFEN_Msk (0x1UL << LCD_CR_BUFEN_Pos) /*!< 0x00000100 */
+#define LCD_CR_BUFEN LCD_CR_BUFEN_Msk /*!< Voltage output buffer enable Bit */
+
+/******************* Bit definition for LCD_FCR register ********************/
+#define LCD_FCR_HD_Pos (0U)
+#define LCD_FCR_HD_Msk (0x1UL << LCD_FCR_HD_Pos) /*!< 0x00000001 */
+#define LCD_FCR_HD LCD_FCR_HD_Msk /*!< High Drive Enable Bit */
+#define LCD_FCR_SOFIE_Pos (1U)
+#define LCD_FCR_SOFIE_Msk (0x1UL << LCD_FCR_SOFIE_Pos) /*!< 0x00000002 */
+#define LCD_FCR_SOFIE LCD_FCR_SOFIE_Msk /*!< Start of Frame Interrupt Enable Bit */
+#define LCD_FCR_UDDIE_Pos (3U)
+#define LCD_FCR_UDDIE_Msk (0x1UL << LCD_FCR_UDDIE_Pos) /*!< 0x00000008 */
+#define LCD_FCR_UDDIE LCD_FCR_UDDIE_Msk /*!< Update Display Done Interrupt Enable Bit */
+
+#define LCD_FCR_PON_Pos (4U)
+#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */
+#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */
+#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */
+#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */
+
+#define LCD_FCR_DEAD_Pos (7U)
+#define LCD_FCR_DEAD_Msk (0x7UL << LCD_FCR_DEAD_Pos) /*!< 0x00000380 */
+#define LCD_FCR_DEAD LCD_FCR_DEAD_Msk /*!< DEAD[2:0] bits (DEAD Time) */
+#define LCD_FCR_DEAD_0 (0x1UL << LCD_FCR_DEAD_Pos) /*!< 0x00000080 */
+#define LCD_FCR_DEAD_1 (0x2UL << LCD_FCR_DEAD_Pos) /*!< 0x00000100 */
+#define LCD_FCR_DEAD_2 (0x4UL << LCD_FCR_DEAD_Pos) /*!< 0x00000200 */
+
+#define LCD_FCR_CC_Pos (10U)
+#define LCD_FCR_CC_Msk (0x7UL << LCD_FCR_CC_Pos) /*!< 0x00001C00 */
+#define LCD_FCR_CC LCD_FCR_CC_Msk /*!< CC[2:0] bits (Contrast Control) */
+#define LCD_FCR_CC_0 (0x1UL << LCD_FCR_CC_Pos) /*!< 0x00000400 */
+#define LCD_FCR_CC_1 (0x2UL << LCD_FCR_CC_Pos) /*!< 0x00000800 */
+#define LCD_FCR_CC_2 (0x4UL << LCD_FCR_CC_Pos) /*!< 0x00001000 */
+
+#define LCD_FCR_BLINKF_Pos (13U)
+#define LCD_FCR_BLINKF_Msk (0x7UL << LCD_FCR_BLINKF_Pos) /*!< 0x0000E000 */
+#define LCD_FCR_BLINKF LCD_FCR_BLINKF_Msk /*!< BLINKF[2:0] bits (Blink Frequency) */
+#define LCD_FCR_BLINKF_0 (0x1UL << LCD_FCR_BLINKF_Pos) /*!< 0x00002000 */
+#define LCD_FCR_BLINKF_1 (0x2UL << LCD_FCR_BLINKF_Pos) /*!< 0x00004000 */
+#define LCD_FCR_BLINKF_2 (0x4UL << LCD_FCR_BLINKF_Pos) /*!< 0x00008000 */
+
+#define LCD_FCR_BLINK_Pos (16U)
+#define LCD_FCR_BLINK_Msk (0x3UL << LCD_FCR_BLINK_Pos) /*!< 0x00030000 */
+#define LCD_FCR_BLINK LCD_FCR_BLINK_Msk /*!< BLINK[1:0] bits (Blink Enable) */
+#define LCD_FCR_BLINK_0 (0x1UL << LCD_FCR_BLINK_Pos) /*!< 0x00010000 */
+#define LCD_FCR_BLINK_1 (0x2UL << LCD_FCR_BLINK_Pos) /*!< 0x00020000 */
+
+#define LCD_FCR_DIV_Pos (18U)
+#define LCD_FCR_DIV_Msk (0xFUL << LCD_FCR_DIV_Pos) /*!< 0x003C0000 */
+#define LCD_FCR_DIV LCD_FCR_DIV_Msk /*!< DIV[3:0] bits (Divider) */
+#define LCD_FCR_PS_Pos (22U)
+#define LCD_FCR_PS_Msk (0xFUL << LCD_FCR_PS_Pos) /*!< 0x03C00000 */
+#define LCD_FCR_PS LCD_FCR_PS_Msk /*!< PS[3:0] bits (Prescaler) */
+
+/******************* Bit definition for LCD_SR register *********************/
+#define LCD_SR_ENS_Pos (0U)
+#define LCD_SR_ENS_Msk (0x1UL << LCD_SR_ENS_Pos) /*!< 0x00000001 */
+#define LCD_SR_ENS LCD_SR_ENS_Msk /*!< LCD Enabled Bit */
+#define LCD_SR_SOF_Pos (1U)
+#define LCD_SR_SOF_Msk (0x1UL << LCD_SR_SOF_Pos) /*!< 0x00000002 */
+#define LCD_SR_SOF LCD_SR_SOF_Msk /*!< Start Of Frame Flag Bit */
+#define LCD_SR_UDR_Pos (2U)
+#define LCD_SR_UDR_Msk (0x1UL << LCD_SR_UDR_Pos) /*!< 0x00000004 */
+#define LCD_SR_UDR LCD_SR_UDR_Msk /*!< Update Display Request Bit */
+#define LCD_SR_UDD_Pos (3U)
+#define LCD_SR_UDD_Msk (0x1UL << LCD_SR_UDD_Pos) /*!< 0x00000008 */
+#define LCD_SR_UDD LCD_SR_UDD_Msk /*!< Update Display Done Flag Bit */
+#define LCD_SR_RDY_Pos (4U)
+#define LCD_SR_RDY_Msk (0x1UL << LCD_SR_RDY_Pos) /*!< 0x00000010 */
+#define LCD_SR_RDY LCD_SR_RDY_Msk /*!< Ready Flag Bit */
+#define LCD_SR_FCRSR_Pos (5U)
+#define LCD_SR_FCRSR_Msk (0x1UL << LCD_SR_FCRSR_Pos) /*!< 0x00000020 */
+#define LCD_SR_FCRSR LCD_SR_FCRSR_Msk /*!< LCD FCR Register Synchronization Flag Bit */
+
+/******************* Bit definition for LCD_CLR register ********************/
+#define LCD_CLR_SOFC_Pos (1U)
+#define LCD_CLR_SOFC_Msk (0x1UL << LCD_CLR_SOFC_Pos) /*!< 0x00000002 */
+#define LCD_CLR_SOFC LCD_CLR_SOFC_Msk /*!< Start Of Frame Flag Clear Bit */
+#define LCD_CLR_UDDC_Pos (3U)
+#define LCD_CLR_UDDC_Msk (0x1UL << LCD_CLR_UDDC_Pos) /*!< 0x00000008 */
+#define LCD_CLR_UDDC LCD_CLR_UDDC_Msk /*!< Update Display Done Flag Clear Bit */
+
+/******************* Bit definition for LCD_RAM register ********************/
+#define LCD_RAM_SEGMENT_DATA_Pos (0U)
+#define LCD_RAM_SEGMENT_DATA_Msk (0xFFFFFFFFUL << LCD_RAM_SEGMENT_DATA_Pos) /*!< 0xFFFFFFFF */
+#define LCD_RAM_SEGMENT_DATA LCD_RAM_SEGMENT_DATA_Msk /*!< Segment Data Bits */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM_Pos (0U)
+#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos (1U)
+#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos (2U)
+#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos (3U)
+#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos (4U)
+#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos (5U)
+#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos (6U)
+#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF_Pos (0U)
+#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos (1U)
+#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos (3U)
+#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos (4U)
+#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos (5U)
+#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos (6U)
+#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos (0U)
+#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos (1U)
+#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos (3U)
+#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos (4U)
+#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos (5U)
+#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos (6U)
+#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos (0U)
+#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos (1U)
+#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos (3U)
+#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos (6U)
+#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos (9U)
+#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos (17U)
+#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos (19U)
+#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos (20U)
+#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos (21U)
+#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos (22U)
+#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos (24U)
+#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE_Pos (0U)
+#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos (1U)
+#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos (2U)
+#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP_Pos (0U)
+#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR_Pos (0U)
+#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT_Pos (0U)
+#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
+
+/******************************************************************************/
+/* */
+/* MIFARE Firewall */
+/* */
+/******************************************************************************/
+
+/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
+#define FW_CSSA_ADD_Pos (8U)
+#define FW_CSSA_ADD_Msk (0xFFFFUL << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
+#define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
+#define FW_CSL_LENG_Pos (8U)
+#define FW_CSL_LENG_Msk (0x3FFFUL << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
+#define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
+#define FW_NVDSSA_ADD_Pos (8U)
+#define FW_NVDSSA_ADD_Msk (0xFFFFUL << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
+#define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
+#define FW_NVDSL_LENG_Pos (8U)
+#define FW_NVDSL_LENG_Msk (0x3FFFUL << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
+#define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
+#define FW_VDSSA_ADD_Pos (6U)
+#define FW_VDSSA_ADD_Msk (0x3FFUL << FW_VDSSA_ADD_Pos) /*!< 0x0000FFC0 */
+#define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
+#define FW_VDSL_LENG_Pos (6U)
+#define FW_VDSL_LENG_Msk (0x3FFUL << FW_VDSL_LENG_Pos) /*!< 0x0000FFC0 */
+#define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
+
+/**************************Bit definition for CR register *********************/
+#define FW_CR_FPA_Pos (0U)
+#define FW_CR_FPA_Msk (0x1UL << FW_CR_FPA_Pos) /*!< 0x00000001 */
+#define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
+#define FW_CR_VDS_Pos (1U)
+#define FW_CR_VDS_Msk (0x1UL << FW_CR_VDS_Pos) /*!< 0x00000002 */
+#define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
+#define FW_CR_VDE_Pos (2U)
+#define FW_CR_VDE_Msk (0x1UL << FW_CR_VDE_Pos) /*!< 0x00000004 */
+#define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
+
+/******************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/******************************************************************************/
+
+#define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPSDSR_Pos (0U)
+#define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP_Pos (9U)
+#define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /*!< 0x00000200 */
+#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
+#define PWR_CR_FWU_Pos (10U)
+#define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /*!< 0x00000400 */
+#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
+
+#define PWR_CR_VOS_Pos (11U)
+#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x00001800 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /*!< 0x00000800 */
+#define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /*!< 0x00001000 */
+#define PWR_CR_DSEEKOFF_Pos (13U)
+#define PWR_CR_DSEEKOFF_Msk (0x1UL << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */
+#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */
+#define PWR_CR_LPRUN_Pos (14U)
+#define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
+#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF_Pos (3U)
+#define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
+#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF_Pos (4U)
+#define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
+#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF_Pos (5U)
+#define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
+#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1_Pos (8U)
+#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2_Pos (9U)
+#define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
+#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP3_Pos (10U)
+#define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
+#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+#define RCC_HSI48_SUPPORT /*!< HSI48 feature support */
+#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos (1U)
+#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos (2U)
+#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIVEN_Pos (3U)
+#define RCC_CR_HSIDIVEN_Msk (0x1UL << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */
+#define RCC_CR_HSIDIVF_Pos (4U)
+#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */
+#define RCC_CR_HSIOUTEN_Pos (5U)
+#define RCC_CR_HSIOUTEN_Msk (0x1UL << RCC_CR_HSIOUTEN_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_Msk /*!< Internal High Speed clock out enable */
+#define RCC_CR_MSION_Pos (8U)
+#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000100 */
+#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY_Pos (9U)
+#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
+#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON_Pos (19U)
+#define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */
+#define RCC_CR_RTCPRE_Pos (20U)
+#define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
+#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC/LCD prescaler [1:0] bits */
+#define RCC_CR_RTCPRE_0 (0x1UL << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */
+#define RCC_CR_RTCPRE_1 (0x2UL << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+/* Reference defines */
+#define RCC_CR_CSSON RCC_CR_CSSHSEON
+
+/******************** Bit definition for RCC_ICSCR register *****************/
+#define RCC_ICSCR_HSICAL_Pos (0U)
+#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
+#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM_Pos (8U)
+#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
+#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE_Pos (13U)
+#define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
+#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
+#define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
+#define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
+#define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
+#define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
+#define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
+#define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
+#define RCC_ICSCR_MSICAL_Pos (16U)
+#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
+#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM_Pos (24U)
+#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
+#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
+
+/******************** Bit definition for RCC_CRRCR register *****************/
+#define RCC_CRRCR_HSI48ON_Pos (0U)
+#define RCC_CRRCR_HSI48ON_Msk (0x1UL << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
+#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk /*!< HSI 48MHz clock enable */
+#define RCC_CRRCR_HSI48RDY_Pos (1U)
+#define RCC_CRRCR_HSI48RDY_Msk (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
+#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk /*!< HSI 48MHz clock ready flag */
+#define RCC_CRRCR_HSI48DIV6OUTEN_Pos (2U)
+#define RCC_CRRCR_HSI48DIV6OUTEN_Msk (0x1UL << RCC_CRRCR_HSI48DIV6OUTEN_Pos) /*!< 0x00000004 */
+#define RCC_CRRCR_HSI48DIV6OUTEN RCC_CRRCR_HSI48DIV6OUTEN_Msk /*!< HSI 48MHz DIV6 out enable */
+#define RCC_CRRCR_HSI48CAL_Pos (8U)
+#define RCC_CRRCR_HSI48CAL_Msk (0xFFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF00 */
+#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI 48MHz clock Calibration */
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos (15U)
+#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */
+
+/*!< PLL entry clock source*/
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
+
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL_Pos (18U)
+#define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV_Pos (22U)
+#define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
+
+#define RCC_CFGR_PLLDIV2_Pos (22U)
+#define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3_Pos (23U)
+#define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4_Pos (22U)
+#define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCOSEL_Pos (24U)
+#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
+#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
+
+#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
+#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCOSEL_HSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_MSI_Pos (24U)
+#define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
+#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_HSE_Pos (26U)
+#define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCOSEL_PLL_Pos (24U)
+#define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
+#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
+#define RCC_CFGR_MCOSEL_LSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
+#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
+#define RCC_CFGR_MCOSEL_LSE_Pos (24U)
+#define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
+#define RCC_CFGR_MCOSEL_HSI48_Pos (27U)
+#define RCC_CFGR_MCOSEL_HSI48_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI48_Pos) /*!< 0x08000000 */
+#define RCC_CFGR_MCOSEL_HSI48 RCC_CFGR_MCOSEL_HSI48_Msk /*!< HSI48 clock selected as MCO source */
+
+#define RCC_CFGR_MCOPRE_Pos (28U)
+#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
+
+#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
+
+/* Legacy defines */
+#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
+#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
+#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
+#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
+#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
+#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
+#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
+#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
+#ifdef RCC_CFGR_MCOSEL_HSI48
+#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48
+#endif
+
+#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
+#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
+
+/*!<****************** Bit definition for RCC_CIER register ********************/
+#define RCC_CIER_LSIRDYIE_Pos (0U)
+#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIER_LSERDYIE_Pos (1U)
+#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIER_HSIRDYIE_Pos (2U)
+#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIER_HSERDYIE_Pos (3U)
+#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIER_PLLRDYIE_Pos (4U)
+#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIER_MSIRDYIE_Pos (5U)
+#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
+#define RCC_CIER_HSI48RDYIE_Pos (6U)
+#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000040 */
+#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk /*!< HSI48 Ready Interrupt Enable */
+#define RCC_CIER_CSSLSE_Pos (7U)
+#define RCC_CIER_CSSLSE_Msk (0x1UL << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */
+
+/* Reference defines */
+#define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
+
+/*!<****************** Bit definition for RCC_CIFR register ********************/
+#define RCC_CIFR_LSIRDYF_Pos (0U)
+#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIFR_LSERDYF_Pos (1U)
+#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIFR_HSIRDYF_Pos (2U)
+#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIFR_HSERDYF_Pos (3U)
+#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIFR_PLLRDYF_Pos (4U)
+#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIFR_MSIRDYF_Pos (5U)
+#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
+#define RCC_CIFR_HSI48RDYF_Pos (6U)
+#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk /*!< HSI48 Ready Interrupt flag */
+#define RCC_CIFR_CSSLSEF_Pos (7U)
+#define RCC_CIFR_CSSLSEF_Msk (0x1UL << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */
+#define RCC_CIFR_CSSHSEF_Pos (8U)
+#define RCC_CIFR_CSSHSEF_Msk (0x1UL << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */
+#define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */
+
+/* Reference defines */
+#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
+#define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
+
+/*!<****************** Bit definition for RCC_CICR register ********************/
+#define RCC_CICR_LSIRDYC_Pos (0U)
+#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CICR_LSERDYC_Pos (1U)
+#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CICR_HSIRDYC_Pos (2U)
+#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CICR_HSERDYC_Pos (3U)
+#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CICR_PLLRDYC_Pos (4U)
+#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CICR_MSIRDYC_Pos (5U)
+#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
+#define RCC_CICR_HSI48RDYC_Pos (6U)
+#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000040 */
+#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk /*!< HSI48 Ready Interrupt Clear */
+#define RCC_CICR_CSSLSEC_Pos (7U)
+#define RCC_CICR_CSSLSEC_Msk (0x1UL << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */
+#define RCC_CICR_CSSHSEC_Pos (8U)
+#define RCC_CICR_CSSHSEC_Msk (0x1UL << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */
+#define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */
+
+/* Reference defines */
+#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
+#define RCC_CICR_CSSC RCC_CICR_CSSHSEC
+/***************** Bit definition for RCC_IOPRSTR register ******************/
+#define RCC_IOPRSTR_IOPARST_Pos (0U)
+#define RCC_IOPRSTR_IOPARST_Msk (0x1UL << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */
+#define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */
+#define RCC_IOPRSTR_IOPBRST_Pos (1U)
+#define RCC_IOPRSTR_IOPBRST_Msk (0x1UL << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */
+#define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */
+#define RCC_IOPRSTR_IOPCRST_Pos (2U)
+#define RCC_IOPRSTR_IOPCRST_Msk (0x1UL << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */
+#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */
+#define RCC_IOPRSTR_IOPDRST_Pos (3U)
+#define RCC_IOPRSTR_IOPDRST_Msk (0x1UL << RCC_IOPRSTR_IOPDRST_Pos) /*!< 0x00000008 */
+#define RCC_IOPRSTR_IOPDRST RCC_IOPRSTR_IOPDRST_Msk /*!< GPIO port D reset */
+#define RCC_IOPRSTR_IOPERST_Pos (4U)
+#define RCC_IOPRSTR_IOPERST_Msk (0x1UL << RCC_IOPRSTR_IOPERST_Pos) /*!< 0x00000010 */
+#define RCC_IOPRSTR_IOPERST RCC_IOPRSTR_IOPERST_Msk /*!< GPIO port E reset */
+#define RCC_IOPRSTR_IOPHRST_Pos (7U)
+#define RCC_IOPRSTR_IOPHRST_Msk (0x1UL << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */
+#define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */
+
+/* Reference defines */
+#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
+#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
+#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
+#define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_IOPDRST /*!< GPIO port D reset */
+#define RCC_IOPRSTR_GPIOERST RCC_IOPRSTR_IOPERST /*!< GPIO port E reset */
+#define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
+
+
+/****************** Bit definition for RCC_AHBRST register ******************/
+#define RCC_AHBRSTR_DMARST_Pos (0U)
+#define RCC_AHBRSTR_DMARST_Msk (0x1UL << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */
+#define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */
+#define RCC_AHBRSTR_MIFRST_Pos (8U)
+#define RCC_AHBRSTR_MIFRST_Msk (0x1UL << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */
+#define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset */
+#define RCC_AHBRSTR_CRCRST_Pos (12U)
+#define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
+#define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */
+#define RCC_AHBRSTR_TSCRST_Pos (16U)
+#define RCC_AHBRSTR_TSCRST_Msk (0x1UL << RCC_AHBRSTR_TSCRST_Pos) /*!< 0x00010000 */
+#define RCC_AHBRSTR_TSCRST RCC_AHBRSTR_TSCRST_Msk /*!< TSC reset */
+#define RCC_AHBRSTR_RNGRST_Pos (20U)
+#define RCC_AHBRSTR_RNGRST_Msk (0x1UL << RCC_AHBRSTR_RNGRST_Pos) /*!< 0x00100000 */
+#define RCC_AHBRSTR_RNGRST RCC_AHBRSTR_RNGRST_Msk /*!< RNG reset */
+
+/* Reference defines */
+#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
+#define RCC_APB2RSTR_TIM21RST_Pos (2U)
+#define RCC_APB2RSTR_TIM21RST_Msk (0x1UL << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 reset */
+#define RCC_APB2RSTR_TIM22RST_Pos (5U)
+#define RCC_APB2RSTR_TIM22RST_Msk (0x1UL << RCC_APB2RSTR_TIM22RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk /*!< TIM22 reset */
+#define RCC_APB2RSTR_ADCRST_Pos (9U)
+#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 reset */
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos (14U)
+#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
+#define RCC_APB2RSTR_DBGRST_Pos (22U)
+#define RCC_APB2RSTR_DBGRST_Msk (0x1UL << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU reset */
+
+/* Reference defines */
+#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 reset */
+#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU reset */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
+#define RCC_APB1RSTR_TIM7RST_Pos (5U)
+#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */
+#define RCC_APB1RSTR_LCDRST_Pos (9U)
+#define RCC_APB1RSTR_LCDRST_Msk (0x1UL << RCC_APB1RSTR_LCDRST_Pos) /*!< 0x00000200 */
+#define RCC_APB1RSTR_LCDRST RCC_APB1RSTR_LCDRST_Msk /*!< LCD reset */
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 reset */
+#define RCC_APB1RSTR_USART2RST_Pos (17U)
+#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
+#define RCC_APB1RSTR_LPUART1RST_Pos (18U)
+#define RCC_APB1RSTR_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 reset */
+#define RCC_APB1RSTR_USART4RST_Pos (19U)
+#define RCC_APB1RSTR_USART4RST_Msk (0x1UL << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART4 reset */
+#define RCC_APB1RSTR_USART5RST_Pos (20U)
+#define RCC_APB1RSTR_USART5RST_Msk (0x1UL << RCC_APB1RSTR_USART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR_USART5RST RCC_APB1RSTR_USART5RST_Msk /*!< USART5 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
+#define RCC_APB1RSTR_USBRST_Pos (23U)
+#define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
+#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */
+#define RCC_APB1RSTR_CRSRST_Pos (27U)
+#define RCC_APB1RSTR_CRSRST_Msk (0x1UL << RCC_APB1RSTR_CRSRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1RSTR_CRSRST RCC_APB1RSTR_CRSRST_Msk /*!< CRS reset */
+#define RCC_APB1RSTR_PWRRST_Pos (28U)
+#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
+#define RCC_APB1RSTR_DACRST_Pos (29U)
+#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC reset */
+#define RCC_APB1RSTR_I2C3RST_Pos (30U)
+#define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x40000000 */
+#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk /*!< I2C3 reset */
+#define RCC_APB1RSTR_LPTIM1RST_Pos (31U)
+#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 reset */
+
+/***************** Bit definition for RCC_IOPENR register ******************/
+#define RCC_IOPENR_IOPAEN_Pos (0U)
+#define RCC_IOPENR_IOPAEN_Msk (0x1UL << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */
+#define RCC_IOPENR_IOPBEN_Pos (1U)
+#define RCC_IOPENR_IOPBEN_Msk (0x1UL << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */
+#define RCC_IOPENR_IOPCEN_Pos (2U)
+#define RCC_IOPENR_IOPCEN_Msk (0x1UL << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */
+#define RCC_IOPENR_IOPDEN_Pos (3U)
+#define RCC_IOPENR_IOPDEN_Msk (0x1UL << RCC_IOPENR_IOPDEN_Pos) /*!< 0x00000008 */
+#define RCC_IOPENR_IOPDEN RCC_IOPENR_IOPDEN_Msk /*!< GPIO port D clock enable */
+#define RCC_IOPENR_IOPEEN_Pos (4U)
+#define RCC_IOPENR_IOPEEN_Msk (0x1UL << RCC_IOPENR_IOPEEN_Pos) /*!< 0x00000010 */
+#define RCC_IOPENR_IOPEEN RCC_IOPENR_IOPEEN_Msk /*!< GPIO port E clock enable */
+#define RCC_IOPENR_IOPHEN_Pos (7U)
+#define RCC_IOPENR_IOPHEN_Msk (0x1UL << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */
+
+/* Reference defines */
+#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
+#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
+#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
+#define RCC_IOPENR_GPIODEN RCC_IOPENR_IOPDEN /*!< GPIO port D clock enable */
+#define RCC_IOPENR_GPIOEEN RCC_IOPENR_IOPEEN /*!< GPIO port E clock enable */
+#define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
+
+/***************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_DMAEN_Pos (0U)
+#define RCC_AHBENR_DMAEN_Msk (0x1UL << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
+#define RCC_AHBENR_MIFEN_Pos (8U)
+#define RCC_AHBENR_MIFEN_Msk (0x1UL << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */
+#define RCC_AHBENR_CRCEN_Pos (12U)
+#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
+#define RCC_AHBENR_TSCEN_Pos (16U)
+#define RCC_AHBENR_TSCEN_Msk (0x1UL << RCC_AHBENR_TSCEN_Pos) /*!< 0x00010000 */
+#define RCC_AHBENR_TSCEN RCC_AHBENR_TSCEN_Msk /*!< TSC clock enable */
+#define RCC_AHBENR_RNGEN_Pos (20U)
+#define RCC_AHBENR_RNGEN_Msk (0x1UL << RCC_AHBENR_RNGEN_Pos) /*!< 0x00100000 */
+#define RCC_AHBENR_RNGEN RCC_AHBENR_RNGEN_Msk /*!< RNG clock enable */
+
+/* Reference defines */
+#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
+
+/***************** Bit definition for RCC_APB2ENR register ******************/
+#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */
+#define RCC_APB2ENR_TIM21EN_Pos (2U)
+#define RCC_APB2ENR_TIM21EN_Msk (0x1UL << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */
+#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */
+#define RCC_APB2ENR_TIM22EN_Pos (5U)
+#define RCC_APB2ENR_TIM22EN_Msk (0x1UL << RCC_APB2ENR_TIM22EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk /*!< TIM22 clock enable */
+#define RCC_APB2ENR_FWEN_Pos (7U)
+#define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
+#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADCEN_Pos (9U)
+#define RCC_APB2ENR_ADCEN_Msk (0x1UL << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos (12U)
+#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos (14U)
+#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
+#define RCC_APB2ENR_DBGEN_Pos (22U)
+#define RCC_APB2ENR_DBGEN_Msk (0x1UL << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */
+
+/* Reference defines */
+
+#define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
+#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN_Pos (0U)
+#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
+#define RCC_APB1ENR_TIM3EN_Pos (1U)
+#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_TIM6EN_Pos (4U)
+#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN_Pos (5U)
+#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_LCDEN_Pos (9U)
+#define RCC_APB1ENR_LCDEN_Msk (0x1UL << RCC_APB1ENR_LCDEN_Pos) /*!< 0x00000200 */
+#define RCC_APB1ENR_LCDEN RCC_APB1ENR_LCDEN_Msk /*!< LCD clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos (11U)
+#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN_Pos (14U)
+#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */
+#define RCC_APB1ENR_USART2EN_Pos (17U)
+#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */
+#define RCC_APB1ENR_LPUART1EN_Pos (18U)
+#define RCC_APB1ENR_LPUART1EN_Msk (0x1UL << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */
+#define RCC_APB1ENR_USART4EN_Pos (19U)
+#define RCC_APB1ENR_USART4EN_Msk (0x1UL << RCC_APB1ENR_USART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1ENR_USART4EN RCC_APB1ENR_USART4EN_Msk /*!< USART4 clock enable */
+#define RCC_APB1ENR_USART5EN_Pos (20U)
+#define RCC_APB1ENR_USART5EN_Msk (0x1UL << RCC_APB1ENR_USART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1ENR_USART5EN RCC_APB1ENR_USART5EN_Msk /*!< USART5 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos (21U)
+#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
+#define RCC_APB1ENR_I2C2EN_Pos (22U)
+#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */
+#define RCC_APB1ENR_USBEN_Pos (23U)
+#define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */
+#define RCC_APB1ENR_CRSEN_Pos (27U)
+#define RCC_APB1ENR_CRSEN_Msk (0x1UL << RCC_APB1ENR_CRSEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1ENR_CRSEN RCC_APB1ENR_CRSEN_Msk /*!< CRS clock enable */
+#define RCC_APB1ENR_PWREN_Pos (28U)
+#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
+#define RCC_APB1ENR_DACEN_Pos (29U)
+#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC clock enable */
+#define RCC_APB1ENR_I2C3EN_Pos (30U)
+#define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x40000000 */
+#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk /*!< I2C3 clock enable */
+#define RCC_APB1ENR_LPTIM1EN_Pos (31U)
+#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */
+
+/****************** Bit definition for RCC_IOPSMENR register ****************/
+#define RCC_IOPSMENR_IOPASMEN_Pos (0U)
+#define RCC_IOPSMENR_IOPASMEN_Msk (0x1UL << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */
+#define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPBSMEN_Pos (1U)
+#define RCC_IOPSMENR_IOPBSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */
+#define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPCSMEN_Pos (2U)
+#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */
+#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPDSMEN_Pos (3U)
+#define RCC_IOPSMENR_IOPDSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPDSMEN_Pos) /*!< 0x00000008 */
+#define RCC_IOPSMENR_IOPDSMEN RCC_IOPSMENR_IOPDSMEN_Msk /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPESMEN_Pos (4U)
+#define RCC_IOPSMENR_IOPESMEN_Msk (0x1UL << RCC_IOPSMENR_IOPESMEN_Pos) /*!< 0x00000010 */
+#define RCC_IOPSMENR_IOPESMEN RCC_IOPSMENR_IOPESMEN_Msk /*!< GPIO port E clock enabled in sleep mode */
+#define RCC_IOPSMENR_IOPHSMEN_Pos (7U)
+#define RCC_IOPSMENR_IOPHSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */
+#define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_IOPDSMEN /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOESMEN RCC_IOPSMENR_IOPESMEN /*!< GPIO port E clock enabled in sleep mode */
+#define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_AHBSMENR register ******************/
+#define RCC_AHBSMENR_DMASMEN_Pos (0U)
+#define RCC_AHBSMENR_DMASMEN_Msk (0x1UL << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */
+#define RCC_AHBSMENR_MIFSMEN_Pos (8U)
+#define RCC_AHBSMENR_MIFSMEN_Msk (0x1UL << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */
+#define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */
+#define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
+#define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
+#define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */
+#define RCC_AHBSMENR_CRCSMEN_Pos (12U)
+#define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */
+#define RCC_AHBSMENR_TSCSMEN_Pos (16U)
+#define RCC_AHBSMENR_TSCSMEN_Msk (0x1UL << RCC_AHBSMENR_TSCSMEN_Pos) /*!< 0x00010000 */
+#define RCC_AHBSMENR_TSCSMEN RCC_AHBSMENR_TSCSMEN_Msk /*!< TSC clock enabled in sleep mode */
+#define RCC_AHBSMENR_RNGSMEN_Pos (20U)
+#define RCC_AHBSMENR_RNGSMEN_Msk (0x1UL << RCC_AHBSMENR_RNGSMEN_Pos) /*!< 0x00100000 */
+#define RCC_AHBSMENR_RNGSMEN RCC_AHBSMENR_RNGSMEN_Msk /*!< RNG clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB2SMENR register ******************/
+#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
+#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM21SMEN_Pos (2U)
+#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */
+#define RCC_APB2SMENR_TIM22SMEN_Pos (5U)
+#define RCC_APB2SMENR_TIM22SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk /*!< TIM22 clock enabled in sleep mode */
+#define RCC_APB2SMENR_ADCSMEN_Pos (9U)
+#define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
+#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
+#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk /*!< USART1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGSMEN_Pos (22U)
+#define RCC_APB2SMENR_DBGSMEN_Msk (0x1UL << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */
+
+/* Reference defines */
+#define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB1SMENR register ******************/
+#define RCC_APB1SMENR_TIM2SMEN_Pos (0U)
+#define RCC_APB1SMENR_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_TIM3SMEN_Pos (1U)
+#define RCC_APB1SMENR_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM3SMEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1SMENR_TIM3SMEN RCC_APB1SMENR_TIM3SMEN_Msk /*!< Timer 3 clock enabled in sleep mode */
+#define RCC_APB1SMENR_TIM6SMEN_Pos (4U)
+#define RCC_APB1SMENR_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM6SMEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1SMENR_TIM6SMEN RCC_APB1SMENR_TIM6SMEN_Msk /*!< Timer 6 clock enabled in sleep mode */
+#define RCC_APB1SMENR_TIM7SMEN_Pos (5U)
+#define RCC_APB1SMENR_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR_TIM7SMEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1SMENR_TIM7SMEN RCC_APB1SMENR_TIM7SMEN_Msk /*!< Timer 7 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LCDSMEN_Pos (9U)
+#define RCC_APB1SMENR_LCDSMEN_Msk (0x1UL << RCC_APB1SMENR_LCDSMEN_Pos) /*!< 0x00000200 */
+#define RCC_APB1SMENR_LCDSMEN RCC_APB1SMENR_LCDSMEN_Msk /*!< LCD clock enabled in sleep mode */
+#define RCC_APB1SMENR_WWDGSMEN_Pos (11U)
+#define RCC_APB1SMENR_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */
+#define RCC_APB1SMENR_SPI2SMEN_Pos (14U)
+#define RCC_APB1SMENR_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR_SPI2SMEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1SMENR_SPI2SMEN RCC_APB1SMENR_SPI2SMEN_Msk /*!< SPI2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART2SMEN_Pos (17U)
+#define RCC_APB1SMENR_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPUART1SMEN_Pos (18U)
+#define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART4SMEN_Pos (19U)
+#define RCC_APB1SMENR_USART4SMEN_Msk (0x1UL << RCC_APB1SMENR_USART4SMEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1SMENR_USART4SMEN RCC_APB1SMENR_USART4SMEN_Msk /*!< USART4 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USART5SMEN_Pos (20U)
+#define RCC_APB1SMENR_USART5SMEN_Msk (0x1UL << RCC_APB1SMENR_USART5SMEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1SMENR_USART5SMEN RCC_APB1SMENR_USART5SMEN_Msk /*!< USART5 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C1SMEN_Pos (21U)
+#define RCC_APB1SMENR_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C2SMEN_Pos (22U)
+#define RCC_APB1SMENR_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C2SMEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1SMENR_I2C2SMEN RCC_APB1SMENR_I2C2SMEN_Msk /*!< I2C2 clock enabled in sleep mode */
+#define RCC_APB1SMENR_USBSMEN_Pos (23U)
+#define RCC_APB1SMENR_USBSMEN_Msk (0x1UL << RCC_APB1SMENR_USBSMEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1SMENR_USBSMEN RCC_APB1SMENR_USBSMEN_Msk /*!< USB clock enabled in sleep mode */
+#define RCC_APB1SMENR_CRSSMEN_Pos (27U)
+#define RCC_APB1SMENR_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR_CRSSMEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1SMENR_CRSSMEN RCC_APB1SMENR_CRSSMEN_Msk /*!< CRS clock enabled in sleep mode */
+#define RCC_APB1SMENR_PWRSMEN_Pos (28U)
+#define RCC_APB1SMENR_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */
+#define RCC_APB1SMENR_DACSMEN_Pos (29U)
+#define RCC_APB1SMENR_DACSMEN_Msk (0x1UL << RCC_APB1SMENR_DACSMEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1SMENR_DACSMEN RCC_APB1SMENR_DACSMEN_Msk /*!< DAC clock enabled in sleep mode */
+#define RCC_APB1SMENR_I2C3SMEN_Pos (30U)
+#define RCC_APB1SMENR_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR_I2C3SMEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1SMENR_I2C3SMEN RCC_APB1SMENR_I2C3SMEN_Msk /*!< I2C3 clock enabled in sleep mode */
+#define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U)
+#define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */
+
+/******************* Bit definition for RCC_CCIPR register *******************/
+/*!< USART1 Clock source selection */
+#define RCC_CCIPR_USART1SEL_Pos (0U)
+#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
+#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk /*!< USART1SEL[1:0] bits */
+#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
+
+/*!< USART2 Clock source selection */
+#define RCC_CCIPR_USART2SEL_Pos (2U)
+#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
+#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */
+#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
+#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
+
+/*!< LPUART1 Clock source selection */
+#define RCC_CCIPR_LPUART1SEL_Pos (10U)
+#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
+#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */
+#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */
+#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */
+
+/*!< I2C1 Clock source selection */
+#define RCC_CCIPR_I2C1SEL_Pos (12U)
+#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
+#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */
+#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
+#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
+
+/*!< I2C3 Clock source selection */
+#define RCC_CCIPR_I2C3SEL_Pos (16U)
+#define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
+#define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk /*!< I2C3SEL [1:0] bits */
+#define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
+#define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
+
+/*!< LPTIM1 Clock source selection */
+#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
+#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
+#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */
+#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
+#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
+
+/*!< HSI48 Clock source selection */
+#define RCC_CCIPR_HSI48SEL_Pos (26U)
+#define RCC_CCIPR_HSI48SEL_Msk (0x1UL << RCC_CCIPR_HSI48SEL_Pos) /*!< 0x04000000 */
+#define RCC_CCIPR_HSI48SEL RCC_CCIPR_HSI48SEL_Msk /*!< HSI48 RC clock source selection bit for USB and RNG*/
+
+/* Legacy defines */
+#define RCC_CCIPR_HSI48MSEL RCC_CCIPR_HSI48SEL
+
+/******************* Bit definition for RCC_CSR register *******************/
+#define RCC_CSR_LSION_Pos (0U)
+#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos (1U)
+#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSEON_Pos (8U)
+#define RCC_CSR_LSEON_Msk (0x1UL << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */
+#define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */
+#define RCC_CSR_LSERDY_Pos (9U)
+#define RCC_CSR_LSERDY_Msk (0x1UL << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */
+#define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP_Pos (10U)
+#define RCC_CSR_LSEBYP_Msk (0x1UL << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */
+#define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
+
+#define RCC_CSR_LSEDRV_Pos (11U)
+#define RCC_CSR_LSEDRV_Msk (0x3UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */
+#define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define RCC_CSR_LSEDRV_0 (0x1UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */
+#define RCC_CSR_LSEDRV_1 (0x2UL << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */
+
+#define RCC_CSR_LSECSSON_Pos (13U)
+#define RCC_CSR_LSECSSON_Msk (0x1UL << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */
+#define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */
+#define RCC_CSR_LSECSSD_Pos (14U)
+#define RCC_CSR_LSECSSD_Msk (0x1UL << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */
+#define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
+
+/*!< RTC congiguration */
+#define RCC_CSR_RTCSEL_Pos (16U)
+#define RCC_CSR_RTCSEL_Msk (0x3UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
+
+#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CSR_RTCSEL_LSE_Pos (16U)
+#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_LSI_Pos (17U)
+#define RCC_CSR_RTCSEL_LSI_Msk (0x1UL << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */
+#define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_HSE_Pos (16U)
+#define RCC_CSR_RTCSEL_HSE_Msk (0x3UL << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */
+
+#define RCC_CSR_RTCEN_Pos (18U)
+#define RCC_CSR_RTCEN_Msk (0x1UL << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */
+#define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */
+#define RCC_CSR_RTCRST_Pos (19U)
+#define RCC_CSR_RTCRST_Msk (0x1UL << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */
+#define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */
+
+#define RCC_CSR_RMVF_Pos (23U)
+#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
+#define RCC_CSR_FWRSTF_Pos (24U)
+#define RCC_CSR_FWRSTF_Msk (0x1UL << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
+#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk /*!< Mifare Firewall reset flag */
+#define RCC_CSR_OBLRSTF_Pos (25U)
+#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
+#define RCC_CSR_PINRSTF_Pos (26U)
+#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos (27U)
+#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos (28U)
+#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos (29U)
+#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos (30U)
+#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos (31U)
+#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
+
+/* Reference defines */
+#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
+
+
+/******************************************************************************/
+/* */
+/* RNG */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RNG_CR register *******************/
+#define RNG_CR_RNGEN_Pos (2U)
+#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
+#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos (3U)
+#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
+#define RNG_CR_IE RNG_CR_IE_Msk
+
+/******************** Bits definition for RNG_SR register *******************/
+#define RNG_SR_DRDY_Pos (0U)
+#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
+#define RNG_SR_DRDY RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos (1U)
+#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
+#define RNG_SR_CECS RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos (2U)
+#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
+#define RNG_SR_SECS RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos (5U)
+#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
+#define RNG_SR_CEIS RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos (6U)
+#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
+#define RNG_SR_SEIS RNG_SR_SEIS_Msk
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions
+*/
+#define RTC_TAMPER1_SUPPORT
+#define RTC_TAMPER2_SUPPORT
+#define RTC_TAMPER3_SUPPORT
+#define RTC_WAKEUP_SUPPORT
+#define RTC_BACKUP_SUPPORT
+
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM_Pos (22U)
+#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TR_PM RTC_TR_PM_Msk /*!< */
+#define RTC_TR_HT_Pos (20U)
+#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TR_HT RTC_TR_HT_Msk /*!< */
+#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TR_HU_Pos (16U)
+#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TR_HU RTC_TR_HU_Msk /*!< */
+#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos (12U)
+#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */
+#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos (8U)
+#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */
+#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TR_ST_Pos (4U)
+#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TR_ST RTC_TR_ST_Msk /*!< */
+#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TR_SU_Pos (0U)
+#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TR_SU RTC_TR_SU_Msk /*!< */
+#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT_Pos (20U)
+#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
+#define RTC_DR_YT RTC_DR_YT_Msk /*!< */
+#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
+#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
+#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
+#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
+#define RTC_DR_YU_Pos (16U)
+#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
+#define RTC_DR_YU RTC_DR_YU_Msk /*!< */
+#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
+#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
+#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
+#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos (13U)
+#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */
+#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_DR_MT_Pos (12U)
+#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
+#define RTC_DR_MT RTC_DR_MT_Msk /*!< */
+#define RTC_DR_MU_Pos (8U)
+#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_DR_MU RTC_DR_MU_Msk /*!< */
+#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
+#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
+#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
+#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
+#define RTC_DR_DT_Pos (4U)
+#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
+#define RTC_DR_DT RTC_DR_DT_Msk /*!< */
+#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
+#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
+#define RTC_DR_DU_Pos (0U)
+#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
+#define RTC_DR_DU RTC_DR_DU_Msk /*!< */
+#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
+#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
+#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
+#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE_Pos (23U)
+#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
+#define RTC_CR_COE RTC_CR_COE_Msk /*!< */
+#define RTC_CR_OSEL_Pos (21U)
+#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */
+#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
+#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
+#define RTC_CR_POL_Pos (20U)
+#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
+#define RTC_CR_POL RTC_CR_POL_Msk /*!< */
+#define RTC_CR_COSEL_Pos (19U)
+#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */
+#define RTC_CR_BKP_Pos (18U)
+#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
+#define RTC_CR_BKP RTC_CR_BKP_Msk /*!< */
+#define RTC_CR_SUB1H_Pos (17U)
+#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */
+#define RTC_CR_ADD1H_Pos (16U)
+#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */
+#define RTC_CR_TSIE_Pos (15U)
+#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */
+#define RTC_CR_WUTIE_Pos (14U)
+#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */
+#define RTC_CR_ALRBIE_Pos (13U)
+#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */
+#define RTC_CR_ALRAIE_Pos (12U)
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */
+#define RTC_CR_TSE_Pos (11U)
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
+#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */
+#define RTC_CR_WUTE_Pos (10U)
+#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */
+#define RTC_CR_ALRBE_Pos (9U)
+#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */
+#define RTC_CR_ALRAE_Pos (8U)
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */
+#define RTC_CR_FMT_Pos (6U)
+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
+#define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */
+#define RTC_CR_BYPSHAD_Pos (5U)
+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */
+#define RTC_CR_REFCKON_Pos (4U)
+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */
+#define RTC_CR_TSEDGE_Pos (3U)
+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */
+#define RTC_CR_WUCKSEL_Pos (0U)
+#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */
+#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF_Pos (16U)
+#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */
+#define RTC_ISR_TAMP3F_Pos (15U)
+#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk /*!< */
+#define RTC_ISR_TAMP2F_Pos (14U)
+#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */
+#define RTC_ISR_TAMP1F_Pos (13U)
+#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */
+#define RTC_ISR_TSOVF_Pos (12U)
+#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */
+#define RTC_ISR_TSF_Pos (11U)
+#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */
+#define RTC_ISR_WUTF_Pos (10U)
+#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */
+#define RTC_ISR_ALRBF_Pos (9U)
+#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */
+#define RTC_ISR_ALRAF_Pos (8U)
+#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */
+#define RTC_ISR_INIT_Pos (7U)
+#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */
+#define RTC_ISR_INITF_Pos (6U)
+#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */
+#define RTC_ISR_RSF_Pos (5U)
+#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */
+#define RTC_ISR_INITS_Pos (4U)
+#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */
+#define RTC_ISR_SHPF_Pos (3U)
+#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */
+#define RTC_ISR_WUTWF_Pos (2U)
+#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */
+#define RTC_ISR_ALRBWF_Pos (1U)
+#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */
+#define RTC_ISR_ALRAWF_Pos (0U)
+#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A_Pos (16U)
+#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */
+#define RTC_PRER_PREDIV_S_Pos (0U)
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT_Pos (0U)
+#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4_Pos (31U)
+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */
+#define RTC_ALRMAR_WDSEL_Pos (30U)
+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */
+#define RTC_ALRMAR_DT_Pos (28U)
+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */
+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos (24U)
+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */
+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos (23U)
+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */
+#define RTC_ALRMAR_PM_Pos (22U)
+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */
+#define RTC_ALRMAR_HT_Pos (20U)
+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */
+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos (16U)
+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */
+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos (15U)
+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */
+#define RTC_ALRMAR_MNT_Pos (12U)
+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */
+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos (8U)
+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */
+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos (7U)
+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */
+#define RTC_ALRMAR_ST_Pos (4U)
+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */
+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos (0U)
+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */
+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4_Pos (31U)
+#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */
+#define RTC_ALRMBR_WDSEL_Pos (30U)
+#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */
+#define RTC_ALRMBR_DT_Pos (28U)
+#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */
+#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos (24U)
+#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */
+#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos (23U)
+#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */
+#define RTC_ALRMBR_PM_Pos (22U)
+#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */
+#define RTC_ALRMBR_HT_Pos (20U)
+#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */
+#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos (16U)
+#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */
+#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos (15U)
+#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */
+#define RTC_ALRMBR_MNT_Pos (12U)
+#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */
+#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos (8U)
+#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */
+#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos (7U)
+#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */
+#define RTC_ALRMBR_ST_Pos (4U)
+#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */
+#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos (0U)
+#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */
+#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY_Pos (0U)
+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS_Pos (0U)
+#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS_Pos (0U)
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */
+#define RTC_SHIFTR_ADD1S_Pos (31U)
+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM_Pos (22U)
+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */
+#define RTC_TSTR_HT_Pos (20U)
+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */
+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos (16U)
+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */
+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos (12U)
+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */
+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos (8U)
+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */
+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos (4U)
+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */
+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos (0U)
+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */
+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU_Pos (13U)
+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */
+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos (12U)
+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */
+#define RTC_TSDR_MU_Pos (8U)
+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */
+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos (4U)
+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */
+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos (0U)
+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */
+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS_Pos (0U)
+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
+
+/******************** Bits definition for RTC_CALR register *****************/
+#define RTC_CALR_CALP_Pos (15U)
+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */
+#define RTC_CALR_CALW8_Pos (14U)
+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */
+#define RTC_CALR_CALW16_Pos (13U)
+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */
+#define RTC_CALR_CALM_Pos (0U)
+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */
+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define RTC_CAL_CALP RTC_CALR_CALP
+#define RTC_CAL_CALW8 RTC_CALR_CALW8
+#define RTC_CAL_CALW16 RTC_CALR_CALW16
+#define RTC_CAL_CALM RTC_CALR_CALM
+#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
+#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
+#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
+#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
+#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
+#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
+#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
+#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
+#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
+
+/******************** Bits definition for RTC_TAMPCR register ****************/
+#define RTC_TAMPCR_TAMP3MF_Pos (24U)
+#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
+#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
+#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
+#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP3IE_Pos (22U)
+#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
+#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2MF_Pos (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP2IE_Pos (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1MF_Pos (18U)
+#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */
+#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
+#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1IE_Pos (16U)
+#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */
+#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */
+#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */
+#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */
+#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos (7U)
+#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */
+#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
+#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
+#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP3E_Pos (5U)
+#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
+#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk /*!< */
+#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP2E_Pos (3U)
+#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */
+#define RTC_TAMPCR_TAMPIE_Pos (2U)
+#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */
+#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
+#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */
+#define RTC_TAMPCR_TAMP1E_Pos (0U)
+#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS_Pos (24U)
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos (0U)
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos (0U)
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
+
+/******************** Bits definition for RTC_OR register ****************/
+#define RTC_OR_OUT_RMP_Pos (1U)
+#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */
+#define RTC_OR_ALARMOUTTYPE_Pos (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */
+
+/* Legacy defines */
+#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R_Pos (0U)
+#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP0R RTC_BKP0R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R_Pos (0U)
+#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP1R RTC_BKP1R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R_Pos (0U)
+#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP2R RTC_BKP2R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R_Pos (0U)
+#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP3R RTC_BKP3R_Msk /*!< */
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R_Pos (0U)
+#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
+#define RTC_BKP4R RTC_BKP4R_Msk /*!< */
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER (0x00000005U) /*!< */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+#define SPI_I2S_SUPPORT /*!< I2S support */
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA_Pos (0U)
+#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos (1U)
+#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos (2U)
+#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
+#define SPI_CR1_BR_Pos (3U)
+#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
+#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
+#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
+#define SPI_CR1_SPE_Pos (6U)
+#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos (7U)
+#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
+#define SPI_CR1_SSI_Pos (8U)
+#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos (9U)
+#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos (10U)
+#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
+#define SPI_CR1_DFF_Pos (11U)
+#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
+#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos (12U)
+#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos (13U)
+#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos (14U)
+#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos (15U)
+#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN_Pos (0U)
+#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos (1U)
+#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos (2U)
+#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
+#define SPI_CR2_FRF_Pos (4U)
+#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
+#define SPI_CR2_ERRIE_Pos (5U)
+#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos (6U)
+#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos (7U)
+#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE_Pos (0U)
+#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos (1U)
+#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos (2U)
+#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
+#define SPI_SR_UDR_Pos (3U)
+#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos (4U)
+#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos (5U)
+#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
+#define SPI_SR_OVR_Pos (6U)
+#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
+#define SPI_SR_BSY_Pos (7U)
+#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
+#define SPI_SR_FRE_Pos (8U)
+#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR_Pos (0U)
+#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY_Pos (0U)
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC_Pos (0U)
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC_Pos (0U)
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN_Pos (0U)
+#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN_Pos (1U)
+#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
+#define SPI_I2SCFGR_CKPOL_Pos (3U)
+#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
+#define SPI_I2SCFGR_I2SE_Pos (10U)
+#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
+#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
+#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
+#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV_Pos (0U)
+#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD_Pos (8U)
+#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos (9U)
+#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_CFGR1 register ****************/
+#define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
+#define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR1_UFB_Pos (3U)
+#define SYSCFG_CFGR1_UFB_Msk (0x1UL << SYSCFG_CFGR1_UFB_Pos) /*!< 0x00000008 */
+#define SYSCFG_CFGR1_UFB SYSCFG_CFGR1_UFB_Msk /*!< User bank swapping */
+#define SYSCFG_CFGR1_BOOT_MODE_Pos (8U)
+#define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */
+#define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */
+#define SYSCFG_CFGR1_BOOT_MODE_0 (0x1UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR1_BOOT_MODE_1 (0x2UL << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */
+
+/***************** Bit definition for SYSCFG_CFGR2 register ****************/
+#define SYSCFG_CFGR2_FWDISEN_Pos (0U)
+#define SYSCFG_CFGR2_FWDISEN_Msk (0x1UL << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */
+#define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */
+#define SYSCFG_CFGR2_CAPA_Pos (1U)
+#define SYSCFG_CFGR2_CAPA_Msk (0x1FUL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x0000003E */
+#define SYSCFG_CFGR2_CAPA SYSCFG_CFGR2_CAPA_Msk /*!< Connection of internal Vlcd rail to external capacitors */
+#define SYSCFG_CFGR2_CAPA_0 (0x01UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000002 */
+#define SYSCFG_CFGR2_CAPA_1 (0x02UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000004 */
+#define SYSCFG_CFGR2_CAPA_2 (0x04UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000008 */
+#define SYSCFG_CFGR2_CAPA_3 (0x08UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000010 */
+#define SYSCFG_CFGR2_CAPA_4 (0x10UL << SYSCFG_CFGR2_CAPA_Pos) /*!< 0x00000020 */
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Pos (8U)
+#define SYSCFG_CFGR2_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR2_I2C_PB6_FMP SYSCFG_CFGR2_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Pos (9U)
+#define SYSCFG_CFGR2_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR2_I2C_PB7_FMP SYSCFG_CFGR2_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Pos (10U)
+#define SYSCFG_CFGR2_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */
+#define SYSCFG_CFGR2_I2C_PB8_FMP SYSCFG_CFGR2_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Pos (11U)
+#define SYSCFG_CFGR2_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */
+#define SYSCFG_CFGR2_I2C_PB9_FMP SYSCFG_CFGR2_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_CFGR2_I2C1_FMP_Pos (12U)
+#define SYSCFG_CFGR2_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR2_I2C1_FMP SYSCFG_CFGR2_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
+#define SYSCFG_CFGR2_I2C2_FMP_Pos (13U)
+#define SYSCFG_CFGR2_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */
+#define SYSCFG_CFGR2_I2C2_FMP SYSCFG_CFGR2_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
+#define SYSCFG_CFGR2_I2C3_FMP_Pos (14U)
+#define SYSCFG_CFGR2_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR2_I2C3_FMP_Pos) /*!< 0x00004000 */
+#define SYSCFG_CFGR2_I2C3_FMP SYSCFG_CFGR2_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH (0x00000050U) /*!< PH[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH (0x00000500U) /*!< PH[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
+
+
+/***************** Bit definition for SYSCFG_CFGR3 register ****************/
+#define SYSCFG_CFGR3_EN_VREFINT_Pos (0U)
+#define SYSCFG_CFGR3_EN_VREFINT_Msk (0x1UL << SYSCFG_CFGR3_EN_VREFINT_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_EN_VREFINT SYSCFG_CFGR3_EN_VREFINT_Msk /*!< Vref Enable bit */
+#define SYSCFG_CFGR3_VREF_OUT_Pos (4U)
+#define SYSCFG_CFGR3_VREF_OUT_Msk (0x3UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */
+#define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */
+#define SYSCFG_CFGR3_VREF_OUT_0 (0x1UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */
+#define SYSCFG_CFGR3_VREF_OUT_1 (0x2UL << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U)
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */
+#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U)
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1UL << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */
+#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U)
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1UL << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */
+#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */
+#define SYSCFG_CFGR3_ENREF_HSI48_Pos (13U)
+#define SYSCFG_CFGR3_ENREF_HSI48_Msk (0x1UL << SYSCFG_CFGR3_ENREF_HSI48_Pos) /*!< 0x00002000 */
+#define SYSCFG_CFGR3_ENREF_HSI48 SYSCFG_CFGR3_ENREF_HSI48_Msk /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
+#define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U)
+#define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1UL << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */
+#define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */
+#define SYSCFG_CFGR3_REF_LOCK_Pos (31U)
+#define SYSCFG_CFGR3_REF_LOCK_Msk (0x1UL << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */
+#define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */
+
+/* Legacy defines */
+
+#define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
+#define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
+#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
+#define SYSCFG_CFGR3_ENREF_RC48MHz SYSCFG_CFGR3_ENREF_HSI48
+#define SYSCFG_CFGR3_REF_RC48MHz_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_REF_HSI48_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+#define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF
+
+/******************************************************************************/
+/* */
+/* Timers (TIM)*/
+/* */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+*/
+#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
+ || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+#define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#else
+#define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
+#endif
+
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN_Pos (0U)
+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos (1U)
+#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
+#define TIM_CR1_URS_Pos (2U)
+#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
+#define TIM_CR1_OPM_Pos (3U)
+#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos (4U)
+#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
+
+#define TIM_CR1_CMS_Pos (5U)
+#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
+#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos (7U)
+#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos (8U)
+#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
+#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCDS_Pos (3U)
+#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos (4U)
+#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
+#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
+#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos (7U)
+#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS_Pos (0U)
+#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
+
+#define TIM_SMCR_TS_Pos (4U)
+#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
+#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
+#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos (7U)
+#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos (8U)
+#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos (12U)
+#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos (14U)
+#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos (15U)
+#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE_Pos (0U)
+#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos (1U)
+#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos (2U)
+#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos (3U)
+#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos (4U)
+#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_TIE_Pos (6U)
+#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
+#define TIM_DIER_UDE_Pos (8U)
+#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos (9U)
+#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos (10U)
+#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos (11U)
+#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos (12U)
+#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_TDE_Pos (14U)
+#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF_Pos (0U)
+#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos (1U)
+#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos (2U)
+#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos (3U)
+#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos (4U)
+#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_TIF_Pos (6U)
+#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
+#define TIM_SR_CC1OF_Pos (9U)
+#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos (10U)
+#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos (11U)
+#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos (12U)
+#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG_Pos (0U)
+#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos (1U)
+#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos (2U)
+#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos (3U)
+#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos (4U)
+#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_TG_Pos (6U)
+#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S_Pos (0U)
+#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos (2U)
+#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos (3U)
+#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos (4U)
+#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos (7U)
+#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos (8U)
+#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos (10U)
+#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos (11U)
+#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos (12U)
+#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos (15U)
+#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos (2U)
+#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos (4U)
+#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos (10U)
+#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos (12U)
+#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S_Pos (0U)
+#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos (2U)
+#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos (3U)
+#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos (4U)
+#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos (7U)
+#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos (8U)
+#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos (10U)
+#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos (11U)
+#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos (12U)
+#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos (15U)
+#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos (2U)
+#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos (4U)
+#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos (10U)
+#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos (12U)
+#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E_Pos (0U)
+#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos (1U)
+#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NP_Pos (3U)
+#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos (4U)
+#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos (5U)
+#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NP_Pos (7U)
+#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos (8U)
+#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos (9U)
+#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NP_Pos (11U)
+#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos (12U)
+#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos (13U)
+#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos (15U)
+#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT_Pos (0U)
+#define TIM_CNT_CNT_Msk (0xFFFFUL << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC_Pos (0U)
+#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR_Pos (0U)
+#define TIM_ARR_ARR_Msk (0xFFFFUL << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1_Pos (0U)
+#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2_Pos (0U)
+#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3_Pos (0U)
+#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4_Pos (0U)
+#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA_Pos (0U)
+#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
+#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
+#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
+#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
+#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos (8U)
+#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
+#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
+#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
+#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
+#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB_Pos (0U)
+#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM2_OR_ETR_RMP_Pos (0U)
+#define TIM2_OR_ETR_RMP_Msk (0x7UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000007 */
+#define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
+#define TIM2_OR_ETR_RMP_0 (0x1UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM2_OR_ETR_RMP_1 (0x2UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM2_OR_ETR_RMP_2 (0x4UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000004 */
+#define TIM2_OR_TI4_RMP_Pos (3U)
+#define TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000018 */
+#define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
+#define TIM2_OR_TI4_RMP_0 (0x1UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */
+#define TIM2_OR_TI4_RMP_1 (0x2UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000010 */
+
+#define TIM21_OR_ETR_RMP_Pos (0U)
+#define TIM21_OR_ETR_RMP_Msk (0x3UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
+#define TIM21_OR_ETR_RMP_0 (0x1UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM21_OR_ETR_RMP_1 (0x2UL << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM21_OR_TI1_RMP_Pos (2U)
+#define TIM21_OR_TI1_RMP_Msk (0x7UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x0000001C */
+#define TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
+#define TIM21_OR_TI1_RMP_0 (0x1UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM21_OR_TI1_RMP_1 (0x2UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+#define TIM21_OR_TI1_RMP_2 (0x4UL << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000010 */
+#define TIM21_OR_TI2_RMP_Pos (5U)
+#define TIM21_OR_TI2_RMP_Msk (0x1UL << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */
+#define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */
+
+#define TIM22_OR_ETR_RMP_Pos (0U)
+#define TIM22_OR_ETR_RMP_Msk (0x3UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM22_OR_ETR_RMP TIM22_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
+#define TIM22_OR_ETR_RMP_0 (0x1UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM22_OR_ETR_RMP_1 (0x2UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM22_OR_TI1_RMP_Pos (2U)
+#define TIM22_OR_TI1_RMP_Msk (0x3UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x0000000C */
+#define TIM22_OR_TI1_RMP TIM22_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
+#define TIM22_OR_TI1_RMP_0 (0x1UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM22_OR_TI1_RMP_1 (0x2UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000008 */
+
+#define TIM3_OR_ETR_RMP_Pos (0U)
+#define TIM3_OR_ETR_RMP_Msk (0x3UL << TIM3_OR_ETR_RMP_Pos) /*!< 0x00000003 */
+#define TIM3_OR_ETR_RMP TIM3_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM3 ETR remap) */
+#define TIM3_OR_ETR_RMP_0 (0x1UL << TIM3_OR_ETR_RMP_Pos) /*!< 0x00000001 */
+#define TIM3_OR_ETR_RMP_1 (0x2UL << TIM3_OR_ETR_RMP_Pos) /*!< 0x00000002 */
+#define TIM3_OR_TI1_RMP_Pos (2U)
+#define TIM3_OR_TI1_RMP_Msk (0x1UL << TIM3_OR_TI1_RMP_Pos) /*!< 0x00000004 */
+#define TIM3_OR_TI1_RMP TIM3_OR_TI1_RMP_Msk /*!<TI1_RMP[2] bit */
+#define TIM3_OR_TI2_RMP_Pos (3U)
+#define TIM3_OR_TI2_RMP_Msk (0x1UL << TIM3_OR_TI2_RMP_Pos) /*!< 0x00000008 */
+#define TIM3_OR_TI2_RMP TIM3_OR_TI2_RMP_Msk /*!<TI2_RMP[3] bit */
+#define TIM3_OR_TI4_RMP_Pos (4U)
+#define TIM3_OR_TI4_RMP_Msk (0x1UL << TIM3_OR_TI4_RMP_Pos) /*!< 0x00000010 */
+#define TIM3_OR_TI4_RMP TIM3_OR_TI4_RMP_Msk /*!<TI4_RMP[4] bit */
+
+
+/******************************************************************************/
+/* */
+/* Touch Sensing Controller (TSC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for TSC_CR register *********************/
+#define TSC_CR_TSCE_Pos (0U)
+#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */
+#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */
+#define TSC_CR_START_Pos (1U)
+#define TSC_CR_START_Msk (0x1UL << TSC_CR_START_Pos) /*!< 0x00000002 */
+#define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */
+#define TSC_CR_AM_Pos (2U)
+#define TSC_CR_AM_Msk (0x1UL << TSC_CR_AM_Pos) /*!< 0x00000004 */
+#define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */
+#define TSC_CR_SYNCPOL_Pos (3U)
+#define TSC_CR_SYNCPOL_Msk (0x1UL << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */
+#define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */
+#define TSC_CR_IODEF_Pos (4U)
+#define TSC_CR_IODEF_Msk (0x1UL << TSC_CR_IODEF_Pos) /*!< 0x00000010 */
+#define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */
+
+#define TSC_CR_MCV_Pos (5U)
+#define TSC_CR_MCV_Msk (0x7UL << TSC_CR_MCV_Pos) /*!< 0x000000E0 */
+#define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */
+#define TSC_CR_MCV_0 (0x1UL << TSC_CR_MCV_Pos) /*!< 0x00000020 */
+#define TSC_CR_MCV_1 (0x2UL << TSC_CR_MCV_Pos) /*!< 0x00000040 */
+#define TSC_CR_MCV_2 (0x4UL << TSC_CR_MCV_Pos) /*!< 0x00000080 */
+
+#define TSC_CR_PGPSC_Pos (12U)
+#define TSC_CR_PGPSC_Msk (0x7UL << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */
+#define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
+#define TSC_CR_PGPSC_0 (0x1UL << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */
+#define TSC_CR_PGPSC_1 (0x2UL << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */
+#define TSC_CR_PGPSC_2 (0x4UL << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */
+
+#define TSC_CR_SSPSC_Pos (15U)
+#define TSC_CR_SSPSC_Msk (0x1UL << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */
+#define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */
+#define TSC_CR_SSE_Pos (16U)
+#define TSC_CR_SSE_Msk (0x1UL << TSC_CR_SSE_Pos) /*!< 0x00010000 */
+#define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */
+
+#define TSC_CR_SSD_Pos (17U)
+#define TSC_CR_SSD_Msk (0x7FUL << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */
+#define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
+#define TSC_CR_SSD_0 (0x01UL << TSC_CR_SSD_Pos) /*!< 0x00020000 */
+#define TSC_CR_SSD_1 (0x02UL << TSC_CR_SSD_Pos) /*!< 0x00040000 */
+#define TSC_CR_SSD_2 (0x04UL << TSC_CR_SSD_Pos) /*!< 0x00080000 */
+#define TSC_CR_SSD_3 (0x08UL << TSC_CR_SSD_Pos) /*!< 0x00100000 */
+#define TSC_CR_SSD_4 (0x10UL << TSC_CR_SSD_Pos) /*!< 0x00200000 */
+#define TSC_CR_SSD_5 (0x20UL << TSC_CR_SSD_Pos) /*!< 0x00400000 */
+#define TSC_CR_SSD_6 (0x40UL << TSC_CR_SSD_Pos) /*!< 0x00800000 */
+
+#define TSC_CR_CTPL_Pos (24U)
+#define TSC_CR_CTPL_Msk (0xFUL << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */
+#define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
+#define TSC_CR_CTPL_0 (0x1UL << TSC_CR_CTPL_Pos) /*!< 0x01000000 */
+#define TSC_CR_CTPL_1 (0x2UL << TSC_CR_CTPL_Pos) /*!< 0x02000000 */
+#define TSC_CR_CTPL_2 (0x4UL << TSC_CR_CTPL_Pos) /*!< 0x04000000 */
+#define TSC_CR_CTPL_3 (0x8UL << TSC_CR_CTPL_Pos) /*!< 0x08000000 */
+
+#define TSC_CR_CTPH_Pos (28U)
+#define TSC_CR_CTPH_Msk (0xFUL << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */
+#define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
+#define TSC_CR_CTPH_0 (0x1UL << TSC_CR_CTPH_Pos) /*!< 0x10000000 */
+#define TSC_CR_CTPH_1 (0x2UL << TSC_CR_CTPH_Pos) /*!< 0x20000000 */
+#define TSC_CR_CTPH_2 (0x4UL << TSC_CR_CTPH_Pos) /*!< 0x40000000 */
+#define TSC_CR_CTPH_3 (0x8UL << TSC_CR_CTPH_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for TSC_IER register ********************/
+#define TSC_IER_EOAIE_Pos (0U)
+#define TSC_IER_EOAIE_Msk (0x1UL << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */
+#define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */
+#define TSC_IER_MCEIE_Pos (1U)
+#define TSC_IER_MCEIE_Msk (0x1UL << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */
+#define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */
+
+/******************* Bit definition for TSC_ICR register ********************/
+#define TSC_ICR_EOAIC_Pos (0U)
+#define TSC_ICR_EOAIC_Msk (0x1UL << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */
+#define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */
+#define TSC_ICR_MCEIC_Pos (1U)
+#define TSC_ICR_MCEIC_Msk (0x1UL << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */
+#define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */
+
+/******************* Bit definition for TSC_ISR register ********************/
+#define TSC_ISR_EOAF_Pos (0U)
+#define TSC_ISR_EOAF_Msk (0x1UL << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */
+#define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */
+#define TSC_ISR_MCEF_Pos (1U)
+#define TSC_ISR_MCEF_Msk (0x1UL << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */
+#define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */
+
+/******************* Bit definition for TSC_IOHCR register ******************/
+#define TSC_IOHCR_G1_IO1_Pos (0U)
+#define TSC_IOHCR_G1_IO1_Msk (0x1UL << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO2_Pos (1U)
+#define TSC_IOHCR_G1_IO2_Msk (0x1UL << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO3_Pos (2U)
+#define TSC_IOHCR_G1_IO3_Msk (0x1UL << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G1_IO4_Pos (3U)
+#define TSC_IOHCR_G1_IO4_Msk (0x1UL << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO1_Pos (4U)
+#define TSC_IOHCR_G2_IO1_Msk (0x1UL << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO2_Pos (5U)
+#define TSC_IOHCR_G2_IO2_Msk (0x1UL << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO3_Pos (6U)
+#define TSC_IOHCR_G2_IO3_Msk (0x1UL << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G2_IO4_Pos (7U)
+#define TSC_IOHCR_G2_IO4_Msk (0x1UL << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO1_Pos (8U)
+#define TSC_IOHCR_G3_IO1_Msk (0x1UL << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO2_Pos (9U)
+#define TSC_IOHCR_G3_IO2_Msk (0x1UL << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO3_Pos (10U)
+#define TSC_IOHCR_G3_IO3_Msk (0x1UL << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G3_IO4_Pos (11U)
+#define TSC_IOHCR_G3_IO4_Msk (0x1UL << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO1_Pos (12U)
+#define TSC_IOHCR_G4_IO1_Msk (0x1UL << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO2_Pos (13U)
+#define TSC_IOHCR_G4_IO2_Msk (0x1UL << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO3_Pos (14U)
+#define TSC_IOHCR_G4_IO3_Msk (0x1UL << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G4_IO4_Pos (15U)
+#define TSC_IOHCR_G4_IO4_Msk (0x1UL << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO1_Pos (16U)
+#define TSC_IOHCR_G5_IO1_Msk (0x1UL << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO2_Pos (17U)
+#define TSC_IOHCR_G5_IO2_Msk (0x1UL << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO3_Pos (18U)
+#define TSC_IOHCR_G5_IO3_Msk (0x1UL << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G5_IO4_Pos (19U)
+#define TSC_IOHCR_G5_IO4_Msk (0x1UL << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO1_Pos (20U)
+#define TSC_IOHCR_G6_IO1_Msk (0x1UL << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO2_Pos (21U)
+#define TSC_IOHCR_G6_IO2_Msk (0x1UL << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO3_Pos (22U)
+#define TSC_IOHCR_G6_IO3_Msk (0x1UL << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G6_IO4_Pos (23U)
+#define TSC_IOHCR_G6_IO4_Msk (0x1UL << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO1_Pos (24U)
+#define TSC_IOHCR_G7_IO1_Msk (0x1UL << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO2_Pos (25U)
+#define TSC_IOHCR_G7_IO2_Msk (0x1UL << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO3_Pos (26U)
+#define TSC_IOHCR_G7_IO3_Msk (0x1UL << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G7_IO4_Pos (27U)
+#define TSC_IOHCR_G7_IO4_Msk (0x1UL << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO1_Pos (28U)
+#define TSC_IOHCR_G8_IO1_Msk (0x1UL << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO2_Pos (29U)
+#define TSC_IOHCR_G8_IO2_Msk (0x1UL << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO3_Pos (30U)
+#define TSC_IOHCR_G8_IO3_Msk (0x1UL << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
+#define TSC_IOHCR_G8_IO4_Pos (31U)
+#define TSC_IOHCR_G8_IO4_Msk (0x1UL << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
+
+/******************* Bit definition for TSC_IOASCR register *****************/
+#define TSC_IOASCR_G1_IO1_Pos (0U)
+#define TSC_IOASCR_G1_IO1_Msk (0x1UL << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */
+#define TSC_IOASCR_G1_IO2_Pos (1U)
+#define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */
+#define TSC_IOASCR_G1_IO3_Pos (2U)
+#define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */
+#define TSC_IOASCR_G1_IO4_Pos (3U)
+#define TSC_IOASCR_G1_IO4_Msk (0x1UL << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */
+#define TSC_IOASCR_G2_IO1_Pos (4U)
+#define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */
+#define TSC_IOASCR_G2_IO2_Pos (5U)
+#define TSC_IOASCR_G2_IO2_Msk (0x1UL << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */
+#define TSC_IOASCR_G2_IO3_Pos (6U)
+#define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */
+#define TSC_IOASCR_G2_IO4_Pos (7U)
+#define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */
+#define TSC_IOASCR_G3_IO1_Pos (8U)
+#define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */
+#define TSC_IOASCR_G3_IO2_Pos (9U)
+#define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */
+#define TSC_IOASCR_G3_IO3_Pos (10U)
+#define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */
+#define TSC_IOASCR_G3_IO4_Pos (11U)
+#define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */
+#define TSC_IOASCR_G4_IO1_Pos (12U)
+#define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */
+#define TSC_IOASCR_G4_IO2_Pos (13U)
+#define TSC_IOASCR_G4_IO2_Msk (0x1UL << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */
+#define TSC_IOASCR_G4_IO3_Pos (14U)
+#define TSC_IOASCR_G4_IO3_Msk (0x1UL << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */
+#define TSC_IOASCR_G4_IO4_Pos (15U)
+#define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */
+#define TSC_IOASCR_G5_IO1_Pos (16U)
+#define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */
+#define TSC_IOASCR_G5_IO2_Pos (17U)
+#define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */
+#define TSC_IOASCR_G5_IO3_Pos (18U)
+#define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */
+#define TSC_IOASCR_G5_IO4_Pos (19U)
+#define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */
+#define TSC_IOASCR_G6_IO1_Pos (20U)
+#define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */
+#define TSC_IOASCR_G6_IO2_Pos (21U)
+#define TSC_IOASCR_G6_IO2_Msk (0x1UL << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */
+#define TSC_IOASCR_G6_IO3_Pos (22U)
+#define TSC_IOASCR_G6_IO3_Msk (0x1UL << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */
+#define TSC_IOASCR_G6_IO4_Pos (23U)
+#define TSC_IOASCR_G6_IO4_Msk (0x1UL << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */
+#define TSC_IOASCR_G7_IO1_Pos (24U)
+#define TSC_IOASCR_G7_IO1_Msk (0x1UL << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */
+#define TSC_IOASCR_G7_IO2_Pos (25U)
+#define TSC_IOASCR_G7_IO2_Msk (0x1UL << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */
+#define TSC_IOASCR_G7_IO3_Pos (26U)
+#define TSC_IOASCR_G7_IO3_Msk (0x1UL << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */
+#define TSC_IOASCR_G7_IO4_Pos (27U)
+#define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */
+#define TSC_IOASCR_G8_IO1_Pos (28U)
+#define TSC_IOASCR_G8_IO1_Msk (0x1UL << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */
+#define TSC_IOASCR_G8_IO2_Pos (29U)
+#define TSC_IOASCR_G8_IO2_Msk (0x1UL << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */
+#define TSC_IOASCR_G8_IO3_Pos (30U)
+#define TSC_IOASCR_G8_IO3_Msk (0x1UL << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */
+#define TSC_IOASCR_G8_IO4_Pos (31U)
+#define TSC_IOASCR_G8_IO4_Msk (0x1UL << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */
+
+/******************* Bit definition for TSC_IOSCR register ******************/
+#define TSC_IOSCR_G1_IO1_Pos (0U)
+#define TSC_IOSCR_G1_IO1_Msk (0x1UL << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */
+#define TSC_IOSCR_G1_IO2_Pos (1U)
+#define TSC_IOSCR_G1_IO2_Msk (0x1UL << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */
+#define TSC_IOSCR_G1_IO3_Pos (2U)
+#define TSC_IOSCR_G1_IO3_Msk (0x1UL << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */
+#define TSC_IOSCR_G1_IO4_Pos (3U)
+#define TSC_IOSCR_G1_IO4_Msk (0x1UL << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */
+#define TSC_IOSCR_G2_IO1_Pos (4U)
+#define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */
+#define TSC_IOSCR_G2_IO2_Pos (5U)
+#define TSC_IOSCR_G2_IO2_Msk (0x1UL << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */
+#define TSC_IOSCR_G2_IO3_Pos (6U)
+#define TSC_IOSCR_G2_IO3_Msk (0x1UL << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */
+#define TSC_IOSCR_G2_IO4_Pos (7U)
+#define TSC_IOSCR_G2_IO4_Msk (0x1UL << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */
+#define TSC_IOSCR_G3_IO1_Pos (8U)
+#define TSC_IOSCR_G3_IO1_Msk (0x1UL << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */
+#define TSC_IOSCR_G3_IO2_Pos (9U)
+#define TSC_IOSCR_G3_IO2_Msk (0x1UL << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */
+#define TSC_IOSCR_G3_IO3_Pos (10U)
+#define TSC_IOSCR_G3_IO3_Msk (0x1UL << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */
+#define TSC_IOSCR_G3_IO4_Pos (11U)
+#define TSC_IOSCR_G3_IO4_Msk (0x1UL << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */
+#define TSC_IOSCR_G4_IO1_Pos (12U)
+#define TSC_IOSCR_G4_IO1_Msk (0x1UL << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */
+#define TSC_IOSCR_G4_IO2_Pos (13U)
+#define TSC_IOSCR_G4_IO2_Msk (0x1UL << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */
+#define TSC_IOSCR_G4_IO3_Pos (14U)
+#define TSC_IOSCR_G4_IO3_Msk (0x1UL << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */
+#define TSC_IOSCR_G4_IO4_Pos (15U)
+#define TSC_IOSCR_G4_IO4_Msk (0x1UL << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */
+#define TSC_IOSCR_G5_IO1_Pos (16U)
+#define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */
+#define TSC_IOSCR_G5_IO2_Pos (17U)
+#define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */
+#define TSC_IOSCR_G5_IO3_Pos (18U)
+#define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */
+#define TSC_IOSCR_G5_IO4_Pos (19U)
+#define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */
+#define TSC_IOSCR_G6_IO1_Pos (20U)
+#define TSC_IOSCR_G6_IO1_Msk (0x1UL << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */
+#define TSC_IOSCR_G6_IO2_Pos (21U)
+#define TSC_IOSCR_G6_IO2_Msk (0x1UL << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */
+#define TSC_IOSCR_G6_IO3_Pos (22U)
+#define TSC_IOSCR_G6_IO3_Msk (0x1UL << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */
+#define TSC_IOSCR_G6_IO4_Pos (23U)
+#define TSC_IOSCR_G6_IO4_Msk (0x1UL << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */
+#define TSC_IOSCR_G7_IO1_Pos (24U)
+#define TSC_IOSCR_G7_IO1_Msk (0x1UL << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */
+#define TSC_IOSCR_G7_IO2_Pos (25U)
+#define TSC_IOSCR_G7_IO2_Msk (0x1UL << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */
+#define TSC_IOSCR_G7_IO3_Pos (26U)
+#define TSC_IOSCR_G7_IO3_Msk (0x1UL << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */
+#define TSC_IOSCR_G7_IO4_Pos (27U)
+#define TSC_IOSCR_G7_IO4_Msk (0x1UL << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */
+#define TSC_IOSCR_G8_IO1_Pos (28U)
+#define TSC_IOSCR_G8_IO1_Msk (0x1UL << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */
+#define TSC_IOSCR_G8_IO2_Pos (29U)
+#define TSC_IOSCR_G8_IO2_Msk (0x1UL << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */
+#define TSC_IOSCR_G8_IO3_Pos (30U)
+#define TSC_IOSCR_G8_IO3_Msk (0x1UL << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */
+#define TSC_IOSCR_G8_IO4_Pos (31U)
+#define TSC_IOSCR_G8_IO4_Msk (0x1UL << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */
+
+/******************* Bit definition for TSC_IOCCR register ******************/
+#define TSC_IOCCR_G1_IO1_Pos (0U)
+#define TSC_IOCCR_G1_IO1_Msk (0x1UL << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */
+#define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */
+#define TSC_IOCCR_G1_IO2_Pos (1U)
+#define TSC_IOCCR_G1_IO2_Msk (0x1UL << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */
+#define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */
+#define TSC_IOCCR_G1_IO3_Pos (2U)
+#define TSC_IOCCR_G1_IO3_Msk (0x1UL << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */
+#define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */
+#define TSC_IOCCR_G1_IO4_Pos (3U)
+#define TSC_IOCCR_G1_IO4_Msk (0x1UL << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */
+#define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */
+#define TSC_IOCCR_G2_IO1_Pos (4U)
+#define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */
+#define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */
+#define TSC_IOCCR_G2_IO2_Pos (5U)
+#define TSC_IOCCR_G2_IO2_Msk (0x1UL << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */
+#define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */
+#define TSC_IOCCR_G2_IO3_Pos (6U)
+#define TSC_IOCCR_G2_IO3_Msk (0x1UL << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */
+#define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */
+#define TSC_IOCCR_G2_IO4_Pos (7U)
+#define TSC_IOCCR_G2_IO4_Msk (0x1UL << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */
+#define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */
+#define TSC_IOCCR_G3_IO1_Pos (8U)
+#define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */
+#define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */
+#define TSC_IOCCR_G3_IO2_Pos (9U)
+#define TSC_IOCCR_G3_IO2_Msk (0x1UL << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */
+#define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */
+#define TSC_IOCCR_G3_IO3_Pos (10U)
+#define TSC_IOCCR_G3_IO3_Msk (0x1UL << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */
+#define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */
+#define TSC_IOCCR_G3_IO4_Pos (11U)
+#define TSC_IOCCR_G3_IO4_Msk (0x1UL << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */
+#define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */
+#define TSC_IOCCR_G4_IO1_Pos (12U)
+#define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */
+#define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */
+#define TSC_IOCCR_G4_IO2_Pos (13U)
+#define TSC_IOCCR_G4_IO2_Msk (0x1UL << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */
+#define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */
+#define TSC_IOCCR_G4_IO3_Pos (14U)
+#define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */
+#define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */
+#define TSC_IOCCR_G4_IO4_Pos (15U)
+#define TSC_IOCCR_G4_IO4_Msk (0x1UL << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */
+#define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */
+#define TSC_IOCCR_G5_IO1_Pos (16U)
+#define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */
+#define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */
+#define TSC_IOCCR_G5_IO2_Pos (17U)
+#define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */
+#define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */
+#define TSC_IOCCR_G5_IO3_Pos (18U)
+#define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */
+#define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */
+#define TSC_IOCCR_G5_IO4_Pos (19U)
+#define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */
+#define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */
+#define TSC_IOCCR_G6_IO1_Pos (20U)
+#define TSC_IOCCR_G6_IO1_Msk (0x1UL << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */
+#define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */
+#define TSC_IOCCR_G6_IO2_Pos (21U)
+#define TSC_IOCCR_G6_IO2_Msk (0x1UL << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */
+#define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */
+#define TSC_IOCCR_G6_IO3_Pos (22U)
+#define TSC_IOCCR_G6_IO3_Msk (0x1UL << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */
+#define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */
+#define TSC_IOCCR_G6_IO4_Pos (23U)
+#define TSC_IOCCR_G6_IO4_Msk (0x1UL << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */
+#define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */
+#define TSC_IOCCR_G7_IO1_Pos (24U)
+#define TSC_IOCCR_G7_IO1_Msk (0x1UL << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */
+#define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */
+#define TSC_IOCCR_G7_IO2_Pos (25U)
+#define TSC_IOCCR_G7_IO2_Msk (0x1UL << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */
+#define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */
+#define TSC_IOCCR_G7_IO3_Pos (26U)
+#define TSC_IOCCR_G7_IO3_Msk (0x1UL << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */
+#define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */
+#define TSC_IOCCR_G7_IO4_Pos (27U)
+#define TSC_IOCCR_G7_IO4_Msk (0x1UL << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */
+#define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */
+#define TSC_IOCCR_G8_IO1_Pos (28U)
+#define TSC_IOCCR_G8_IO1_Msk (0x1UL << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */
+#define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */
+#define TSC_IOCCR_G8_IO2_Pos (29U)
+#define TSC_IOCCR_G8_IO2_Msk (0x1UL << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */
+#define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */
+#define TSC_IOCCR_G8_IO3_Pos (30U)
+#define TSC_IOCCR_G8_IO3_Msk (0x1UL << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */
+#define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */
+#define TSC_IOCCR_G8_IO4_Pos (31U)
+#define TSC_IOCCR_G8_IO4_Msk (0x1UL << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */
+#define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */
+
+/******************* Bit definition for TSC_IOGCSR register *****************/
+#define TSC_IOGCSR_G1E_Pos (0U)
+#define TSC_IOGCSR_G1E_Msk (0x1UL << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */
+#define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */
+#define TSC_IOGCSR_G2E_Pos (1U)
+#define TSC_IOGCSR_G2E_Msk (0x1UL << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */
+#define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */
+#define TSC_IOGCSR_G3E_Pos (2U)
+#define TSC_IOGCSR_G3E_Msk (0x1UL << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */
+#define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */
+#define TSC_IOGCSR_G4E_Pos (3U)
+#define TSC_IOGCSR_G4E_Msk (0x1UL << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */
+#define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */
+#define TSC_IOGCSR_G5E_Pos (4U)
+#define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */
+#define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */
+#define TSC_IOGCSR_G6E_Pos (5U)
+#define TSC_IOGCSR_G6E_Msk (0x1UL << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */
+#define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */
+#define TSC_IOGCSR_G7E_Pos (6U)
+#define TSC_IOGCSR_G7E_Msk (0x1UL << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */
+#define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */
+#define TSC_IOGCSR_G8E_Pos (7U)
+#define TSC_IOGCSR_G8E_Msk (0x1UL << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */
+#define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */
+#define TSC_IOGCSR_G1S_Pos (16U)
+#define TSC_IOGCSR_G1S_Msk (0x1UL << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */
+#define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */
+#define TSC_IOGCSR_G2S_Pos (17U)
+#define TSC_IOGCSR_G2S_Msk (0x1UL << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */
+#define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */
+#define TSC_IOGCSR_G3S_Pos (18U)
+#define TSC_IOGCSR_G3S_Msk (0x1UL << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */
+#define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */
+#define TSC_IOGCSR_G4S_Pos (19U)
+#define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */
+#define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */
+#define TSC_IOGCSR_G5S_Pos (20U)
+#define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */
+#define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */
+#define TSC_IOGCSR_G6S_Pos (21U)
+#define TSC_IOGCSR_G6S_Msk (0x1UL << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */
+#define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */
+#define TSC_IOGCSR_G7S_Pos (22U)
+#define TSC_IOGCSR_G7S_Msk (0x1UL << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */
+#define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */
+#define TSC_IOGCSR_G8S_Pos (23U)
+#define TSC_IOGCSR_G8S_Msk (0x1UL << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */
+#define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */
+
+/******************* Bit definition for TSC_IOGXCR register *****************/
+#define TSC_IOGXCR_CNT_Pos (0U)
+#define TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
+#define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
+ */
+/* Note: No specific macro feature on this device */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_UE_Pos (0U)
+#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+#define USART_CR1_UESM_Pos (1U)
+#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
+#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos (2U)
+#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
+#define USART_CR1_TE_Pos (3U)
+#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos (4U)
+#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos (5U)
+#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos (6U)
+#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos (7U)
+#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
+#define USART_CR1_PEIE_Pos (8U)
+#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos (9U)
+#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
+#define USART_CR1_PCE_Pos (10U)
+#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos (11U)
+#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos (12U)
+#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
+#define USART_CR1_M0_Pos (12U)
+#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
+#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos (13U)
+#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos (14U)
+#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos (16U)
+#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
+#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
+#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
+#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
+#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos (21U)
+#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
+#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
+#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
+#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
+#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos (26U)
+#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos (27U)
+#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos (28U)
+#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
+#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADDM7_Pos (4U)
+#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos (5U)
+#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos (6U)
+#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos (8U)
+#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos (9U)
+#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos (10U)
+#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos (11U)
+#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
+#define USART_CR2_STOP_Pos (12U)
+#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
+#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos (14U)
+#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos (15U)
+#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos (16U)
+#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos (17U)
+#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos (18U)
+#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos (19U)
+#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos (20U)
+#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos (21U)
+#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos (23U)
+#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos (24U)
+#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE_Pos (0U)
+#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos (1U)
+#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos (2U)
+#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos (3U)
+#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos (4U)
+#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos (5U)
+#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos (6U)
+#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos (7U)
+#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos (8U)
+#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos (9U)
+#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos (10U)
+#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos (12U)
+#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos (13U)
+#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos (14U)
+#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos (15U)
+#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos (17U)
+#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos (20U)
+#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
+#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
+#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos (22U)
+#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
+#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
+#define USART_CR3_UCESM_Pos (23U)
+#define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
+#define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION_Pos (0U)
+#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos (4U)
+#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC_Pos (0U)
+#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos (8U)
+#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
+
+
+/******************* Bit definition for USART_RTOR register *****************/
+#define USART_RTOR_RTO_Pos (0U)
+#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos (24U)
+#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
+
+/******************* Bit definition for USART_RQR register ******************/
+#define USART_RQR_ABRRQ_Pos (0U)
+#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
+#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos (1U)
+#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
+#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos (2U)
+#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
+#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos (3U)
+#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
+#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos (4U)
+#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
+#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
+
+/******************* Bit definition for USART_ISR register ******************/
+#define USART_ISR_PE_Pos (0U)
+#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
+#define USART_ISR_FE_Pos (1U)
+#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
+#define USART_ISR_NE_Pos (2U)
+#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos (3U)
+#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos (4U)
+#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
+#define USART_ISR_RXNE_Pos (5U)
+#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
+#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
+#define USART_ISR_TC_Pos (6U)
+#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
+#define USART_ISR_TXE_Pos (7U)
+#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
+#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
+#define USART_ISR_LBDF_Pos (8U)
+#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos (9U)
+#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos (10U)
+#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
+#define USART_ISR_RTOF_Pos (11U)
+#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos (12U)
+#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
+#define USART_ISR_ABRE_Pos (14U)
+#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos (15U)
+#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos (16U)
+#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
+#define USART_ISR_CMF_Pos (17U)
+#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos (18U)
+#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos (19U)
+#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos (20U)
+#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
+#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos (21U)
+#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos (22U)
+#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
+#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
+
+/******************* Bit definition for USART_ICR register ******************/
+#define USART_ICR_PECF_Pos (0U)
+#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos (1U)
+#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
+#define USART_ICR_NCF_Pos (2U)
+#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */
+#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos (3U)
+#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos (4U)
+#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TCCF_Pos (6U)
+#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
+#define USART_ICR_LBDCF_Pos (8U)
+#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos (9U)
+#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos (11U)
+#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos (12U)
+#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
+#define USART_ICR_CMCF_Pos (17U)
+#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos (20U)
+#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
+#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
+
+/* Compatibility defines with other series */
+#define USART_ICR_NECF USART_ICR_NCF
+
+/******************* Bit definition for USART_RDR register ******************/
+#define USART_RDR_RDR_Pos (0U)
+#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
+
+/******************* Bit definition for USART_TDR register ******************/
+#define USART_TDR_TDR_Pos (0U)
+#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/* */
+/* USB Device General registers */
+/* */
+/******************************************************************************/
+#define USB_BASE (0x40005C00U) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR_Pos (13U)
+#define USB_PMAADDR_Msk (0x20003UL << USB_PMAADDR_Pos) /*!< 0x40006000 */
+#define USB_PMAADDR USB_PMAADDR_Msk /*!< USB_IP Packet Memory Area base address */
+
+#define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
+#define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
+#define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
+#define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
+#define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
+#define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
+#define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
+
+/**************************** ISTR interrupt events *************************/
+#define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
+#define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
+#define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
+#define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
+#define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
+#define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
+#define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
+#define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
+#define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
+#define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
+
+#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
+#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
+#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
+#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
+#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
+#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
+#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
+#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
+#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
+/************************* CNTR control register bits definitions ***********/
+#define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
+#define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
+#define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
+#define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
+#define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
+#define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
+#define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
+#define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
+#define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
+#define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
+#define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
+#define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
+#define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
+#define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
+#define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
+/************************* BCDR control register bits definitions ***********/
+#define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
+#define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
+#define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
+#define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
+#define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
+#define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
+#define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
+#define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
+#define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
+/*************************** LPM register bits definitions ******************/
+#define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
+#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
+#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
+#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
+/******************** FNR Frame Number Register bit definitions ************/
+#define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
+#define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
+#define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
+#define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
+#define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
+/******************** DADDR Device ADDRess bit definitions ****************/
+#define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */
+#define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */
+/****************************** Endpoint register *************************/
+#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
+#define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
+#define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
+#define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
+#define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
+#define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
+#define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
+#define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
+/* bit positions */
+#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
+#define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
+#define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
+#define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
+#define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+ /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
+#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T_Pos (0U)
+#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
+#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
+#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
+#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
+#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
+#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
+#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
+#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CR_T0 WWDG_CR_T_0
+#define WWDG_CR_T1 WWDG_CR_T_1
+#define WWDG_CR_T2 WWDG_CR_T_2
+#define WWDG_CR_T3 WWDG_CR_T_3
+#define WWDG_CR_T4 WWDG_CR_T_4
+#define WWDG_CR_T5 WWDG_CR_T_5
+#define WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos (7U)
+#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W_Pos (0U)
+#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
+#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
+#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
+#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
+#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
+#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
+#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
+
+/* Legacy defines */
+#define WWDG_CFR_W0 WWDG_CFR_W_0
+#define WWDG_CFR_W1 WWDG_CFR_W_1
+#define WWDG_CFR_W2 WWDG_CFR_W_2
+#define WWDG_CFR_W3 WWDG_CFR_W_3
+#define WWDG_CFR_W4 WWDG_CFR_W_4
+#define WWDG_CFR_W5 WWDG_CFR_W_5
+#define WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos (7U)
+#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
+
+/* Legacy defines */
+#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos (9U)
+#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF_Pos (0U)
+#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macros
+ * @{
+ */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+/******************************* COMP Instances *******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+ ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances *********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/******************************* DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+ ((INSTANCE) == DMA1_Channel2) || \
+ ((INSTANCE) == DMA1_Channel3) || \
+ ((INSTANCE) == DMA1_Channel4) || \
+ ((INSTANCE) == DMA1_Channel5) || \
+ ((INSTANCE) == DMA1_Channel6) || \
+ ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOH))
+
+#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+ ((INSTANCE) == GPIOB) || \
+ ((INSTANCE) == GPIOC) || \
+ ((INSTANCE) == GPIOD) || \
+ ((INSTANCE) == GPIOE) || \
+ ((INSTANCE) == GPIOH))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C2) || \
+ ((INSTANCE) == I2C3))
+
+/****************** I2C Instances : wakeup capability from stop modes *********/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C3))
+
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
+
+/******************************** SMBUS Instances *****************************/
+#define IS_SMBUS_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+ ((INSTANCE) == I2C3))
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+ ((INSTANCE) == SPI2))
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/************* LPTIM instances supporting the encoder mode feature ************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+ (((((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3)) \
+ && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))) \
+ || \
+ (((INSTANCE) == TIM21) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))) \
+ || \
+ (((INSTANCE) == TIM22) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2))))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/***************** TIM Instances : external trigger input availabe ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM6) || \
+ ((INSTANCE) == TIM7) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM21) || \
+ ((INSTANCE) == TIM22))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
+
+/******************* TIM Instances : output(s) OCXEC register *****************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+/****************************** TSC Instances *********************************/
+#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART4) || \
+ ((INSTANCE) == USART5))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART4) || \
+ ((INSTANCE) == USART5))
+
+/****************** USART Instances : Auto Baud Rate detection ****************/
+
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/****************** UART Instances : Driver Enable *****************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART4) || \
+ ((INSTANCE) == USART5) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART4) || \
+ ((INSTANCE) == USART5) || \
+ ((INSTANCE) == LPUART1))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** UART Instances : Wake-up from Stop mode **********************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == LPUART1))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2) || \
+ ((INSTANCE) == USART4) || \
+ ((INSTANCE) == USART5) || \
+ ((INSTANCE) == LPUART1))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+ ((INSTANCE) == USART2))
+
+/******************** LPUART Instance *****************************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
+
+/******************************* USB Instances *******************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+
+/****************************** LCD Instances ********************************/
+#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* For a painless codes migration between the STM32L0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32L0 Family */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+
+#define LPUART1_IRQn RNG_LPUART1_IRQn
+#define AES_LPUART1_IRQn RNG_LPUART1_IRQn
+#define AES_RNG_LPUART1_IRQn RNG_LPUART1_IRQn
+#define TIM6_IRQn TIM6_DAC_IRQn
+#define RCC_IRQn RCC_CRS_IRQn
+#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
+#define ADC1_IRQn ADC1_COMP_IRQn
+
+/* Aliases for __IRQHandler */
+#define LPUART1_IRQHandler RNG_LPUART1_IRQHandler
+#define AES_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
+#define AES_RNG_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
+#define TIM6_IRQHandler TIM6_DAC_IRQHandler
+#define RCC_IRQHandler RCC_CRS_IRQHandler
+#define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
+#define ADC1_IRQHandler ADC1_COMP_IRQHandler
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L073xx_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/CMSIS/device/stm32l081xx.h b/CMSIS/device/stm32l081xx.h
new file mode 100644
index 0000000..65ce0d2
--- /dev/null
+++ b/CMSIS/device/stm32l081xx.h
@@ -0,0 +1,6637 @@
+/**
+ ******************************************************************************
+ * @file stm32l081xx.h
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for stm32l081xx devices.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral's registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright(c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l081xx
+ * @{
+ */
+
+#ifndef __STM32L081xx_H
+#define __STM32L081xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+/**
+ * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */
+#define __MPU_PRESENT 1U /*!< STM32L0xx provides an MPU */
+#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
+#define __NVIC_PRIO_BITS 2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief stm32l081xx Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+
+/*!< Interrupt Number Definition */
+typedef enum
+{
+/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
+
+/****** STM32L-0 specific Interrupt Numbers *********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */
+ RCC_IRQn = 4, /*!< RCC Interrupt */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
+ ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
+ LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
+ USART4_5_IRQn = 14, /*!< USART4 and USART5 Interrupt */
+ TIM2_IRQn = 15, /*!< TIM2 Interrupt */
+ TIM3_IRQn = 16, /*!< TIM3 Interrupt */
+ TIM6_IRQn = 17, /*!< TIM6 Interrupt */
+ TIM7_IRQn = 18, /*!< TIM7 Interrupt */
+ TIM21_IRQn = 20, /*!< TIM21 Interrupt */
+ I2C3_IRQn = 21, /*!< I2C3 Interrupt */
+ TIM22_IRQn = 22, /*!< TIM22 Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */
+ I2C2_IRQn = 24, /*!< I2C2 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ SPI2_IRQn = 26, /*!< SPI2 Interrupt */
+ USART1_IRQn = 27, /*!< USART1 Interrupt */
+ USART2_IRQn = 28, /*!< USART2 Interrupt */
+ AES_LPUART1_IRQn = 29, /*!< AES and LPUART1 Interrupts */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm0plus.h"
+#include "system_stm32l0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
+ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
+ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
+ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
+ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
+ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
+ uint32_t RESERVED3; /*!< Reserved, 0x24 */
+ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
+ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
+ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
+ uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CCR;
+} ADC_Common_TypeDef;
+
+/**
+ * @brief AES hardware accelerator
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
+ __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
+ __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
+ __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
+ __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
+ __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
+ __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
+ __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
+ __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
+ __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
+ __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
+} AES_TypeDef;
+
+/**
+ * @brief Comparator
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
+} COMP_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+
+/**
+* @brief CRC calculation unit
+*/
+
+typedef struct
+{
+__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+uint8_t RESERVED0; /*!< Reserved, 0x05 */
+uint16_t RESERVED1; /*!< Reserved, 0x06 */
+__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+uint32_t RESERVED2; /*!< Reserved, 0x0C */
+__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
+} DMA_Request_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+typedef struct
+{
+ __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
+ __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
+ __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
+ __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
+ __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
+ __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
+ __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
+ __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
+ __IO uint32_t RESERVED1[23]; /*!< Reserved1, Address offset: 0x24 */
+ __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */
+} FLASH_TypeDef;
+
+
+/**
+ * @brief Option Bytes Registers
+ */
+typedef struct
+{
+ __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
+ __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
+ __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
+ __IO uint32_t WRP23; /*!< write protection Bytes 2 and 3 Address offset: 0x0C */
+ __IO uint32_t WRP45; /*!< write protection Bytes 4 and 5 Address offset: 0x10 */
+} OB_TypeDef;
+
+
+/**
+ * @brief General Purpose IO
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+}GPIO_TypeDef;
+
+/**
+ * @brief LPTIMIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+} LPTIM_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
+ __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
+} SYSCFG_TypeDef;
+
+
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/**
+ * @brief Independent WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief MIFARE Firewall
+ */
+typedef struct
+{
+ __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
+ __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
+ __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
+ __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
+ __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
+ __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
+ __IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x18 */
+ __IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */
+ __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
+
+} FIREWALL_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
+ __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
+ __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
+ __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
+ __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
+ __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
+ __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
+ __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
+ __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
+ __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
+ __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */
+
+#define DATA_EEPROM_BASE (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
+#define DATA_EEPROM_BANK2_BASE (0x08080C00UL) /*!< DATA EEPROM BANK2 base address in the alias region */
+#define DATA_EEPROM_BANK1_END (0x08080BFFUL) /*!< Program end DATA EEPROM BANK1 address */
+#define DATA_EEPROM_BANK2_END (0x080817FFUL) /*!< Program end DATA EEPROM BANK2 address */
+#define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */
+#define SRAM_SIZE_MAX (0x00005000UL) /*!< maximum SRAM size (up to 20KBytes) */
+
+#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE PERIPH_BASE
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000UL)
+
+#define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL)
+#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL)
+#define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL)
+#define TIM7_BASE (APBPERIPH_BASE + 0x00001400UL)
+#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
+#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
+#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
+#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL)
+#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
+#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800UL)
+#define USART4_BASE (APBPERIPH_BASE + 0x00004C00UL)
+#define USART5_BASE (APBPERIPH_BASE + 0x00005000UL)
+#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
+#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL)
+#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
+#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL)
+#define I2C3_BASE (APBPERIPH_BASE + 0x00007800UL)
+
+#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
+#define COMP1_BASE (APBPERIPH_BASE + 0x00010018UL)
+#define COMP2_BASE (APBPERIPH_BASE + 0x0001001CUL)
+#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
+#define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL)
+#define TIM21_BASE (APBPERIPH_BASE + 0x00010800UL)
+#define TIM22_BASE (APBPERIPH_BASE + 0x00011400UL)
+#define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00UL)
+#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
+#define ADC_BASE (APBPERIPH_BASE + 0x00012708UL)
+#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
+#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL)
+#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL)
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
+#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL)
+
+
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */
+#define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */
+#define FLASHSIZE_BASE (0x1FF8007CUL) /*!< FLASH Size register base address */
+#define UID_BASE (0x1FF80050UL) /*!< Unique device ID register base address */
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
+#define AES_BASE (AHBPERIPH_BASE + 0x00006000UL)
+
+#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL)
+#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL)
+#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL)
+#define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00UL)
+#define GPIOE_BASE (IOPPERIPH_BASE + 0x00001000UL)
+#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00UL)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define USART4 ((USART_TypeDef *) USART4_BASE)
+#define USART5 ((USART_TypeDef *) USART5_BASE)
+
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
+#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
+#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
+/* Legacy defines */
+#define ADC ADC1_COMMON
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define AES ((AES_TypeDef *) AES_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+ /** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for ADC_ISR register ******************/
+#define ADC_ISR_EOCAL_Pos (11U)
+#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
+#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */
+#define ADC_ISR_AWD_Pos (7U)
+#define ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */
+#define ADC_ISR_EOSEQ_Pos (3U)
+#define ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS ADC_ISR_EOSEQ
+
+/******************** Bits definition for ADC_IER register ******************/
+#define ADC_IER_EOCALIE_Pos (11U)
+#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
+#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */
+#define ADC_IER_AWDIE_Pos (7U)
+#define ADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE_Pos (3U)
+#define ADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE ADC_IER_EOSEQIE
+
+/******************** Bits definition for ADC_CR register *******************/
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */
+
+/******************* Bits definition for ADC_CFGR1 register *****************/
+#define ADC_CFGR1_AWDCH_Pos (26U)
+#define ADC_CFGR1_AWDCH_Msk (0x1FUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR1_AWDCH_4 (0x10UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */
+#define ADC_CFGR1_AWDEN_Pos (23U)
+#define ADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */
+#define ADC_CFGR1_AWDSGL_Pos (22U)
+#define ADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */
+#define ADC_CFGR1_DISCEN_Pos (16U)
+#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */
+#define ADC_CFGR1_AUTOFF_Pos (15U)
+#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
+#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */
+#define ADC_CFGR1_WAIT_Pos (14U)
+#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
+#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */
+#define ADC_CFGR1_CONT_Pos (13U)
+#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */
+#define ADC_CFGR1_OVRMOD_Pos (12U)
+#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */
+#define ADC_CFGR1_EXTEN_Pos (10U)
+#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
+#define ADC_CFGR1_EXTSEL_Pos (6U)
+#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
+#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
+#define ADC_CFGR1_ALIGN_Pos (5U)
+#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
+#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */
+#define ADC_CFGR1_RES_Pos (3U)
+#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
+#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */
+#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
+#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
+#define ADC_CFGR1_SCANDIR_Pos (2U)
+#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */
+#define ADC_CFGR1_DMACFG_Pos (1U)
+#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
+#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */
+#define ADC_CFGR1_DMAEN_Pos (0U)
+#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
+#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
+
+/******************* Bits definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_TOVS_Pos (9U)
+#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
+#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */
+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+#define ADC_CFGR2_OVSR_Pos (2U)
+#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */
+#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+#define ADC_CFGR2_OVSE_Pos (0U)
+#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */
+#define ADC_CFGR2_CKMODE_Pos (30U)
+#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
+#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */
+#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
+#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
+
+
+/****************** Bit definition for ADC_SMPR register ********************/
+#define ADC_SMPR_SMP_Pos (0U)
+#define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
+#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */
+#define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
+#define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
+#define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
+
+/* Legacy defines */
+#define ADC_SMPR_SMPR ADC_SMPR_SMP
+#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
+#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
+#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
+
+/******************* Bit definition for ADC_TR register ********************/
+#define ADC_TR_HT_Pos (16U)
+#define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
+#define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */
+#define ADC_TR_LT_Pos (0U)
+#define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */
+#define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */
+
+/****************** Bit definition for ADC_CHSELR register ******************/
+#define ADC_CHSELR_CHSEL_Pos (0U)
+#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
+#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */
+#define ADC_CHSELR_CHSEL18_Pos (18U)
+#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
+#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */
+#define ADC_CHSELR_CHSEL17_Pos (17U)
+#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
+#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */
+#define ADC_CHSELR_CHSEL15_Pos (15U)
+#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
+#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */
+#define ADC_CHSELR_CHSEL14_Pos (14U)
+#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
+#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */
+#define ADC_CHSELR_CHSEL13_Pos (13U)
+#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
+#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */
+#define ADC_CHSELR_CHSEL12_Pos (12U)
+#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
+#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */
+#define ADC_CHSELR_CHSEL11_Pos (11U)
+#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
+#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */
+#define ADC_CHSELR_CHSEL10_Pos (10U)
+#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
+#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */
+#define ADC_CHSELR_CHSEL9_Pos (9U)
+#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
+#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */
+#define ADC_CHSELR_CHSEL8_Pos (8U)
+#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
+#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */
+#define ADC_CHSELR_CHSEL7_Pos (7U)
+#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
+#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */
+#define ADC_CHSELR_CHSEL6_Pos (6U)
+#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
+#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */
+#define ADC_CHSELR_CHSEL5_Pos (5U)
+#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
+#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */
+#define ADC_CHSELR_CHSEL4_Pos (4U)
+#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
+#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */
+#define ADC_CHSELR_CHSEL3_Pos (3U)
+#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
+#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */
+#define ADC_CHSELR_CHSEL2_Pos (2U)
+#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
+#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */
+#define ADC_CHSELR_CHSEL1_Pos (1U)
+#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
+#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */
+#define ADC_CHSELR_CHSEL0_Pos (0U)
+#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
+#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA_Pos (0U)
+#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */
+
+/******************** Bit definition for ADC_CALFACT register ********************/
+#define ADC_CALFACT_CALFACT_Pos (0U)
+#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_LFMEN_Pos (25U)
+#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
+#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */
+#define ADC_CCR_TSEN_Pos (23U)
+#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */
+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+/******************************************************************************/
+/* */
+/* Advanced Encryption Standard (AES) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for AES_CR register *********************/
+#define AES_CR_EN_Pos (0U)
+#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */
+#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */
+#define AES_CR_DATATYPE_Pos (1U)
+#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */
+#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */
+#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */
+#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */
+
+#define AES_CR_MODE_Pos (3U)
+#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */
+#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */
+#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */
+#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */
+
+#define AES_CR_CHMOD_Pos (5U)
+#define AES_CR_CHMOD_Msk (0x3UL << AES_CR_CHMOD_Pos) /*!< 0x00000060 */
+#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */
+#define AES_CR_CHMOD_0 (0x1UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */
+#define AES_CR_CHMOD_1 (0x2UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */
+
+#define AES_CR_CCFC_Pos (7U)
+#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */
+#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */
+#define AES_CR_ERRC_Pos (8U)
+#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */
+#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */
+#define AES_CR_CCIE_Pos (9U)
+#define AES_CR_CCIE_Msk (0x1UL << AES_CR_CCIE_Pos) /*!< 0x00000200 */
+#define AES_CR_CCIE AES_CR_CCIE_Msk /*!< Computation Complete Interrupt Enable */
+#define AES_CR_ERRIE_Pos (10U)
+#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */
+#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */
+#define AES_CR_DMAINEN_Pos (11U)
+#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */
+#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< DMA ENable managing the data input phase */
+#define AES_CR_DMAOUTEN_Pos (12U)
+#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */
+#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< DMA Enable managing the data output phase */
+
+/******************* Bit definition for AES_SR register *********************/
+#define AES_SR_CCF_Pos (0U)
+#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */
+#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */
+#define AES_SR_RDERR_Pos (1U)
+#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */
+#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */
+#define AES_SR_WRERR_Pos (2U)
+#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */
+#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */
+
+/******************* Bit definition for AES_DINR register *******************/
+#define AES_DINR_Pos (0U)
+#define AES_DINR_Msk (0xFFFFUL << AES_DINR_Pos) /*!< 0x0000FFFF */
+#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */
+
+/******************* Bit definition for AES_DOUTR register ******************/
+#define AES_DOUTR_Pos (0U)
+#define AES_DOUTR_Msk (0xFFFFUL << AES_DOUTR_Pos) /*!< 0x0000FFFF */
+#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */
+
+/******************* Bit definition for AES_KEYR0 register ******************/
+#define AES_KEYR0_Pos (0U)
+#define AES_KEYR0_Msk (0xFFFFUL << AES_KEYR0_Pos) /*!< 0x0000FFFF */
+#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */
+
+/******************* Bit definition for AES_KEYR1 register ******************/
+#define AES_KEYR1_Pos (0U)
+#define AES_KEYR1_Msk (0xFFFFUL << AES_KEYR1_Pos) /*!< 0x0000FFFF */
+#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */
+
+/******************* Bit definition for AES_KEYR2 register ******************/
+#define AES_KEYR2_Pos (0U)
+#define AES_KEYR2_Msk (0xFFFFUL << AES_KEYR2_Pos) /*!< 0x0000FFFF */
+#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */
+
+/******************* Bit definition for AES_KEYR3 register ******************/
+#define AES_KEYR3_Pos (0U)
+#define AES_KEYR3_Msk (0xFFFFUL << AES_KEYR3_Pos) /*!< 0x0000FFFF */
+#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */
+
+/******************* Bit definition for AES_IVR0 register *******************/
+#define AES_IVR0_Pos (0U)
+#define AES_IVR0_Msk (0xFFFFUL << AES_IVR0_Pos) /*!< 0x0000FFFF */
+#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */
+
+/******************* Bit definition for AES_IVR1 register *******************/
+#define AES_IVR1_Pos (0U)
+#define AES_IVR1_Msk (0xFFFFUL << AES_IVR1_Pos) /*!< 0x0000FFFF */
+#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */
+
+/******************* Bit definition for AES_IVR2 register *******************/
+#define AES_IVR2_Pos (0U)
+#define AES_IVR2_Msk (0xFFFFUL << AES_IVR2_Pos) /*!< 0x0000FFFF */
+#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */
+
+/******************* Bit definition for AES_IVR3 register *******************/
+#define AES_IVR3_Pos (0U)
+#define AES_IVR3_Msk (0xFFFFUL << AES_IVR3_Pos) /*!< 0x0000FFFF */
+#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+/************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN_Pos (0U)
+#define COMP_CSR_COMP1EN_Msk (0x1UL << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */
+#define COMP_CSR_COMP1INNSEL_Pos (4U)
+#define COMP_CSR_COMP1INNSEL_Msk (0x3UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */
+#define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INNSEL_0 (0x1UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP1INNSEL_1 (0x2UL << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP1WM_Pos (8U)
+#define COMP_CSR_COMP1WM_Msk (0x1UL << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */
+#define COMP_CSR_COMP1LPTIM1IN1_Pos (12U)
+#define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP1POLARITY_Pos (15U)
+#define COMP_CSR_COMP1POLARITY_Msk (0x1UL << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1VALUE_Pos (30U)
+#define COMP_CSR_COMP1VALUE_Msk (0x1UL << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK_Pos (31U)
+#define COMP_CSR_COMP1LOCK_Msk (0x1UL << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN_Pos (0U)
+#define COMP_CSR_COMP2EN_Msk (0x1UL << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */
+#define COMP_CSR_COMP2SPEED_Pos (3U)
+#define COMP_CSR_COMP2SPEED_Msk (0x1UL << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */
+#define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */
+#define COMP_CSR_COMP2INNSEL_Pos (4U)
+#define COMP_CSR_COMP2INNSEL_Msk (0x7UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */
+#define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INNSEL_0 (0x1UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */
+#define COMP_CSR_COMP2INNSEL_1 (0x2UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */
+#define COMP_CSR_COMP2INNSEL_2 (0x4UL << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */
+#define COMP_CSR_COMP2INPSEL_Pos (8U)
+#define COMP_CSR_COMP2INPSEL_Msk (0x7UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */
+#define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */
+#define COMP_CSR_COMP2INPSEL_0 (0x1UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */
+#define COMP_CSR_COMP2INPSEL_1 (0x2UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */
+#define COMP_CSR_COMP2INPSEL_2 (0x4UL << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */
+#define COMP_CSR_COMP2LPTIM1IN2_Pos (12U)
+#define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */
+#define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */
+#define COMP_CSR_COMP2LPTIM1IN1_Pos (13U)
+#define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1UL << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */
+#define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */
+#define COMP_CSR_COMP2POLARITY_Pos (15U)
+#define COMP_CSR_COMP2POLARITY_Msk (0x1UL << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2VALUE_Pos (30U)
+#define COMP_CSR_COMP2VALUE_Msk (0x1UL << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK_Pos (31U)
+#define COMP_CSR_COMP2LOCK_Msk (0x1UL << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */
+
+/********************** Bit definition for COMP_CSR register common ****************/
+#define COMP_CSR_COMPxEN_Pos (0U)
+#define COMP_CSR_COMPxEN_Msk (0x1UL << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */
+#define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */
+#define COMP_CSR_COMPxPOLARITY_Pos (15U)
+#define COMP_CSR_COMPxPOLARITY_Msk (0x1UL << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */
+#define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */
+#define COMP_CSR_COMPxOUTVALUE_Pos (30U)
+#define COMP_CSR_COMPxOUTVALUE_Msk (0x1UL << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */
+#define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */
+#define COMP_CSR_COMPxLOCK_Pos (31U)
+#define COMP_CSR_COMPxLOCK_Msk (0x1UL << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */
+#define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */
+
+/* Reference defines */
+#define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR_Pos (0U)
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR (0xFFU) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET_Pos (0U)
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos (3U)
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos (5U)
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos (7U)
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
+
+/******************* Bit definition for CRC_INIT register *******************/
+#define CRC_INIT_INIT_Pos (0U)
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
+
+/******************* Bit definition for CRC_POL register ********************/
+#define CRC_POL_POL_Pos (0U)
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_Pos (0U)
+#define DBGMCU_CR_DBG_Msk (0x7UL << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */
+#define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos (1U)
+#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos (23U)
+#define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1_FZ_DBG_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U)
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
+#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1_Pos (0U)
+#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos (1U)
+#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos (2U)
+#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos (3U)
+#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos (4U)
+#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos (5U)
+#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos (6U)
+#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos (7U)
+#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos (8U)
+#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos (9U)
+#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos (10U)
+#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos (11U)
+#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos (12U)
+#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos (13U)
+#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos (14U)
+#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos (15U)
+#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos (16U)
+#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos (17U)
+#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos (18U)
+#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos (19U)
+#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos (20U)
+#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos (21U)
+#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos (22U)
+#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos (23U)
+#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos (24U)
+#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos (25U)
+#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos (26U)
+#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos (27U)
+#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1_Pos (0U)
+#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos (1U)
+#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos (2U)
+#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos (3U)
+#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos (4U)
+#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos (5U)
+#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos (6U)
+#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos (7U)
+#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos (8U)
+#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos (9U)
+#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos (10U)
+#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos (11U)
+#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos (12U)
+#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos (13U)
+#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos (14U)
+#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos (15U)
+#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos (16U)
+#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos (17U)
+#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos (18U)
+#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos (19U)
+#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos (20U)
+#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos (21U)
+#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos (22U)
+#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos (23U)
+#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos (24U)
+#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos (25U)
+#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos (26U)
+#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos (27U)
+#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR register ********************/
+#define DMA_CCR_EN_Pos (0U)
+#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
+#define DMA_CCR_TCIE_Pos (1U)
+#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos (2U)
+#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos (3U)
+#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos (4U)
+#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos (5U)
+#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
+#define DMA_CCR_PINC_Pos (6U)
+#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos (7U)
+#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos (8U)
+#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos (10U)
+#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos (12U)
+#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
+#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
+#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos (14U)
+#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CNDTR register *******************/
+#define DMA_CNDTR_NDT_Pos (0U)
+#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR register ********************/
+#define DMA_CPAR_PA_Pos (0U)
+#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR register ********************/
+#define DMA_CMAR_MA_Pos (0U)
+#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
+
+
+/******************* Bit definition for DMA_CSELR register *******************/
+#define DMA_CSELR_C1S_Pos (0U)
+#define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */
+#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */
+#define DMA_CSELR_C2S_Pos (4U)
+#define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */
+#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */
+#define DMA_CSELR_C3S_Pos (8U)
+#define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */
+#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */
+#define DMA_CSELR_C4S_Pos (12U)
+#define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */
+#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */
+#define DMA_CSELR_C5S_Pos (16U)
+#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
+#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
+#define DMA_CSELR_C6S_Pos (20U)
+#define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
+#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
+#define DMA_CSELR_C7S_Pos (24U)
+#define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
+#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_IM0_Pos (0U)
+#define EXTI_IMR_IM0_Msk (0x1UL << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */
+#define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_IM1_Pos (1U)
+#define EXTI_IMR_IM1_Msk (0x1UL << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */
+#define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_IM2_Pos (2U)
+#define EXTI_IMR_IM2_Msk (0x1UL << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */
+#define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_IM3_Pos (3U)
+#define EXTI_IMR_IM3_Msk (0x1UL << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */
+#define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_IM4_Pos (4U)
+#define EXTI_IMR_IM4_Msk (0x1UL << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */
+#define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_IM5_Pos (5U)
+#define EXTI_IMR_IM5_Msk (0x1UL << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */
+#define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_IM6_Pos (6U)
+#define EXTI_IMR_IM6_Msk (0x1UL << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */
+#define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_IM7_Pos (7U)
+#define EXTI_IMR_IM7_Msk (0x1UL << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */
+#define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_IM8_Pos (8U)
+#define EXTI_IMR_IM8_Msk (0x1UL << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */
+#define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_IM9_Pos (9U)
+#define EXTI_IMR_IM9_Msk (0x1UL << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */
+#define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_IM10_Pos (10U)
+#define EXTI_IMR_IM10_Msk (0x1UL << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */
+#define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_IM11_Pos (11U)
+#define EXTI_IMR_IM11_Msk (0x1UL << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */
+#define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_IM12_Pos (12U)
+#define EXTI_IMR_IM12_Msk (0x1UL << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */
+#define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_IM13_Pos (13U)
+#define EXTI_IMR_IM13_Msk (0x1UL << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */
+#define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_IM14_Pos (14U)
+#define EXTI_IMR_IM14_Msk (0x1UL << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */
+#define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_IM15_Pos (15U)
+#define EXTI_IMR_IM15_Msk (0x1UL << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */
+#define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_IM16_Pos (16U)
+#define EXTI_IMR_IM16_Msk (0x1UL << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */
+#define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_IM17_Pos (17U)
+#define EXTI_IMR_IM17_Msk (0x1UL << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */
+#define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_IM18_Pos (18U)
+#define EXTI_IMR_IM18_Msk (0x1UL << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */
+#define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_IM19_Pos (19U)
+#define EXTI_IMR_IM19_Msk (0x1UL << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */
+#define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_IM20_Pos (20U)
+#define EXTI_IMR_IM20_Msk (0x1UL << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */
+#define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_IM21_Pos (21U)
+#define EXTI_IMR_IM21_Msk (0x1UL << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */
+#define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_IM22_Pos (22U)
+#define EXTI_IMR_IM22_Msk (0x1UL << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */
+#define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_IM23_Pos (23U)
+#define EXTI_IMR_IM23_Msk (0x1UL << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */
+#define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR_IM24_Pos (24U)
+#define EXTI_IMR_IM24_Msk (0x1UL << EXTI_IMR_IM24_Pos) /*!< 0x01000000 */
+#define EXTI_IMR_IM24 EXTI_IMR_IM24_Msk /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR_IM25_Pos (25U)
+#define EXTI_IMR_IM25_Msk (0x1UL << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */
+#define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR_IM26_Pos (26U)
+#define EXTI_IMR_IM26_Msk (0x1UL << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */
+#define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR_IM28_Pos (28U)
+#define EXTI_IMR_IM28_Msk (0x1UL << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */
+#define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR_IM29_Pos (29U)
+#define EXTI_IMR_IM29_Msk (0x1UL << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */
+#define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */
+
+#define EXTI_IMR_IM_Pos (0U)
+#define EXTI_IMR_IM_Msk (0x37FFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x37FFFFFF */
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
+
+/****************** Bit definition for EXTI_EMR register ********************/
+#define EXTI_EMR_EM0_Pos (0U)
+#define EXTI_EMR_EM0_Msk (0x1UL << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */
+#define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */
+#define EXTI_EMR_EM1_Pos (1U)
+#define EXTI_EMR_EM1_Msk (0x1UL << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */
+#define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */
+#define EXTI_EMR_EM2_Pos (2U)
+#define EXTI_EMR_EM2_Msk (0x1UL << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */
+#define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */
+#define EXTI_EMR_EM3_Pos (3U)
+#define EXTI_EMR_EM3_Msk (0x1UL << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */
+#define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */
+#define EXTI_EMR_EM4_Pos (4U)
+#define EXTI_EMR_EM4_Msk (0x1UL << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */
+#define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */
+#define EXTI_EMR_EM5_Pos (5U)
+#define EXTI_EMR_EM5_Msk (0x1UL << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */
+#define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */
+#define EXTI_EMR_EM6_Pos (6U)
+#define EXTI_EMR_EM6_Msk (0x1UL << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */
+#define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */
+#define EXTI_EMR_EM7_Pos (7U)
+#define EXTI_EMR_EM7_Msk (0x1UL << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */
+#define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */
+#define EXTI_EMR_EM8_Pos (8U)
+#define EXTI_EMR_EM8_Msk (0x1UL << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */
+#define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */
+#define EXTI_EMR_EM9_Pos (9U)
+#define EXTI_EMR_EM9_Msk (0x1UL << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */
+#define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */
+#define EXTI_EMR_EM10_Pos (10U)
+#define EXTI_EMR_EM10_Msk (0x1UL << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */
+#define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */
+#define EXTI_EMR_EM11_Pos (11U)
+#define EXTI_EMR_EM11_Msk (0x1UL << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */
+#define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */
+#define EXTI_EMR_EM12_Pos (12U)
+#define EXTI_EMR_EM12_Msk (0x1UL << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */
+#define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */
+#define EXTI_EMR_EM13_Pos (13U)
+#define EXTI_EMR_EM13_Msk (0x1UL << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */
+#define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */
+#define EXTI_EMR_EM14_Pos (14U)
+#define EXTI_EMR_EM14_Msk (0x1UL << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */
+#define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */
+#define EXTI_EMR_EM15_Pos (15U)
+#define EXTI_EMR_EM15_Msk (0x1UL << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */
+#define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */
+#define EXTI_EMR_EM16_Pos (16U)
+#define EXTI_EMR_EM16_Msk (0x1UL << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */
+#define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */
+#define EXTI_EMR_EM17_Pos (17U)
+#define EXTI_EMR_EM17_Msk (0x1UL << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */
+#define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */
+#define EXTI_EMR_EM18_Pos (18U)
+#define EXTI_EMR_EM18_Msk (0x1UL << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */
+#define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */
+#define EXTI_EMR_EM19_Pos (19U)
+#define EXTI_EMR_EM19_Msk (0x1UL << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */
+#define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */
+#define EXTI_EMR_EM20_Pos (20U)
+#define EXTI_EMR_EM20_Msk (0x1UL << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */
+#define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */
+#define EXTI_EMR_EM21_Pos (21U)
+#define EXTI_EMR_EM21_Msk (0x1UL << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */
+#define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */
+#define EXTI_EMR_EM22_Pos (22U)
+#define EXTI_EMR_EM22_Msk (0x1UL << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */
+#define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */
+#define EXTI_EMR_EM23_Pos (23U)
+#define EXTI_EMR_EM23_Msk (0x1UL << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */
+#define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */
+#define EXTI_EMR_EM24_Pos (24U)
+#define EXTI_EMR_EM24_Msk (0x1UL << EXTI_EMR_EM24_Pos) /*!< 0x01000000 */
+#define EXTI_EMR_EM24 EXTI_EMR_EM24_Msk /*!< Event Mask on line 24 */
+#define EXTI_EMR_EM25_Pos (25U)
+#define EXTI_EMR_EM25_Msk (0x1UL << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */
+#define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */
+#define EXTI_EMR_EM26_Pos (26U)
+#define EXTI_EMR_EM26_Msk (0x1UL << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */
+#define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */
+#define EXTI_EMR_EM28_Pos (28U)
+#define EXTI_EMR_EM28_Msk (0x1UL << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */
+#define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */
+#define EXTI_EMR_EM29_Pos (29U)
+#define EXTI_EMR_EM29_Msk (0x1UL << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */
+#define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */
+
+/******************* Bit definition for EXTI_RTSR register ******************/
+#define EXTI_RTSR_RT0_Pos (0U)
+#define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */
+#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_RT1_Pos (1U)
+#define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */
+#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_RT2_Pos (2U)
+#define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */
+#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_RT3_Pos (3U)
+#define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */
+#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_RT4_Pos (4U)
+#define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */
+#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_RT5_Pos (5U)
+#define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */
+#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_RT6_Pos (6U)
+#define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */
+#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_RT7_Pos (7U)
+#define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */
+#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_RT8_Pos (8U)
+#define EXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */
+#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_RT9_Pos (9U)
+#define EXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */
+#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_RT10_Pos (10U)
+#define EXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */
+#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_RT11_Pos (11U)
+#define EXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */
+#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_RT12_Pos (12U)
+#define EXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */
+#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_RT13_Pos (13U)
+#define EXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */
+#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_RT14_Pos (14U)
+#define EXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */
+#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_RT15_Pos (15U)
+#define EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */
+#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_RT16_Pos (16U)
+#define EXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */
+#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_RT17_Pos (17U)
+#define EXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */
+#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_RT19_Pos (19U)
+#define EXTI_RTSR_RT19_Msk (0x1UL << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */
+#define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_RT20_Pos (20U)
+#define EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */
+#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_RT21_Pos (21U)
+#define EXTI_RTSR_RT21_Msk (0x1UL << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */
+#define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_RT22_Pos (22U)
+#define EXTI_RTSR_RT22_Msk (0x1UL << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */
+#define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
+#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
+#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
+#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
+#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
+#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
+#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
+#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
+#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
+#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
+#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
+#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
+#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
+#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
+#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
+#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
+#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
+#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
+#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
+#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
+#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
+#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
+
+/******************* Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_FT0_Pos (0U)
+#define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */
+#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_FT1_Pos (1U)
+#define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */
+#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_FT2_Pos (2U)
+#define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */
+#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_FT3_Pos (3U)
+#define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */
+#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_FT4_Pos (4U)
+#define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */
+#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_FT5_Pos (5U)
+#define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */
+#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_FT6_Pos (6U)
+#define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */
+#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_FT7_Pos (7U)
+#define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */
+#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_FT8_Pos (8U)
+#define EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */
+#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_FT9_Pos (9U)
+#define EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */
+#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_FT10_Pos (10U)
+#define EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */
+#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_FT11_Pos (11U)
+#define EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */
+#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_FT12_Pos (12U)
+#define EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */
+#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_FT13_Pos (13U)
+#define EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */
+#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_FT14_Pos (14U)
+#define EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */
+#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_FT15_Pos (15U)
+#define EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */
+#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_FT16_Pos (16U)
+#define EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */
+#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_FT17_Pos (17U)
+#define EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */
+#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_FT19_Pos (19U)
+#define EXTI_FTSR_FT19_Msk (0x1UL << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */
+#define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_FT20_Pos (20U)
+#define EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */
+#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_FT21_Pos (21U)
+#define EXTI_FTSR_FT21_Msk (0x1UL << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */
+#define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_FT22_Pos (22U)
+#define EXTI_FTSR_FT22_Msk (0x1UL << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */
+#define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
+
+/* Legacy defines */
+#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
+#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
+#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
+#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
+#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
+#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
+#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
+#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
+#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
+#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
+#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
+#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
+#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
+#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
+#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
+#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
+#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
+#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
+#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
+#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
+#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
+#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define EXTI_SWIER_SWI0_Pos (0U)
+#define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */
+#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWI1_Pos (1U)
+#define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */
+#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWI2_Pos (2U)
+#define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */
+#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWI3_Pos (3U)
+#define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */
+#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWI4_Pos (4U)
+#define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */
+#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWI5_Pos (5U)
+#define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */
+#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWI6_Pos (6U)
+#define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */
+#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWI7_Pos (7U)
+#define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */
+#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWI8_Pos (8U)
+#define EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */
+#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWI9_Pos (9U)
+#define EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */
+#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWI10_Pos (10U)
+#define EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */
+#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWI11_Pos (11U)
+#define EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */
+#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWI12_Pos (12U)
+#define EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */
+#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWI13_Pos (13U)
+#define EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */
+#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWI14_Pos (14U)
+#define EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */
+#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWI15_Pos (15U)
+#define EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */
+#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWI16_Pos (16U)
+#define EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */
+#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWI17_Pos (17U)
+#define EXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */
+#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWI19_Pos (19U)
+#define EXTI_SWIER_SWI19_Msk (0x1UL << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */
+#define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWI20_Pos (20U)
+#define EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */
+#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWI21_Pos (21U)
+#define EXTI_SWIER_SWI21_Msk (0x1UL << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */
+#define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWI22_Pos (22U)
+#define EXTI_SWIER_SWI22_Msk (0x1UL << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */
+#define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */
+
+/* Legacy defines */
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
+
+/****************** Bit definition for EXTI_PR register *********************/
+#define EXTI_PR_PIF0_Pos (0U)
+#define EXTI_PR_PIF0_Msk (0x1UL << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */
+#define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */
+#define EXTI_PR_PIF1_Pos (1U)
+#define EXTI_PR_PIF1_Msk (0x1UL << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */
+#define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */
+#define EXTI_PR_PIF2_Pos (2U)
+#define EXTI_PR_PIF2_Msk (0x1UL << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */
+#define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */
+#define EXTI_PR_PIF3_Pos (3U)
+#define EXTI_PR_PIF3_Msk (0x1UL << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */
+#define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */
+#define EXTI_PR_PIF4_Pos (4U)
+#define EXTI_PR_PIF4_Msk (0x1UL << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */
+#define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */
+#define EXTI_PR_PIF5_Pos (5U)
+#define EXTI_PR_PIF5_Msk (0x1UL << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */
+#define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */
+#define EXTI_PR_PIF6_Pos (6U)
+#define EXTI_PR_PIF6_Msk (0x1UL << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */
+#define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */
+#define EXTI_PR_PIF7_Pos (7U)
+#define EXTI_PR_PIF7_Msk (0x1UL << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */
+#define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */
+#define EXTI_PR_PIF8_Pos (8U)
+#define EXTI_PR_PIF8_Msk (0x1UL << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */
+#define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */
+#define EXTI_PR_PIF9_Pos (9U)
+#define EXTI_PR_PIF9_Msk (0x1UL << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */
+#define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */
+#define EXTI_PR_PIF10_Pos (10U)
+#define EXTI_PR_PIF10_Msk (0x1UL << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */
+#define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */
+#define EXTI_PR_PIF11_Pos (11U)
+#define EXTI_PR_PIF11_Msk (0x1UL << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */
+#define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */
+#define EXTI_PR_PIF12_Pos (12U)
+#define EXTI_PR_PIF12_Msk (0x1UL << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */
+#define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */
+#define EXTI_PR_PIF13_Pos (13U)
+#define EXTI_PR_PIF13_Msk (0x1UL << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */
+#define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */
+#define EXTI_PR_PIF14_Pos (14U)
+#define EXTI_PR_PIF14_Msk (0x1UL << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */
+#define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */
+#define EXTI_PR_PIF15_Pos (15U)
+#define EXTI_PR_PIF15_Msk (0x1UL << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */
+#define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */
+#define EXTI_PR_PIF16_Pos (16U)
+#define EXTI_PR_PIF16_Msk (0x1UL << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */
+#define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */
+#define EXTI_PR_PIF17_Pos (17U)
+#define EXTI_PR_PIF17_Msk (0x1UL << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */
+#define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */
+#define EXTI_PR_PIF19_Pos (19U)
+#define EXTI_PR_PIF19_Msk (0x1UL << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */
+#define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */
+#define EXTI_PR_PIF20_Pos (20U)
+#define EXTI_PR_PIF20_Msk (0x1UL << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */
+#define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */
+#define EXTI_PR_PIF21_Pos (21U)
+#define EXTI_PR_PIF21_Msk (0x1UL << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */
+#define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */
+#define EXTI_PR_PIF22_Pos (22U)
+#define EXTI_PR_PIF22_Msk (0x1UL << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */
+#define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */
+
+/* Legacy defines */
+#define EXTI_PR_PR0 EXTI_PR_PIF0
+#define EXTI_PR_PR1 EXTI_PR_PIF1
+#define EXTI_PR_PR2 EXTI_PR_PIF2
+#define EXTI_PR_PR3 EXTI_PR_PIF3
+#define EXTI_PR_PR4 EXTI_PR_PIF4
+#define EXTI_PR_PR5 EXTI_PR_PIF5
+#define EXTI_PR_PR6 EXTI_PR_PIF6
+#define EXTI_PR_PR7 EXTI_PR_PIF7
+#define EXTI_PR_PR8 EXTI_PR_PIF8
+#define EXTI_PR_PR9 EXTI_PR_PIF9
+#define EXTI_PR_PR10 EXTI_PR_PIF10
+#define EXTI_PR_PR11 EXTI_PR_PIF11
+#define EXTI_PR_PR12 EXTI_PR_PIF12
+#define EXTI_PR_PR13 EXTI_PR_PIF13
+#define EXTI_PR_PR14 EXTI_PR_PIF14
+#define EXTI_PR_PR15 EXTI_PR_PIF15
+#define EXTI_PR_PR16 EXTI_PR_PIF16
+#define EXTI_PR_PR17 EXTI_PR_PIF17
+#define EXTI_PR_PR19 EXTI_PR_PIF19
+#define EXTI_PR_PR20 EXTI_PR_PIF20
+#define EXTI_PR_PR21 EXTI_PR_PIF21
+#define EXTI_PR_PR22 EXTI_PR_PIF22
+
+/******************************************************************************/
+/* */
+/* FLASH and Option Bytes Registers */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY_Pos (0U)
+#define FLASH_ACR_LATENCY_Msk (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
+#define FLASH_ACR_PRFTEN_Pos (1U)
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_SLEEP_PD_Pos (3U)
+#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
+#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD_Pos (4U)
+#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
+#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
+#define FLASH_ACR_DISAB_BUF_Pos (5U)
+#define FLASH_ACR_DISAB_BUF_Msk (0x1UL << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */
+#define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */
+#define FLASH_ACR_PRE_READ_Pos (6U)
+#define FLASH_ACR_PRE_READ_Msk (0x1UL << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */
+#define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */
+
+/******************* Bit definition for FLASH_PECR register ******************/
+#define FLASH_PECR_PELOCK_Pos (0U)
+#define FLASH_PECR_PELOCK_Msk (0x1UL << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
+#define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK_Pos (1U)
+#define FLASH_PECR_PRGLOCK_Msk (0x1UL << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
+#define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK_Pos (2U)
+#define FLASH_PECR_OPTLOCK_Msk (0x1UL << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
+#define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG_Pos (3U)
+#define FLASH_PECR_PROG_Msk (0x1UL << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
+#define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
+#define FLASH_PECR_DATA_Pos (4U)
+#define FLASH_PECR_DATA_Msk (0x1UL << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
+#define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
+#define FLASH_PECR_FIX_Pos (8U)
+#define FLASH_PECR_FIX_Msk (0x1UL << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */
+#define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE_Pos (9U)
+#define FLASH_PECR_ERASE_Msk (0x1UL << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
+#define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
+#define FLASH_PECR_FPRG_Pos (10U)
+#define FLASH_PECR_FPRG_Msk (0x1UL << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
+#define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_PARALLBANK_Pos (15U)
+#define FLASH_PECR_PARALLBANK_Msk (0x1UL << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */
+#define FLASH_PECR_PARALLBANK FLASH_PECR_PARALLBANK_Msk /*!< Parallel Bank mode */
+#define FLASH_PECR_EOPIE_Pos (16U)
+#define FLASH_PECR_EOPIE_Msk (0x1UL << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
+#define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
+#define FLASH_PECR_ERRIE_Pos (17U)
+#define FLASH_PECR_ERRIE_Msk (0x1UL << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
+#define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
+#define FLASH_PECR_OBL_LAUNCH_Pos (18U)
+#define FLASH_PECR_OBL_LAUNCH_Msk (0x1UL << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
+#define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
+#define FLASH_PECR_HALF_ARRAY_Pos (19U)
+#define FLASH_PECR_HALF_ARRAY_Msk (0x1UL << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */
+#define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */
+#define FLASH_PECR_NZDISABLE_Pos (22U)
+#define FLASH_PECR_NZDISABLE_Msk (0x1UL << FLASH_PECR_NZDISABLE_Pos) /*!< 0x00400000 */
+#define FLASH_PECR_NZDISABLE FLASH_PECR_NZDISABLE_Msk /*!< Non-Zero check disable */
+
+/****************** Bit definition for FLASH_PDKEYR register ******************/
+#define FLASH_PDKEYR_PDKEYR_Pos (0U)
+#define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PEKEYR register ******************/
+#define FLASH_PEKEYR_PEKEYR_Pos (0U)
+#define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFUL << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PRGKEYR register ******************/
+#define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
+#define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFUL << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
+
+/****************** Bit definition for FLASH_OPTKEYR register ******************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY_Pos (0U)
+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
+#define FLASH_SR_EOP_Pos (1U)
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
+#define FLASH_SR_HVOFF_Pos (2U)
+#define FLASH_SR_HVOFF_Msk (0x1UL << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */
+#define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */
+#define FLASH_SR_READY_Pos (3U)
+#define FLASH_SR_READY_Msk (0x1UL << FLASH_SR_READY_Pos) /*!< 0x00000008 */
+#define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR_Pos (8U)
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
+#define FLASH_SR_PGAERR_Pos (9U)
+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR_Pos (10U)
+#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
+#define FLASH_SR_OPTVERR_Pos (11U)
+#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */
+#define FLASH_SR_RDERR_Pos (13U)
+#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
+#define FLASH_SR_NOTZEROERR_Pos (16U)
+#define FLASH_SR_NOTZEROERR_Msk (0x1UL << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */
+#define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */
+#define FLASH_SR_FWWERR_Pos (17U)
+#define FLASH_SR_FWWERR_Msk (0x1UL << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */
+#define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */
+
+/* Legacy defines */
+#define FLASH_SR_FWWER FLASH_SR_FWWERR
+#define FLASH_SR_ENHV FLASH_SR_HVOFF
+#define FLASH_SR_ENDHV FLASH_SR_HVOFF
+
+/****************** Bit definition for FLASH_OPTR register *******************/
+#define FLASH_OPTR_RDPROT_Pos (0U)
+#define FLASH_OPTR_RDPROT_Msk (0xFFUL << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */
+#define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */
+#define FLASH_OPTR_WPRMOD_Pos (8U)
+#define FLASH_OPTR_WPRMOD_Msk (0x1UL << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */
+#define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */
+#define FLASH_OPTR_BOR_LEV_Pos (16U)
+#define FLASH_OPTR_BOR_LEV_Msk (0xFUL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */
+#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OPTR_IWDG_SW_Pos (20U)
+#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */
+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */
+#define FLASH_OPTR_nRST_STOP_Pos (21U)
+#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */
+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */
+#define FLASH_OPTR_nRST_STDBY_Pos (22U)
+#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */
+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */
+#define FLASH_OPTR_BFB2_Pos (23U)
+#define FLASH_OPTR_BFB2_Msk (0x1UL << FLASH_OPTR_BFB2_Pos) /*!< 0x00800000 */
+#define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk /*!< BFB2 */
+#define FLASH_OPTR_USER_Pos (20U)
+#define FLASH_OPTR_USER_Msk (0x7UL << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */
+#define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */
+#define FLASH_OPTR_BOOT1_Pos (31U)
+#define FLASH_OPTR_BOOT1_Msk (0x1UL << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */
+#define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP_Pos (0U)
+#define FLASH_WRPR_WRP_Msk (0xFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
+#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODE0_Pos (0U)
+#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
+#define GPIO_MODER_MODE1_Pos (2U)
+#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
+#define GPIO_MODER_MODE2_Pos (4U)
+#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
+#define GPIO_MODER_MODE3_Pos (6U)
+#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
+#define GPIO_MODER_MODE4_Pos (8U)
+#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
+#define GPIO_MODER_MODE5_Pos (10U)
+#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
+#define GPIO_MODER_MODE6_Pos (12U)
+#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
+#define GPIO_MODER_MODE7_Pos (14U)
+#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
+#define GPIO_MODER_MODE8_Pos (16U)
+#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
+#define GPIO_MODER_MODE9_Pos (18U)
+#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
+#define GPIO_MODER_MODE10_Pos (20U)
+#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
+#define GPIO_MODER_MODE11_Pos (22U)
+#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
+#define GPIO_MODER_MODE12_Pos (24U)
+#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
+#define GPIO_MODER_MODE13_Pos (26U)
+#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
+#define GPIO_MODER_MODE14_Pos (28U)
+#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
+#define GPIO_MODER_MODE15_Pos (30U)
+#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
+
+/****************** Bit definition for GPIO_OTYPER register *****************/
+#define GPIO_OTYPER_OT_0 (0x00000001U)
+#define GPIO_OTYPER_OT_1 (0x00000002U)
+#define GPIO_OTYPER_OT_2 (0x00000004U)
+#define GPIO_OTYPER_OT_3 (0x00000008U)
+#define GPIO_OTYPER_OT_4 (0x00000010U)
+#define GPIO_OTYPER_OT_5 (0x00000020U)
+#define GPIO_OTYPER_OT_6 (0x00000040U)
+#define GPIO_OTYPER_OT_7 (0x00000080U)
+#define GPIO_OTYPER_OT_8 (0x00000100U)
+#define GPIO_OTYPER_OT_9 (0x00000200U)
+#define GPIO_OTYPER_OT_10 (0x00000400U)
+#define GPIO_OTYPER_OT_11 (0x00000800U)
+#define GPIO_OTYPER_OT_12 (0x00001000U)
+#define GPIO_OTYPER_OT_13 (0x00002000U)
+#define GPIO_OTYPER_OT_14 (0x00004000U)
+#define GPIO_OTYPER_OT_15 (0x00008000U)
+
+/**************** Bit definition for GPIO_OSPEEDR register ******************/
+#define GPIO_OSPEEDER_OSPEED0_Pos (0U)
+#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk
+#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */
+#define GPIO_OSPEEDER_OSPEED1_Pos (2U)
+#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk
+#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */
+#define GPIO_OSPEEDER_OSPEED2_Pos (4U)
+#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk
+#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */
+#define GPIO_OSPEEDER_OSPEED3_Pos (6U)
+#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk
+#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */
+#define GPIO_OSPEEDER_OSPEED4_Pos (8U)
+#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk
+#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */
+#define GPIO_OSPEEDER_OSPEED5_Pos (10U)
+#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk
+#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */
+#define GPIO_OSPEEDER_OSPEED6_Pos (12U)
+#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk
+#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */
+#define GPIO_OSPEEDER_OSPEED7_Pos (14U)
+#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk
+#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */
+#define GPIO_OSPEEDER_OSPEED8_Pos (16U)
+#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk
+#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */
+#define GPIO_OSPEEDER_OSPEED9_Pos (18U)
+#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk
+#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */
+#define GPIO_OSPEEDER_OSPEED10_Pos (20U)
+#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk
+#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */
+#define GPIO_OSPEEDER_OSPEED11_Pos (22U)
+#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk
+#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */
+#define GPIO_OSPEEDER_OSPEED12_Pos (24U)
+#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk
+#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */
+#define GPIO_OSPEEDER_OSPEED13_Pos (26U)
+#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk
+#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */
+#define GPIO_OSPEEDER_OSPEED14_Pos (28U)
+#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk
+#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */
+#define GPIO_OSPEEDER_OSPEED15_Pos (30U)
+#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk
+#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPD0_Pos (0U)
+#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos (2U)
+#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos (4U)
+#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos (6U)
+#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos (8U)
+#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos (10U)
+#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos (12U)
+#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos (14U)
+#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos (16U)
+#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos (18U)
+#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos (20U)
+#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos (22U)
+#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos (24U)
+#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos (26U)
+#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos (28U)
+#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos (30U)
+#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
+
+/******************* Bit definition for GPIO_IDR register *******************/
+#define GPIO_IDR_ID0_Pos (0U)
+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos (1U)
+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos (2U)
+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos (3U)
+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos (4U)
+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos (5U)
+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos (6U)
+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos (7U)
+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos (8U)
+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos (9U)
+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos (10U)
+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos (11U)
+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos (12U)
+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos (13U)
+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos (14U)
+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos (15U)
+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
+
+/****************** Bit definition for GPIO_ODR register ********************/
+#define GPIO_ODR_OD0_Pos (0U)
+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos (1U)
+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos (2U)
+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos (3U)
+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos (4U)
+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos (5U)
+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos (6U)
+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos (7U)
+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos (8U)
+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos (9U)
+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos (10U)
+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos (11U)
+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos (12U)
+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos (13U)
+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos (14U)
+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos (15U)
+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
+
+/****************** Bit definition for GPIO_BSRR register ********************/
+#define GPIO_BSRR_BS_0 (0x00000001U)
+#define GPIO_BSRR_BS_1 (0x00000002U)
+#define GPIO_BSRR_BS_2 (0x00000004U)
+#define GPIO_BSRR_BS_3 (0x00000008U)
+#define GPIO_BSRR_BS_4 (0x00000010U)
+#define GPIO_BSRR_BS_5 (0x00000020U)
+#define GPIO_BSRR_BS_6 (0x00000040U)
+#define GPIO_BSRR_BS_7 (0x00000080U)
+#define GPIO_BSRR_BS_8 (0x00000100U)
+#define GPIO_BSRR_BS_9 (0x00000200U)
+#define GPIO_BSRR_BS_10 (0x00000400U)
+#define GPIO_BSRR_BS_11 (0x00000800U)
+#define GPIO_BSRR_BS_12 (0x00001000U)
+#define GPIO_BSRR_BS_13 (0x00002000U)
+#define GPIO_BSRR_BS_14 (0x00004000U)
+#define GPIO_BSRR_BS_15 (0x00008000U)
+#define GPIO_BSRR_BR_0 (0x00010000U)
+#define GPIO_BSRR_BR_1 (0x00020000U)
+#define GPIO_BSRR_BR_2 (0x00040000U)
+#define GPIO_BSRR_BR_3 (0x00080000U)
+#define GPIO_BSRR_BR_4 (0x00100000U)
+#define GPIO_BSRR_BR_5 (0x00200000U)
+#define GPIO_BSRR_BR_6 (0x00400000U)
+#define GPIO_BSRR_BR_7 (0x00800000U)
+#define GPIO_BSRR_BR_8 (0x01000000U)
+#define GPIO_BSRR_BR_9 (0x02000000U)
+#define GPIO_BSRR_BR_10 (0x04000000U)
+#define GPIO_BSRR_BR_11 (0x08000000U)
+#define GPIO_BSRR_BR_12 (0x10000000U)
+#define GPIO_BSRR_BR_13 (0x20000000U)
+#define GPIO_BSRR_BR_14 (0x40000000U)
+#define GPIO_BSRR_BR_15 (0x80000000U)
+
+/****************** Bit definition for GPIO_LCKR register ********************/
+#define GPIO_LCKR_LCK0_Pos (0U)
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos (1U)
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos (2U)
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos (3U)
+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos (4U)
+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos (5U)
+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos (6U)
+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos (7U)
+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos (8U)
+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos (9U)
+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos (10U)
+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos (11U)
+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos (12U)
+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos (13U)
+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos (14U)
+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos (15U)
+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos (16U)
+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register ********************/
+#define GPIO_AFRL_AFSEL0_Pos (0U)
+#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL1_Pos (4U)
+#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL2_Pos (8U)
+#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL3_Pos (12U)
+#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL4_Pos (16U)
+#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL5_Pos (20U)
+#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL6_Pos (24U)
+#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL7_Pos (28U)
+#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
+
+/****************** Bit definition for GPIO_AFRH register ********************/
+#define GPIO_AFRH_AFSEL8_Pos (0U)
+#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL9_Pos (4U)
+#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL10_Pos (8U)
+#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL11_Pos (12U)
+#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL12_Pos (16U)
+#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL13_Pos (20U)
+#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL14_Pos (24U)
+#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL15_Pos (28U)
+#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
+
+/****************** Bit definition for GPIO_BRR register *********************/
+#define GPIO_BRR_BR_0 (0x00000001U)
+#define GPIO_BRR_BR_1 (0x00000002U)
+#define GPIO_BRR_BR_2 (0x00000004U)
+#define GPIO_BRR_BR_3 (0x00000008U)
+#define GPIO_BRR_BR_4 (0x00000010U)
+#define GPIO_BRR_BR_5 (0x00000020U)
+#define GPIO_BRR_BR_6 (0x00000040U)
+#define GPIO_BRR_BR_7 (0x00000080U)
+#define GPIO_BRR_BR_8 (0x00000100U)
+#define GPIO_BRR_BR_9 (0x00000200U)
+#define GPIO_BRR_BR_10 (0x00000400U)
+#define GPIO_BRR_BR_11 (0x00000800U)
+#define GPIO_BRR_BR_12 (0x00001000U)
+#define GPIO_BRR_BR_13 (0x00002000U)
+#define GPIO_BRR_BR_14 (0x00004000U)
+#define GPIO_BRR_BR_15 (0x00008000U)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register *******************/
+#define I2C_CR1_PE_Pos (0U)
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos (1U)
+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos (2U)
+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos (3U)
+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos (4U)
+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos (5U)
+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos (6U)
+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos (7U)
+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos (8U)
+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos (12U)
+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos (14U)
+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos (15U)
+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos (16U)
+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos (17U)
+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos (18U)
+#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos (19U)
+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos (20U)
+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos (21U)
+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos (22U)
+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos (23U)
+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
+
+/****************** Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_SADD_Pos (0U)
+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos (10U)
+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos (11U)
+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos (12U)
+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos (13U)
+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
+#define I2C_CR2_STOP_Pos (14U)
+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos (15U)
+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos (16U)
+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos (24U)
+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos (25U)
+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos (26U)
+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
+
+/******************* Bit definition for I2C_OAR1 register ******************/
+#define I2C_OAR1_OA1_Pos (0U)
+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos (10U)
+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos (15U)
+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
+
+/******************* Bit definition for I2C_OAR2 register ******************/
+#define I2C_OAR2_OA2_Pos (1U)
+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos (8U)
+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos (8U)
+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos (9U)
+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos (8U)
+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos (10U)
+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos (8U)
+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos (9U)
+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos (8U)
+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos (15U)
+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
+
+/******************* Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos (0U)
+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos (8U)
+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos (16U)
+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos (20U)
+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos (28U)
+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
+
+/****************** Bit definition for I2C_ISR register *********************/
+#define I2C_ISR_TXE_Pos (0U)
+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos (1U)
+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos (2U)
+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos (3U)
+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos (4U)
+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos (5U)
+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos (6U)
+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos (7U)
+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos (8U)
+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
+#define I2C_ISR_ARLO_Pos (9U)
+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos (10U)
+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos (11U)
+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos (12U)
+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos (13U)
+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos (15U)
+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
+#define I2C_ISR_DIR_Pos (16U)
+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos (17U)
+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
+
+/****************** Bit definition for I2C_ICR register *********************/
+#define I2C_ICR_ADDRCF_Pos (3U)
+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos (4U)
+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos (5U)
+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos (8U)
+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos (9U)
+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos (10U)
+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos (11U)
+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos (12U)
+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos (13U)
+#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
+
+/****************** Bit definition for I2C_PECR register *********************/
+#define I2C_PECR_PEC_Pos (0U)
+#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
+
+/****************** Bit definition for I2C_RXDR register *********************/
+#define I2C_RXDR_RXDATA_Pos (0U)
+#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
+
+/****************** Bit definition for I2C_TXDR register *********************/
+#define I2C_TXDR_TXDATA_Pos (0U)
+#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY_Pos (0U)
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR_Pos (0U)
+#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
+#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
+#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL_Pos (0U)
+#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU_Pos (0U)
+#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos (1U)
+#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos (2U)
+#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_WINR_WIN_Pos (0U)
+#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/* */
+/* Low Power Timer (LPTTIM) */
+/* */
+/******************************************************************************/
+/****************** Bit definition for LPTIM_ISR register *******************/
+#define LPTIM_ISR_CMPM_Pos (0U)
+#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos (1U)
+#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos (2U)
+#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos (3U)
+#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos (4U)
+#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos (5U)
+#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos (6U)
+#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
+
+/****************** Bit definition for LPTIM_ICR register *******************/
+#define LPTIM_ICR_CMPMCF_Pos (0U)
+#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos (1U)
+#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos (3U)
+#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos (4U)
+#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos (5U)
+#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos (6U)
+#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
+
+/****************** Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos (0U)
+#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos (1U)
+#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos (3U)
+#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos (4U)
+#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos (5U)
+#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos (6U)
+#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
+
+/****************** Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos (0U)
+#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos (1U)
+#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos (3U)
+#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos (6U)
+#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos (9U)
+#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos (17U)
+#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos (19U)
+#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos (20U)
+#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos (21U)
+#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos (22U)
+#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos (24U)
+#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
+
+/****************** Bit definition for LPTIM_CR register ********************/
+#define LPTIM_CR_ENABLE_Pos (0U)
+#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos (1U)
+#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos (2U)
+#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
+
+/****************** Bit definition for LPTIM_CMP register *******************/
+#define LPTIM_CMP_CMP_Pos (0U)
+#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
+
+/****************** Bit definition for LPTIM_ARR register *******************/
+#define LPTIM_ARR_ARR_Pos (0U)
+#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
+
+/****************** Bit definition for LPTIM_CNT register *******************/
+#define LPTIM_CNT_CNT_Pos (0U)
+#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
+
+/******************************************************************************/
+/* */
+/* MIFARE Firewall */
+/* */
+/******************************************************************************/
+
+/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
+#define FW_CSSA_ADD_Pos (8U)
+#define FW_CSSA_ADD_Msk (0xFFFFUL << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */
+#define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */
+#define FW_CSL_LENG_Pos (8U)
+#define FW_CSL_LENG_Msk (0x3FFFUL << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */
+#define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */
+#define FW_NVDSSA_ADD_Pos (8U)
+#define FW_NVDSSA_ADD_Msk (0xFFFFUL << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */
+#define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */
+#define FW_NVDSL_LENG_Pos (8U)
+#define FW_NVDSL_LENG_Msk (0x3FFFUL << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */
+#define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */
+#define FW_VDSSA_ADD_Pos (6U)
+#define FW_VDSSA_ADD_Msk (0x3FFUL << FW_VDSSA_ADD_Pos) /*!< 0x0000FFC0 */
+#define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */
+#define FW_VDSL_LENG_Pos (6U)
+#define FW_VDSL_LENG_Msk (0x3FFUL << FW_VDSL_LENG_Pos) /*!< 0x0000FFC0 */
+#define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */
+
+/**************************Bit definition for CR register *********************/
+#define FW_CR_FPA_Pos (0U)
+#define FW_CR_FPA_Msk (0x1UL << FW_CR_FPA_Pos) /*!< 0x00000001 */
+#define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/
+#define FW_CR_VDS_Pos (1U)
+#define FW_CR_VDS_Msk (0x1UL << FW_CR_VDS_Pos) /*!< 0x00000002 */
+#define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/
+#define FW_CR_VDE_Pos (2U)
+#define FW_CR_VDE_Msk (0x1UL << FW_CR_VDE_Pos) /*!< 0x00000004 */
+#define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/
+
+/******************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/******************************************************************************/
+
+#define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPSDSR_Pos (0U)
+#define PWR_CR_LPSDSR_Msk (0x1UL << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
+#define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS_Pos (1U)
+#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
+#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos (2U)
+#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
+#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos (3U)
+#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
+#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos (4U)
+#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
+#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos (5U)
+#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
+#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */
+#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */
+#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
+
+#define PWR_CR_DBP_Pos (8U)
+#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
+#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP_Pos (9U)
+#define PWR_CR_ULP_Msk (0x1UL << PWR_CR_ULP_Pos) /*!< 0x00000200 */
+#define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
+#define PWR_CR_FWU_Pos (10U)
+#define PWR_CR_FWU_Msk (0x1UL << PWR_CR_FWU_Pos) /*!< 0x00000400 */
+#define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
+
+#define PWR_CR_VOS_Pos (11U)
+#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos) /*!< 0x00001800 */
+#define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0 (0x1UL << PWR_CR_VOS_Pos) /*!< 0x00000800 */
+#define PWR_CR_VOS_1 (0x2UL << PWR_CR_VOS_Pos) /*!< 0x00001000 */
+#define PWR_CR_DSEEKOFF_Pos (13U)
+#define PWR_CR_DSEEKOFF_Msk (0x1UL << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */
+#define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */
+#define PWR_CR_LPRUN_Pos (14U)
+#define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
+#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF_Pos (0U)
+#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
+#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos (1U)
+#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
+#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos (2U)
+#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
+#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF_Pos (3U)
+#define PWR_CSR_VREFINTRDYF_Msk (0x1UL << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
+#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF_Pos (4U)
+#define PWR_CSR_VOSF_Msk (0x1UL << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
+#define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF_Pos (5U)
+#define PWR_CSR_REGLPF_Msk (0x1UL << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
+#define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1_Pos (8U)
+#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
+#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2_Pos (9U)
+#define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
+#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP3_Pos (10U)
+#define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
+#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control */
+/* */
+/******************************************************************************/
+
+#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
+
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION_Pos (0U)
+#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
+#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos (1U)
+#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
+#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos (2U)
+#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIVEN_Pos (3U)
+#define RCC_CR_HSIDIVEN_Msk (0x1UL << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */
+#define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */
+#define RCC_CR_HSIDIVF_Pos (4U)
+#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */
+#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */
+#define RCC_CR_HSIOUTEN_Pos (5U)
+#define RCC_CR_HSIOUTEN_Msk (0x1UL << RCC_CR_HSIOUTEN_Pos) /*!< 0x00000020 */
+#define RCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_Msk /*!< Internal High Speed clock out enable */
+#define RCC_CR_MSION_Pos (8U)
+#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000100 */
+#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY_Pos (9U)
+#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
+#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
+#define RCC_CR_HSEON_Pos (16U)
+#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos (17U)
+#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos (18U)
+#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON_Pos (19U)
+#define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
+#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */
+#define RCC_CR_RTCPRE_Pos (20U)
+#define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
+#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */
+#define RCC_CR_RTCPRE_0 (0x1UL << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */
+#define RCC_CR_RTCPRE_1 (0x2UL << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */
+#define RCC_CR_PLLON_Pos (24U)
+#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos (25U)
+#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+
+/* Reference defines */
+#define RCC_CR_CSSON RCC_CR_CSSHSEON
+
+/******************** Bit definition for RCC_ICSCR register *****************/
+#define RCC_ICSCR_HSICAL_Pos (0U)
+#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
+#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM_Pos (8U)
+#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
+#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE_Pos (13U)
+#define RCC_ICSCR_MSIRANGE_Msk (0x7UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
+#define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0 (0x0UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
+#define RCC_ICSCR_MSIRANGE_1 (0x1UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
+#define RCC_ICSCR_MSIRANGE_2 (0x2UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
+#define RCC_ICSCR_MSIRANGE_3 (0x3UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
+#define RCC_ICSCR_MSIRANGE_4 (0x4UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
+#define RCC_ICSCR_MSIRANGE_5 (0x5UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
+#define RCC_ICSCR_MSIRANGE_6 (0x6UL << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
+#define RCC_ICSCR_MSICAL_Pos (16U)
+#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
+#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM_Pos (24U)
+#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
+#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
+
+
+/******************* Bit definition for RCC_CFGR register *******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos (0U)
+#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
+#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos (2U)
+#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos (4U)
+#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos (8U)
+#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
+
+#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos (11U)
+#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
+
+#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_STOPWUCK_Pos (15U)
+#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */
+#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */
+
+/*!< PLL entry clock source*/
+#define RCC_CFGR_PLLSRC_Pos (16U)
+#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
+
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL_Pos (18U)
+#define RCC_CFGR_PLLMUL_Msk (0xFUL << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 (0x1UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
+#define RCC_CFGR_PLLMUL_1 (0x2UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
+#define RCC_CFGR_PLLMUL_2 (0x4UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
+#define RCC_CFGR_PLLMUL_3 (0x8UL << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
+
+#define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV_Pos (22U)
+#define RCC_CFGR_PLLDIV_Msk (0x3UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0 (0x1UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV_1 (0x2UL << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
+
+#define RCC_CFGR_PLLDIV2_Pos (22U)
+#define RCC_CFGR_PLLDIV2_Msk (0x1UL << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3_Pos (23U)
+#define RCC_CFGR_PLLDIV3_Msk (0x1UL << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
+#define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4_Pos (22U)
+#define RCC_CFGR_PLLDIV4_Msk (0x3UL << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCOSEL_Pos (24U)
+#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
+#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
+
+#define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
+#define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
+#define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1UL << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCOSEL_HSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_HSI_Msk (0x1UL << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_MSI_Pos (24U)
+#define RCC_CFGR_MCOSEL_MSI_Msk (0x3UL << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
+#define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_HSE_Pos (26U)
+#define RCC_CFGR_MCOSEL_HSE_Msk (0x1UL << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCOSEL_PLL_Pos (24U)
+#define RCC_CFGR_MCOSEL_PLL_Msk (0x5UL << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
+#define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
+#define RCC_CFGR_MCOSEL_LSI_Pos (25U)
+#define RCC_CFGR_MCOSEL_LSI_Msk (0x3UL << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
+#define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
+#define RCC_CFGR_MCOSEL_LSE_Pos (24U)
+#define RCC_CFGR_MCOSEL_LSE_Msk (0x7UL << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
+
+#define RCC_CFGR_MCOPRE_Pos (28U)
+#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
+#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
+
+#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
+
+/* Legacy defines */
+#define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
+#define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
+#define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
+#define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
+#define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
+#define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
+#define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
+#define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
+#ifdef RCC_CFGR_MCOSEL_HSI48
+#define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48
+#endif
+
+#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
+#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
+
+/*!<****************** Bit definition for RCC_CIER register ********************/
+#define RCC_CIER_LSIRDYIE_Pos (0U)
+#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
+#define RCC_CIER_LSERDYIE_Pos (1U)
+#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
+#define RCC_CIER_HSIRDYIE_Pos (2U)
+#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
+#define RCC_CIER_HSERDYIE_Pos (3U)
+#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
+#define RCC_CIER_PLLRDYIE_Pos (4U)
+#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
+#define RCC_CIER_MSIRDYIE_Pos (5U)
+#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
+#define RCC_CIER_CSSLSE_Pos (7U)
+#define RCC_CIER_CSSLSE_Msk (0x1UL << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */
+
+/* Reference defines */
+#define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
+
+/*!<****************** Bit definition for RCC_CIFR register ********************/
+#define RCC_CIFR_LSIRDYF_Pos (0U)
+#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
+#define RCC_CIFR_LSERDYF_Pos (1U)
+#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
+#define RCC_CIFR_HSIRDYF_Pos (2U)
+#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
+#define RCC_CIFR_HSERDYF_Pos (3U)
+#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
+#define RCC_CIFR_PLLRDYF_Pos (4U)
+#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
+#define RCC_CIFR_MSIRDYF_Pos (5U)
+#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
+#define RCC_CIFR_CSSLSEF_Pos (7U)
+#define RCC_CIFR_CSSLSEF_Msk (0x1UL << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */
+#define RCC_CIFR_CSSHSEF_Pos (8U)
+#define RCC_CIFR_CSSHSEF_Msk (0x1UL << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */
+#define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */
+
+/* Reference defines */
+#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
+#define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
+
+/*!<****************** Bit definition for RCC_CICR register ********************/
+#define RCC_CICR_LSIRDYC_Pos (0U)
+#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
+#define RCC_CICR_LSERDYC_Pos (1U)
+#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
+#define RCC_CICR_HSIRDYC_Pos (2U)
+#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
+#define RCC_CICR_HSERDYC_Pos (3U)
+#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
+#define RCC_CICR_PLLRDYC_Pos (4U)
+#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
+#define RCC_CICR_MSIRDYC_Pos (5U)
+#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
+#define RCC_CICR_CSSLSEC_Pos (7U)
+#define RCC_CICR_CSSLSEC_Msk (0x1UL << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */
+#define RCC_CICR_CSSHSEC_Pos (8U)
+#define RCC_CICR_CSSHSEC_Msk (0x1UL << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */
+#define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */
+
+/* Reference defines */
+#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
+#define RCC_CICR_CSSC RCC_CICR_CSSHSEC
+/***************** Bit definition for RCC_IOPRSTR register ******************/
+#define RCC_IOPRSTR_IOPARST_Pos (0U)
+#define RCC_IOPRSTR_IOPARST_Msk (0x1UL << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */
+#define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */
+#define RCC_IOPRSTR_IOPBRST_Pos (1U)
+#define RCC_IOPRSTR_IOPBRST_Msk (0x1UL << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */
+#define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */
+#define RCC_IOPRSTR_IOPCRST_Pos (2U)
+#define RCC_IOPRSTR_IOPCRST_Msk (0x1UL << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */
+#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */
+#define RCC_IOPRSTR_IOPDRST_Pos (3U)
+#define RCC_IOPRSTR_IOPDRST_Msk (0x1UL << RCC_IOPRSTR_IOPDRST_Pos) /*!< 0x00000008 */
+#define RCC_IOPRSTR_IOPDRST RCC_IOPRSTR_IOPDRST_Msk /*!< GPIO port D reset */
+#define RCC_IOPRSTR_IOPERST_Pos (4U)
+#define RCC_IOPRSTR_IOPERST_Msk (0x1UL << RCC_IOPRSTR_IOPERST_Pos) /*!< 0x00000010 */
+#define RCC_IOPRSTR_IOPERST RCC_IOPRSTR_IOPERST_Msk /*!< GPIO port E reset */
+#define RCC_IOPRSTR_IOPHRST_Pos (7U)
+#define RCC_IOPRSTR_IOPHRST_Msk (0x1UL << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */
+#define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */
+
+/* Reference defines */
+#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!<